Questions tagged [jitter]

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Jitter measurement

I want to make a jitter measurement for the PWM output of this STM32F302R8 Nucelo board. Its datasheet is given here. By jitter I mean the histogram of pulse periods which shows how the periods vary ...
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Loop Filter Bandpass Jitter Characteristic in PLL

I was watching some PLL video lectures by Professor Elad Alon, and he explains why intuitively the jitter transfer function of the loop filter to the PLL output has a bandpass characteristic. He says ...
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How to interpolate phase noise curves?

I am trying to calculate the phase jitter of a transmitter. A phase noise profile is given, say: ...
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Phase noise and RMS jitter scaling with frequency

The phase noise plot for a particular crystal oscillator is here. The datasheet represents an entire series of oscillators which range in frequency from 1 to 75MHz. The phase noise plot is indicated ...
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Calculating peak period jitter from datasheet that lists phase noise

The oscillator I plan on using list phase noise for a 20MHZ signal as: (100Hz) -124 dBc/Hz (1kHz) -140 dBc/Hz (10kHz) -148 dBc/Hz 100kHz -155 dBc/Hz (1MHz) -157 dBc/...
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Microcontroller Power Transient Voltage Spike

First of all thanks for even taking your time to read this question. We are hoping someone can help assist us with an issue we have been having. We are currently working on an automotive tail light ...
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Table jitter on 40 ft planer mill at certain low feedrates with new 40 hp 3-phase motor and 50 hp ABB drive

The display on the drive shows 26 amps with little variation at all speeds. At 176.14 RPM it shows -9.2% motor torque, 25.63 amps. At 977 RPM it shows 26.04 amps and 2.4% torque. The motor spec ...
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Driving Delta-Sigma ADC with reference clock output from MCU

I am sending out the PB clock (32MHz which is PLL multiplied) generated from the internal FRC on a pin to feed into an ADC as a master clock after probing it at 32MHz. This is what I see. It doesn't ...
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Output Jitter of jittery bitstream through flipflop

I have a bitstream of about 10-20 MHz coming out of an FPGA, that is obtained by Delta Sigma modulation. This bitstream is expectedly very jittery and can not be passed directly through an analog ...
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3 votes
1 answer
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Clock jitter - ppm, ui, ps

I using Xilinx FPGA and need to use its PLL (MMCM or Clk Wizard) I have on my board LVDS 200MHz clock with 50 ppm frequency jitter, I took this and go to some converted I can find on the internet and ...
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3 answers
218 views

DIY reference clock jitter / Allan deviation measurement

I am considering doing some recreational timing. I have few OCXO's, GPSDO, Rb source - but no way to compare their stability / jitter. Majority of sources are around 10Mhz. Is there any DIY-friendly ...
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How do a generate a clean, precise pulse wave electronically without jitter?

I am trying to build a simple pulse generator circuit for electrophysiological stimulation purposes. It seems to be surprisingly difficult to generate a square/ pulse waveform where the pulses have ...
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2 votes
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232 views

STM32 Timer Discrete Jitter

I'm using a STM32F746 running at 200MHz. A timer (tim2) is counting up at 100MHz and triggers an update interrupt with the following simplified ISR that writes a pattern to GPIOB ...
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What causes a potentiometer to get "jittery" after cleaning?

I recently cleaned a potentiometer's resistive element by using general purpose contact cleaner (CRC). I now find that there is "jitter" or non-linear increase in the resistance as I rotate ...
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Typical rms values for random jitter in satellite communication

I'm trying to find typical values for random jitter in satellite communication and I'm not really finding any values in any documents. Most of the time I only find definitions for different jitter ...
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1 answer
448 views

Does dividing a clock increase its jitter?

I want to have my microcontroller and ADC using a clock derived from the same source in an effort to avoid intermodulation effects. All clocks are under 50 MHz. The maximum SNR out of an ADC is ...
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Servo doesn't move properly

I have a problem with my servo motor. I connected a servo to the PWA connection of a PCA9685, but powered the motor externally. There's no problem with that and it works fine with some smaller servo ...
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RMS phase jitter, not sure the right formula

In derivation of IPN power we normally approximate the area under the noise curve by dividing the area into trapezoids, where each trapezoid represents a specific region. The following plot is one ...
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Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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2 votes
2 answers
880 views

CPLD based Pierce oscillator

I want to make a clock generator for Altera EPM240T100C5N using the CPLD itself as a Pierce oscillator. This CPLD has Schmitt trigger inputs so I guess this should be possible. What I`m not sure about ...
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1 answer
730 views

What can be the cause for the servo to jitter continuously while powered?

I'm using an HS-785HB servo (https://www.robotshop.com/media/files/pdf/hs-785hb.pdf) for my project. I'm working on the Mbed platform and it uses C++. The servo library I use is Servo.h and I'm ...
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2 votes
1 answer
254 views

PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
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74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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5 votes
7 answers
3k views

Sub microsecond jitter accuracy - what to use?

I have four TTL level signals that must change state in a particular order. From the “go” signal on one of the lines, all toggling of the other lines will be done within 100 us. The other three ...
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4 votes
1 answer
274 views

Can phase noise be averaged out?

I have an ADC sampling a downconverted RF signal at fs. I obtain N=2^15 samples of the RF input signal "fcarrier + fs/10". The more I average, the more the entire noise floor shifts down (as expected,...
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4 answers
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Jitter in 'ppm' and 'ns'

In many datasheets clock tolerance is in ppm and in some other it is in ns or ps. What is the difference in giving clock tolerance in ppm and ns/ps. How it can be converted from one unit to another?
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Jitter measurement in High speed serial link - Random jitter mean not 0

I made some jitter measurements of my high speed serial link yesterday. Now i'm analysing the jitter sources, and found out, my random jitter is often not around zero, most time about -1 .. -0.5ps. ...
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3 votes
1 answer
2k views

How does retiming flip flop work?

I found the following circuit which acts as a "retiming flip flop". A similar version exists which uses the CLEAR (instead or PRESET input), data tied to VCC (instead of GND) and output taken from \$Q\...
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1 answer
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What does "1.2 psrms integrated jitter" mean?

What does "1.2 psrms integrated jitter" mean? What is "psrm" as a unit for jitter? and how is it calculated? and does a unit interval differ from circuit to circuit?
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2 answers
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How create a high precision clock in an FPGA?

FPGAs can easily run at 100 to 500 MHz and create time resolutions of 10 to 2 ns. That frequency can be used to create timestamp counters, which are in turn used to create very fine grained time ...
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4 votes
1 answer
163 views

A capacitor as loop filter of a DLL

I know that if a second order, type two PLL has only a capacitor as its loop filter, it is unstable because its phase margin would be zero. but why is it ok for a DLL to only have a capacitor as its ...
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1 answer
536 views

Error with phase noise to jitter calculation

I'm trying to get the jitter for an oscillator. The nominal frequency \$f_0\$ is 10 MHz, I'm integrating from 1 Hz to 100 kHz. The specifications are given as "RF Output Phase Noise (SSB)", in dBc/Hz. ...
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1 answer
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Poor man's clock MUX with an LVDS input

I want to send two different 10MHz clock signals to a device. My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC. The first source have ...
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2 answers
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Jitter Measurement Equipment

I'm looking into measuring clock signal jitters in the range of 50 to 100 ps peak-peak, at clock frequencies up to 250 MHz. What kind of measurement equipment do I need for that? A super fast ...
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3 votes
1 answer
610 views

Period Jitter vs. Phase Jitter

I've got an oscillator spec that states an RMS period jitter of 1.7 ps and an RMS phase jitter of 0.85 ps. I know that period jitter describes the deviations from the oscillator's average period over ...
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1 vote
2 answers
369 views

Clock Tree Jitter Estimation

How do I estimate the output jitter of a clock tree consisting of a clock oscillator followed by a clock buffer? The components have the following jitter characteristics: The clock oscillator has a ...
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1 vote
4 answers
615 views

clock oscillator substitution, jitter question (audio DAC)

I need a 5 x 7 mm HCMOS clock oscillator for my hifi audio DAC (Texas Instruments PCM5122) I used to employ the following oscillator: FXO-HC736R-22.5792, but it is now discontinued, and the suggested ...
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1 vote
1 answer
765 views

Would a long chain of inverters induce jitter?

I've recently designed a high-speed driver with the clock working at a highest frequency of 10GHz.But as the clock period becomes shorter,I've found that jitter situation too serious to be ignored. ...
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2 votes
2 answers
166 views

LPDDR2 clock long term jitter issue

I have a problem with LPDDR2 clock period cumulative error measurement tERR(11-50per) but shorter length measurement are OK with some margin. I'm looking at some cause or tips to understand or fix ...
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Has anyone ever seen a (ring oscillator) circuit like this?

I first designed this using NT Multisim 14 and the simulation worked. Then I built it with breadboard but used NTE101 Germanium transistors instead of 2N3904 silicon transistors. When I tested it I ...
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2 votes
1 answer
501 views

In which physical unit is 'clock drift' measured?

I would like to model a clock signal with an drift parameter in my digital simulation. The current implementation handles: frequency / period phase -360.0 .. 360.0 degree duty cycle 0.0 .. 1.0 ...
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1 vote
1 answer
535 views

What could be the source of this sine wave distortion, visible as equally spaced lines in FFT?

I have an MCU controlling a 16bit DAC via SPI (and an additional LDAC output, which triggers the update of the DAC output). The MCU has a precalculated 1120Hz sine wave in a 364-byte long buffer (all ...
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2 answers
3k views

Calculate jitter of oscillator from PPM

I found oscillators with from 10ppm up to 50ppm and more, but how I can calulate maximum jitter of this oscillators? With an online calculator I've found with 40Mhz and 50ppm this value: 2.500e-12s ...
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  • 607
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1 answer
553 views

Clock distribution for low-jitter audio DAC

I am building a 10-channel audio DAC using 10 ES9018 converters and an ultra low phase noise clock (Pulsar) with femtosecond jitter. What would be the best way to distribute the clock's signal to the ...
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1 vote
1 answer
595 views

PLL drift over time

I'm curious about this situation and how I would go about understanding it better. I have an input clock of 100Mhz with a maximum total jitter of 1ns. I want to put that into a pll to double the ...
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Frequency locked loop for input jitter rejection

I have an application where I want to multiply from a xtal oscillator at 32KHz to a system clock of 40MHz. A standard PLL isn't going to do the job, because the 32KHz jitter is measured in ns. Since ...
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2 answers
528 views

What is the jitter of an asynchronous FIFO?

I have an asynchronous FIFO (in a Stratix V FPGA) with two asynchronous read and write clocks of the same frequency of 100 MHz. As I understand, asynchronous FIFOs have a two-register ...
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0 votes
4 answers
423 views

Strange amplitude fluctuation in video signal

I am reading a video signal from a CCD array. For some reason I get this extreme vertical jitter. I use decoupling and bypass caps everywhere possible. But it does not seem to be the noise issue. Any ...
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4 votes
1 answer
486 views

What are the jitter characteristics of PLLs internal to Stratix V FPGAs?

I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
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2 votes
1 answer
326 views

What is the 1G Ethernet jitter requirements?

We have a Stratix V FPGA on which we want to run a 1G Ethernet PHY and MAC. Because we don't have a readily available 125MHz reference clock, we are considering using a PLL internal to the FPGA to ...
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