Questions tagged [jitter]
The jitter tag has no usage guidance.
2
votes
2answers
703 views
CPLD based Pierce oscillator
I want to make a clock generator for Altera EPM240T100C5N using the CPLD itself as a Pierce oscillator. This CPLD has Schmitt trigger inputs so I guess this should be possible. What I`m not sure about ...
0
votes
1answer
74 views
What can be the cause for the servo to jitter continuously while powered?
I'm using an HS-785HB servo (https://www.robotshop.com/media/files/pdf/hs-785hb.pdf) for my project.
I'm working on the Mbed platform and it uses C++.
The servo library I use is Servo.h and I'm ...
2
votes
1answer
65 views
PCIe Gen2 PLL lock issue
Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY.
This PHY's PLL requires a 100 MHz reference clock.
We are using the reference ...
0
votes
2answers
77 views
74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)
Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz
I have two options:
1) 74HC74 (CMOS ...
5
votes
7answers
3k views
Sub microsecond jitter accuracy - what to use?
I have four TTL level signals that must change state in a particular order.
From the “go” signal on one of the lines, all toggling of the other lines will be done within 100 us. The other three ...
1
vote
1answer
108 views
Can phase noise be averaged out?
I have an ADC sampling a downconverted RF signal at fs. I obtain N=2^15 samples of the RF input signal "fcarrier + fs/10".
The more I average, the more the entire noise floor shifts down (as expected,...
2
votes
4answers
841 views
Jitter in 'ppm' and 'ns'
In many datasheets clock tolerance is in ppm and in some other it is in ns or ps. What is the difference in giving clock tolerance in ppm and ns/ps. How it can be converted from one unit to another?
0
votes
1answer
64 views
Jitter measurement in High speed serial link - Random jitter mean not 0
I made some jitter measurements of my high speed serial link yesterday. Now i'm analysing the jitter sources, and found out, my random jitter is often not around zero, most time about -1 .. -0.5ps.
...
3
votes
1answer
577 views
How does retiming flip flop work?
I found the following circuit which acts as a "retiming flip flop". A similar version exists which uses the CLEAR (instead or PRESET input), data tied to VCC (instead of GND) and output taken from \$Q\...
0
votes
1answer
189 views
What does “1.2 psrms integrated jitter” mean?
What does "1.2 psrms integrated jitter" mean? What is "psrm" as a unit for jitter? and how is it calculated? and does a unit interval differ from circuit to circuit?
1
vote
2answers
752 views
How create a high precision clock in an FPGA?
FPGAs can easily run at 100 to 500 MHz and create time resolutions of 10 to 2 ns. That frequency can be used to create timestamp counters, which are in turn used to create very fine grained time ...
4
votes
1answer
118 views
A capacitor as loop filter of a DLL
I know that if a second order, type two PLL has only a capacitor as its loop filter, it is unstable because its phase margin would be zero. but why is it ok for a DLL to only have a capacitor as its ...
1
vote
1answer
108 views
Error with phase noise to jitter calculation
I'm trying to get the jitter for an oscillator. The nominal frequency \$f_0\$ is 10 MHz, I'm integrating from 1 Hz to 100 kHz.
The specifications are given as "RF Output Phase Noise (SSB)", in dBc/Hz.
...
0
votes
1answer
142 views
Poor man's clock MUX with an LVDS input
I want to send two different 10MHz clock signals to a device.
My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC.
The first source have ...
0
votes
2answers
55 views
Jitter Measurement Equipment
I'm looking into measuring clock signal jitters in the range of 50 to 100 ps peak-peak, at clock frequencies up to 250 MHz. What kind of measurement equipment do I need for that? A super fast ...
3
votes
1answer
401 views
Period Jitter vs. Phase Jitter
I've got an oscillator spec that states an RMS period jitter of 1.7 ps and an RMS phase jitter of 0.85 ps.
I know that period jitter describes the deviations from the oscillator's average period over ...
1
vote
2answers
189 views
Clock Tree Jitter Estimation
How do I estimate the output jitter of a clock tree consisting of a clock oscillator followed by a clock buffer?
The components have the following jitter characteristics:
The clock oscillator has a ...
1
vote
4answers
298 views
clock oscillator substitution, jitter question (audio DAC)
I need a 5 x 7 mm HCMOS clock oscillator for my hifi audio DAC (Texas Instruments PCM5122)
I used to employ the following oscillator: FXO-HC736R-22.5792, but it is now discontinued, and the suggested ...
1
vote
1answer
439 views
Would a long chain of inverters induce jitter?
I've recently designed a high-speed driver with the clock working at a highest frequency of 10GHz.But as the clock period becomes shorter,I've found that jitter situation too serious to be ignored.
...
1
vote
0answers
31 views
Jitter Specification of a fanout buffer
While designing clock tree, we use source, receiver & distribution circuit.
Now, my receiver has a fixed Jitter requirement which I need to meet.
The problem is that the source I am using, ...
2
votes
2answers
126 views
LPDDR2 clock long term jitter issue
I have a problem with LPDDR2 clock period cumulative error measurement tERR(11-50per) but shorter length measurement are OK with some margin. I'm looking at some cause or tips to understand or fix ...
0
votes
0answers
130 views
Has anyone ever seen a (ring oscillator) circuit like this?
I first designed this using NT Multisim 14 and the simulation worked. Then I built it with breadboard but used NTE101 Germanium transistors instead of 2N3904 silicon transistors. When I tested it I ...
2
votes
1answer
361 views
In which physical unit is 'clock drift' measured?
I would like to model a clock signal with an drift parameter in my digital simulation.
The current implementation handles:
frequency / period
phase -360.0 .. 360.0 degree
duty cycle 0.0 .. 1.0
...
1
vote
1answer
354 views
What could be the source of this sine wave distortion, visible as equally spaced lines in FFT?
I have an MCU controlling a 16bit DAC via SPI (and an additional LDAC output, which triggers the update of the DAC output). The MCU has a precalculated 1120Hz sine wave in a 364-byte long buffer (all ...
1
vote
2answers
2k views
Calculate jitter of oscillator from PPM
I found oscillators with from 10ppm up to 50ppm and more, but how I can calulate maximum jitter of this oscillators?
With an online calculator I've found with 40Mhz and 50ppm this value:
2.500e-12s ...
0
votes
1answer
490 views
Clock distribution for low-jitter audio DAC
I am building a 10-channel audio DAC using 10 ES9018 converters and an ultra low phase noise clock (Pulsar) with femtosecond jitter. What would be the best way to distribute the clock's signal to the ...
1
vote
1answer
398 views
PLL drift over time
I'm curious about this situation and how I would go about understanding it better. I have an input clock of 100Mhz with a maximum total jitter of 1ns. I want to put that into a pll to double the ...
1
vote
0answers
311 views
Frequency locked loop for input jitter rejection
I have an application where I want to multiply from a xtal oscillator
at 32KHz to a system clock of 40MHz. A standard PLL isn't going to do the
job, because the 32KHz jitter is measured in ns. Since ...
0
votes
2answers
393 views
What is the jitter of an asynchronous FIFO?
I have an asynchronous FIFO (in a Stratix V FPGA) with two asynchronous read and write clocks of the same frequency of 100 MHz. As I understand, asynchronous FIFOs have a two-register ...
0
votes
4answers
400 views
Strange amplitude fluctuation in video signal
I am reading a video signal from a CCD array. For some reason I get this extreme vertical jitter. I use decoupling and bypass caps everywhere possible. But it does not seem to be the noise issue. Any ...
4
votes
1answer
456 views
What are the jitter characteristics of PLLs internal to Stratix V FPGAs?
I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
2
votes
1answer
226 views
What is the 1G Ethernet jitter requirements?
We have a Stratix V FPGA on which we want to run a 1G Ethernet PHY and MAC. Because we don't have a readily available 125MHz reference clock, we are considering using a PLL internal to the FPGA to ...
0
votes
2answers
323 views
Choosing Oscilloscope with appropriate bandwidth for Jitter analysis
Can someone give me a rule of thumb of choosing Oscilloscope with appropriate bandwidth for the Jitter analysis of clock signals? What device is highly preferable: spectrum analyzers, frequency ...
12
votes
3answers
2k views
How to add a controlled amount of jitter to a signal
Background
I am developing a digital clock and data recovery circuit and am now getting into the evaluation phase, focusing on testing the limits of the design and finding potential strengths and ...
7
votes
2answers
3k views
Phase Noise(dBc/Hz) and Jitter
Jitter as wiki explains undesired deviation in the periodicity of the clock and Phase Noise is random fluctuation in the phase of waveform caused by jitter. Exploring deeper into these terms when I ...
1
vote
2answers
302 views
Accurate ADC sampling with in-accurate clock
Im building a datalogger with a LPC11xx as CPU. It needs to wakeup at 256hz to take ADC samples, but this CPU has very in-accurate timed wakeup from deep-sleep, causing jitter on the sampled data.
So ...
5
votes
2answers
2k views
What causes jitter? [closed]
What are the hardware causes of jitter in a chip? Is it simply the clocks to blame, or maybe other components (such as transistors, capacitors, etc.)? Are the tracks bereft of fault?
