Questions tagged [kintex-series-fpga]
The kintex-series-fpga tag has no usage guidance.
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Does Vivado use the supply voltage to control the timing analysis results?
The question How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado? has the following comment from Dave Tweed:
The only reason Vivado allows you ...
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Seeing multiple possible locations for SYNC_HEADER in 10GBASE-R
I am trying to implement a 10GBASE-R PCS on an FPGA (Xilinx Kintex UltraScale+ Family). First of all, I understand that the included on-board transceivers provide native 64b/66b gearboxing, so I am ...
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Difference between PCS and PMA loopback in transceivers
Can someone let me know the difference between PCS and PMA loopback used in XILINX transceiver IBERT testing.
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AD7626 interfacing with Zynq or Kintex
I want to connect an AD7626 with a Zynq FPGA or a Kintex. Which bank should I choose?
Let say the for case
Chosen Zynq FPGA has only HR bank
Kintex has HR and HP bank.
How should I choose a bank ...
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Generate high speed data using GTX transceiver of Kintex-7 FPGA board
I want to use Genesys-2 FPGA board as a BER tester for transceiver circuits. I am using IBERT IP core available in Vivado for it. Genesys-2 has an FMC connector to provide output for which I am using ...
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ADC input with Low pass RC filter
I’m trying to implement 8 bit ADC in FPGA. FPGA running at 100MHz clock.
PWM signal is given to RC filter. Knowing that f=1/2piRC,
I have trouble with choosing the component's value. Is there any ...
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Clock source controlled by the logic that is being clocked by the source
What are the implications when an always block controls the switch that will change the clock source(actually more than one frequency coming from a clock divider) that is clocking the always block? ...
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What is the role of DE input of ADV7511 HDMI video controller?
I need to understand the data, DE, VSYNC, HSYNC and CLK inputs of ADV7511 video controller. I need them to program FPGA card (Xilinx Kintex KCU116) that has this video chip. FPGA manual says it uses ...
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Using a clock to increment a counter which drives a mux?
I am trying to program this functionality onto a Xilinx FPGA; however, when I program it to do this, I get no output.
My situation is as follows:
I have 12 bits of data (in parallel): the first 6 ...
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How to implement 8b10b en/decoding protocol between two FPGAs?
I'm using two Xilinx FPGAs (one Kintex 7 and one Artix 7). The Kintex 7 is tied to its own system (OPAL-RT software, it is a simulation software that is an addon to Simulink which lets data be output ...
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How would the SFP+ transceiver interface (Linear vs Limiting) affect my design?
On my board, I'd like to replace an RJ45 port with an SFP+ transceiver to increase data rate to 10Gbps.
In choosing an SFP+ module, I have noticed that the only MSA compliant interfaces can be ...
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PCB footprint of Xilinx Kintex 7 FPGA [closed]
I am laying out a board with a Xilinx Kintex 7 FPGA (serial number XC7K70TFBG676). The first step is to create a footprint of the FPGA for my layout tool, the Cadence Allegro PCB Editor.
Does Xilinx ...
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