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Questions tagged [kintex-series-fpga]

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Why the resource overhead of a design with new functionality (extra logic) is different on different xilinx fpga devices?

I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra ...
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2answers
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Clock source controlled by the logic that is being clocked by the source

What are the implications when an always block controls the switch that will change the clock source(actually more than one frequency coming from a clock divider) that is clocking the always block? ...
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What is the role of DE input of ADV7511 HDMI video controller?

I need to understand the data, DE, VSYNC, HSYNC and CLK inputs of ADV7511 video controller. I need them to program FPGA card (Xilinx Kintex KCU116) that has this video chip. FPGA manual says it uses ...
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0answers
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Using a clock to increment a counter which drives a mux?

I am trying to program this functionality onto a Xilinx FPGA; however, when I program it to do this, I get no output. My situation is as follows: I have 12 bits of data (in parallel): the first 6 ...
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1answer
296 views

How to implement 8b10b en/decoding protocol between two FPGAs?

I'm using two Xilinx FPGAs (one Kintex 7 and one Artix 7). The Kintex 7 is tied to its own system (OPAL-RT software, it is a simulation software that is an addon to Simulink which lets data be output ...
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1answer
2k views

How would the SFP+ transceiver interface (Linear vs Limiting) affect my design?

On my board, I'd like to replace an RJ45 port with an SFP+ transceiver to increase data rate to 10Gbps. In choosing an SFP+ module, I have noticed that the only MSA compliant interfaces can be ...
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1answer
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PCB footprint of Xilinx Kintex 7 FPGA [closed]

I am laying out a board with a Xilinx Kintex 7 FPGA (serial number XC7K70TFBG676). The first step is to create a footprint of the FPGA for my layout tool, the Cadence Allegro PCB Editor. Does Xilinx ...