Questions tagged [latch]

A latch or flip-flop is a circuit that has two stable states and can be used to store state information. However latch is normally used to describe a simple storage device while flip-flop is normally reserved for clocked devices.

Filter by
Sorted by
Tagged with
0
votes
1answer
30 views

Need a modified S-R latch

I have a comparator output who is normally high and goes low from time to time. I need a latch which will change its output from high to low when the comparator's output change to low (and keep it ...
0
votes
0answers
29 views

SR Latch confused about possible Race condition

Totally new to electrical and got confused when reading about SR Latch [ What I am not sure is when R=0 then 2nd input on nor gate comes from output of nor gate below where again only value provided ...
0
votes
1answer
35 views

Inferred latch occurence in verilog

Implement the following circuit: Note that this is a latch, so a Quartus warning about having inferred a latch is expected. This is my implementation ...
0
votes
1answer
79 views

What is this symbol used in this D flip flop circuit? [duplicate]

I'm studying some notes on latches and flip flops. After the introduction of the D flip flop, the notes go on to explain its function - how it works. However, the first circuit diagram contains this ...
14
votes
6answers
2k views

How does an SR Latch get started [duplicate]

Noob question, but I'm not seeing how an SR latch such as the one in the image can "get started". If each input depends on the output from the other, how can there be two inputs to each gate to set ...
1
vote
3answers
178 views

Would this circuit work like an SR latch? Why is it better to use two NOR gates?

I am very new to digital logic, and have just started to learn about feedback in circuits. The basic example of an OR gate with its output connected to one of its inputs creates a circuit that seems ...
0
votes
2answers
55 views

What does fall and rise of clock mean?

Im new to electronics. In fact, I'm a computer scientist looking into embedded systems. I am going through Vol. 1 of Jonathan Valvano's book on embedded systems and got stuck when i read on Gated D ...
0
votes
1answer
53 views

Why is the SR Flip flop edge enabled

I'm struggling to understand the diference between a Latch and a SR Flip Flop, I know that a latch is level activated, and the SR Flip Flop is edge activated but if the circuit is the same, why is the ...
0
votes
2answers
154 views

Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...
1
vote
1answer
125 views

What is edge trigerring and what's need for it?

I was reading flip-flops and the text-book said that we should edge trigger flip-flops. I didn't get what is edge triggering and why it is needed. Can anyone explain me ?
0
votes
0answers
29 views

Do I understand the off state (0/0) of an SR latch correctly? [duplicate]

Can someone please confirm if I understand this correctly: When neither R nor S are on (both are 0) it seems to me that at first both outputs are 1, then it feeds back through, and both go to 0, and ...
0
votes
3answers
86 views

VHDL: I have a lot of inferring latches due to my case statement

I have coded a project for an FPGA and in one of my files which is a mux, I have a lot of inferring latches, which I think is due to my case statement. The code looks like this: ...
1
vote
2answers
85 views

SR Latch: Why reverse S and R in NAND and NOR if it reverses the outputs too?

Here is a NOR based SR latch: And here is a NAND based SR latch: So, basically first we flipped the orientation of R and S and then declare that in our NAND latch, the output would be flipped i.e. 0 ...
0
votes
0answers
66 views

TTL “radio-button” using priority encoder and latch

I'm liking this site and I am not always using it to just throw a question but to develop ideas all the way. First time I did that was on StackOverflow I need JSZip and gzip for my web page, and JSZip ...
0
votes
4answers
95 views

simplest digital voltage selector circuit using common parts

I found the following circuit for the atmel AT89LP4052 microcontroller programmer, but the bottom right section with all those transistors is an awkward way (to me) to make the input to VPP zero, 5V, ...
0
votes
2answers
141 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
0
votes
0answers
42 views

Understanding complements on inputs

I've got a problem understanding formal writing down of complements on inputs. During my laboratory exercise I was working with a device that had D flip flop embedded in it. The goal was to ...
0
votes
0answers
22 views

Sequential NAND Based Phase-Frequency Detector output

I'm trying to understand the output of my phase detector only for a pulse that goes from zero to one. here is my schematic: (ref is Clk_ref, and Div is Clk_out, both come from an outside circuit) ...
0
votes
2answers
162 views

Which is better latches or flip flop

I was reading about flip flops where author is convincing that it's better to use flip flop than latches. He gave following reason for it. As seen from the block diagram of Fig. 5.2. a sequential ...
0
votes
2answers
58 views

D Latch as Transparent latch

I was reading an article over latches and suddenly a line struck me which says "D latches are also known as Transparent latches.". Anyone who can explain me why D latches are known as transparent ...
0
votes
1answer
96 views

Stable state and don't care

I have a latch but I can't understand what are the meaning of Un/Stable state and ...
0
votes
2answers
40 views

SR Latch internal conflicts

it is known that "11" are invalid inputs for a SR Latch. But I do not understand the reason of that. I cannot see the electrical conflict in this structure: If R = 1, its NOR gate will give 0, for ...
0
votes
2answers
213 views

Can anyone help me to understand what these capacitors do in this design?

I have a circuit design makes a button latch on-off and drive a mosfet. When I energize the circuit Vout that drives thr mosfet is initially low. After pressing the button, the button state changes ...
0
votes
0answers
47 views

BJT Latching Circuit Help

I have build a latching circuit using both a NPN & PNP BJT to turn on and off an LED, as shown below: simulate this circuit – Schematic created using CircuitLab When I built the circuit ...
0
votes
1answer
56 views

How does this RS-latch with open switches power the lightbulb?

So I'm trying to learn some of the basics in electrical engineering such that I can better understand how computers work and I'm currently reading about circuits with switches, relays, different gates ...
3
votes
2answers
172 views

How to analyze S-R latch circuits?

I'm trying to understand the circuit below (from the Apollo Guidance Computer), which is two S-R latches connected together. The top input resets the output and the bottom input sets the output. But ...
0
votes
1answer
70 views

How soft latch power switch in this specific circuit is possible?

I am trying to understand the soft power switch operation of a LED lamp I dissembled. The circuit of the lamp is depicted below. The switch S1 can be considered as a momentary on switch (SPST). The ...
1
vote
3answers
137 views

Circuit to randomly light one LED or another

I am attempting to make a cheap and simple "quantum-ish" coin flip circuit. My idea is to use something like an SR latch driving two LEDs, and have the initialization be driven by some random event. ...
0
votes
2answers
58 views

Power Failure Detection Circuit via Flip-Flop

I'm trying to create a circuit that will detect complete power failure. I think I understand what major components I need, but I'm unsure as to how to go about connecting them. My plan is to take 3....
1
vote
1answer
61 views

How latches are used to implement High-speed VLSI Designs?

I read a article saying "Latch-based designs, however, have smaller dice and are more successful in high-speed designs in which the clock frequency is in the gigahertz" but I am unable to understand ...
0
votes
1answer
60 views

Finding out the values in a truth table for a SR-Latch [closed]

My task is to fill in this table the output Q by analysing following circuit My suggestion would be: Would that idea be right? in the digital electronics means: S=1 => Q=1 and R=1 => Q=0 Edit: My ...
0
votes
3answers
169 views

Why is my Gated Latch not a Gated Latch?

After watching the excellent Carrie Anne's Crash Course Computer Science #6 (https://www.youtube.com/watch?v=fpnE6UAfbtU), I tried to design a Gated Latch in Logicly. I played with it a little, and ...
1
vote
1answer
126 views

What is the meaning of a “soft” latch?

Googling for "soft latch" brings up many results, and on this site 12 out of 232 questions tagged latch contain the phrase "soft latch". However, there seem to be ...
1
vote
2answers
173 views

What's happening to this 2N3906?

I'm creating a soft-latching circuit for my project, using a 2N3906 PNP transistor and an N-Channel IRLZ44N MOSFET. The circuit is fairly simple; Once switch one is pressed, it brings the gate of the ...
0
votes
1answer
105 views

Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...
0
votes
1answer
94 views

Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
0
votes
2answers
191 views

What's the difference between a hardware register and a shift register?

There are two different wikipedia articles but they don't articulate the difference very clearly. Is the main difference that the shift registry uses a clock?
0
votes
1answer
334 views

Why are latches level triggered and flip flops edge triggered?

I know what it means to be edge or level triggered but considering the block diagram or logic diagram of inside of latches and flip flops I cannot see what inside them specifies this property of each, ...
0
votes
0answers
55 views

Capacitor life hours

Working on an existing product which has had field failures. Design is a short (60ms) pulse is sent via microcontroller to activate / deactivate a latching switch. I have determined failure is due to ...
0
votes
1answer
599 views

Metastable state when S = R = 1 in SR Latch?

According to wikibooks, under the section SR Latch, S = R = 1 is a metastable state. The following things are mentioned under the heading When both inputs are high at once, however, there is a ...
0
votes
1answer
68 views

Rising Edge-Triggered Truth Tables

I'm trying to debug some issues in an old (early-90's is old now, isn't it?) circuit, and noticed something in at least two different chip's truth-tables, and thought I'd ask here.. In the 74LS74 (...
0
votes
1answer
81 views

Question about SR latch timing

I have a question about how SR latches work: To my understanding the real-world implication is that one of the two gates will receive power first and produce an output signal, and they aren't going ...
0
votes
2answers
69 views

Difference between low signal and no signal for a SR latch?

I am struggling to understand how the SR latch works. When an input has designation 0, this means "low signal" correct? Is this completely different than "no signal"? Doesn't a logic gate need some ...
1
vote
1answer
179 views

Some questions about a transistor latch?

Below is a latch made up of two transistors: When the base current of Q2 is increaased this increases also the base current of Q1 which in turn increases the base current of Q2 more. So by such ...
1
vote
0answers
41 views

Problem based on Latches (Sequential Circuits)

I am trying to solve the following question: I want to know: If the truth table for \$ Q_{n+1}\$ and \$\bar Q_{n+1}\$ is correct. I have found out the Reset and \$Q_{n}\$ conditions. However, I see ...
0
votes
1answer
164 views

How do we decide which circuit is a latch?

Will A and B always be the complement of one another regardless of what logic gates we use in the latch-like circuit? For instance (the two circuits shown as examples): How do we decide whether A and ...
1
vote
0answers
88 views

Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
0
votes
1answer
620 views

Convert a toggle switch into a momentary response

I'm working on a project and I need to use a toggle switch to control a device that expects a momentary signal. What I want is send a momentary pulse when turning it on and off. Ie: swith off to on: ...
1
vote
1answer
1k views

New to circuits: Creating a toggle button in Logisim using Latch

I have just started doing logic and circuits and I am trying to make a toggle button using a button and a latch. I can't seem to figure out how to make the light toggle instead of turning on when the ...
0
votes
1answer
225 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...

1 2 3 4 5 6