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Questions tagged [latch]

A latch or flip-flop is a circuit that has two stable states and can be used to store state information. However latch is normally used to describe a simple storage device while flip-flop is normally reserved for clocked devices.

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What is the point of two enable signals in PT6957 LED driver?

I have a 48 x 16 matrix LED display E-MOTIVE Q-B-069B (no datasheet), and during reverse engineering I found 4 off PT6957 there. PT6957 is 16-bit shift register, latched with constant current drives. ...
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Why is my code implemented in latches?

I am starting to design in a HDL. So, I'm designing a simple test, where variable "var" is an and of each "partial" row. However, when I synthesize this, I see that the RTL ...
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how do I add turn-off to a latching circuit?

so, I made this latch circuit : Falstad Simulator simulate this circuit – Schematic created using CircuitLab It turns on and stays on. How do I add turning off using single momentary switch? I ...
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Is there something wrong with this power-on latch circuit?

I am analyzing an electronic device that has an MCU and the following characteristics: it is powered from a 3.7 V Li-ion battery it has an on/off button that needs to be pressed 1 second to power-on ...
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What are the necessary conditions to prevent latch-up problem for Oscillators?

In his chapter on oscillator design, Razavi discusses the issue of latch-up and proposes several methods to eliminate it. However, he doesn't provide explanations for these methods. Could anyone ...
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Comparator Latch Initial state

I am working on a latching current limiter circuit and as part of it I'm using multiple LM139 comparators to implement a simple SR latch. This specific comparator has an open-drain output. A latching ...
Malte's user avatar
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D latch circuit not working

I have made the attached circuit, to make a on/off switch for a power circuit. I have made the set and reset pins high. Also shorted the Q' and D. After many trials, still stuck up with the output Q ...
Sainath's user avatar
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CML Latch simulation in LTSpice

I am trying to simulate a CML Latch in LTSpice (schematic below), but the simulation results do not seem right. I am using N_50n transistors from BSIM4 model. L = 60n for all transistors, W = 10u for ...
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Transistor latch circuit stays on and button is unresponsive

I'm using a 2n2222a and 2n3906 with a 2n3906 as a reset and a irf4905 mosfet to carry the load I've redone this circuit many times on the computer, and breadboard and it seems to work but as soon as I ...
Kali Bot's user avatar
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How to convert SR (NOR) latch into S'R' (NAND) latch

What is the general rule of thumb to convert SR (NOR) latch into S'R' (NAND) latch? I only know the two inputs (S,R) need to be inverted. What about outputs (Q)?
VvOoGame's user avatar
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Setup and hold time for pulsed latches

I am reading "CMOS VLSI Design A circuit and System Perspective". I didn't understand why the clock period needs to be larger than below formula. Can anyone help me to understand it?
Cyan_VLSI's user avatar
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Modification on latching power circuit

I have built the following circuit to power my esp8266. And it works fine. https://community.home-assistant.io/t/multiple-button-wifi-remote-no-deep-sleep-required-battery-lasts-forever/306233 When ...
Kerem's user avatar
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Is negative voltage going to cause trouble?

I'm trying to design a circuit that will allow me to set and reset an SR-latch with a single input. My idea is that when the input is driven high, the latch immediately resets, and if it persists for ...
php_nub_qq's user avatar
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Comparator connection with SR latch v2

I designed a comparator that sets 12 V on the output whenever there is overvoltage on the input of the comparator (13 V from AC sin source). In my schematic, the output value of the SR latch reacts to ...
Simplifier's user avatar
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Rising Edge Demux

I'm trying to create a demux for the YM2610 sound chip. The sound chip selects whether to set the low bits or high bits of the address with a single pulse; the rising edge should trigger a latch for ...
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Explain schematic for one-shot trigger

Can you please help to explain following schematic: How does this circuit work? What is the purpose of the diode and the capacitor?
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The logic gate design of a positive edge triggered, master slave d flip flop with asynchronous inputs preset and clear?

I'm a computer science student who's trying to get a better understanding of the d flip-flop. My project assignment is to make a CMOS design of a positive edged d flip-flop using ff master slave and ...
Are You Sure About That's user avatar
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Dual Mosfet as a hard latch rather than soft?

I have built and tested the below circuit and it works well as a soft latch with a toggle function from the momentary switch. How would I modify this circuit to latch once and not reset until either ...
Ken's user avatar
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MCU not powering off completely

I implemented this on/off circuit that I use with a LiPo battery and a HT7833 voltage regulator. Since my MCU (ESP8266) can only handle 3.3v, I added a voltage divider for the MCU sense pin, just like ...
ruben's user avatar
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1 answer
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On a method of clock gating with a latch

My textbook (CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, by Weste and Harris) gives the following discussion of a particular method of clock gating into some digital block. I ...
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Working of edge-triggered flip flop

The above circuit is a master slave flip flop. Edge triggered. The working should be: During positive cycle, master is enabled by clock, storing data. At the negative edge (transition), slave takes ...
DaveFenner's user avatar
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What's the difference between a latch and a flip flop? I found multiple answers

So I was checking out sequential logic and I found two different circuits for flip flops (or latches, or both). Let's take D flip flop for my quesiton. There's one circuit here, showing a D flip flop: ...
DaveFenner's user avatar
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How to calculate the time constant of a simple cross coupled diff pair latch circuit

I have a circuit, which is given below. Now I want to find the time constant of the circuit, considering there are equal caps placed at node X and Y. For a small signal model I can easily find the ...
thehappywine's user avatar
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Confusion about Synthesis Results of Verilog Code: DATAIN has no connection

I am quite puzzled about the synthesis results of the following code. Here is the code: ...
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SR latch with both inputs at 0

I know questions on SR latch and FF has come up fairly often and I've already seen answers that made me understand better how this device work. However, I still have a doubt when both input S and R ...
aghin's user avatar
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Is there any such thing as a tristable, quadristable, etc. multivibrator?

The title says it all. Is there a discrete circuit that can produce 4 different outputs based on a single tactile switch click? I'd like to do this with either a discrete design or a 74373 since ...
Aaron Butkovich's user avatar
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Difference between DM13A and TLC59281 Constant Current LED sink Drivers

I was using DM13A driver in my old PCB designs and it was working perfectly using Arduino Mega. Due to parts shortage at JLCPCB I had to use TLC59281 driver for my new PCB. But TLC59281 is not working ...
Zunuran Nasrullah's user avatar
4 votes
4 answers
378 views

Capacitor function in a flip flop circuit

I'm new to electronics and I'm trying to figure out the following circuit. The circuit turns on one of the leds when one button is clicked, if the other is clicked then the current light is turned off ...
Fahed's user avatar
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2 answers
149 views

Latching with MOSFET

I am struggling to have the circuit below working on LTspice. Indeed, as I understand it when the switch is pressed the LED should change it's state (turn on if off / turn off if on). The switch is ...
Julien's user avatar
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Blue UV LED Timer Circuit

I have designed a PCB for mouth guard device and also its enclosure is ready in which PCB will be placed when its not in use. I want to use a UV blue light for UV sterilization inside the box. Now the ...
Zunuran Nasrullah's user avatar
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Replacing pushbutton with sensor in 555 timer latch circuit

I want to make a circuit where there will be a photodiode which when receives infra red light from the IR LED for the first time, produces a high output and when it receives the light for the second ...
Kailash Kumaravel's user avatar
1 vote
5 answers
140 views

Why would an intermediate voltage level cause a metastability in a SR-latch

Transistors and logic gates are actually analog in nature they aren't digital they don't turn on or off at certain voltages. Image source: All About Circuits - Voltage Tolerance of CMOS Gate Inputs ...
John greg's user avatar
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Astable multivibrator and latch in one

I am trying to design a combined function of oscillator and latch in one circuit to spare parts. Seems it is working but anyway do you think it is OK or did you see somewhere this circuit?: simulate ...
Michal Podmanický's user avatar
2 votes
3 answers
473 views

Tie an input of an AND gate to its output

Let's say we have an AND gate and we give 1 as one of its inputs and we tie the other input to the gate's output. What will happen?
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Triggering an SR Latch with multiple reset lines

Ok, so I'm relatively new to electrical engineering having worked on the software side of life in the past. I'm trying to work a simple SR Latch where only one output is enabled at once. To do this, I'...
AQMS's user avatar
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2 votes
1 answer
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Latch is stable with competing capacitors?

I inherited the attached design as part of a work project. This is a latch which is meant to hold the high-voltage side of the system in the powered on state when a momentary power button attached to ...
carpenma's user avatar
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Is this circuit correct and safe to bypass my latch circuit, turning on the load every time I connect it to 5V?

I have this working on/off latch circuit below that works on a 8.4V battery. I can charge and bypass the battery when I connect the circuit to a 5V charger, while still providing supply to the load ...
Rodrigo's user avatar
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3 votes
2 answers
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First time designing an SR latch; I'm using it to control the enable pin on my eFuse IC. Just want to know if I'm overlooking anything

I just finished designing my rectifier module that has a built-in voltage monitor IC and an eFuse IC. Its purpose is to convert the 3-phase AC output from my wind turbine and use it to power my USB ...
soconnoriv's user avatar
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1 answer
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Transistors falsely latch with EMI

I have a very basic NPN - PNP latching circuit: [Sorry for the upside down image] The latch initially is off, and when the op_amp_Signal_and_latch turns on, the ...
15 Volts's user avatar
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ESP32 power latch circuit react on low and high (reed switch)

I am currently building a door sensor with an ESP32 and a reed switch. My code is working with the deep sleep functionalities of the ESP32. With its help I can detect a falling/rising edge and wake ...
EBMare's user avatar
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2 votes
4 answers
925 views

Push button latch circuit - switch issue

I have built a single push on/off latching circuit as per the diagram. It runs from 12 V. It works, but the issues I have is that first, it is already on when I connect power, it should start off, ...
Grant Lee's user avatar
3 votes
0 answers
94 views

D-type LATCH output when minimum clock/enable pulse width is violated and input/output are the same [closed]

Can the output of a D-type latch go metastable when: There is a minimum CLK/ENable pulse width violation The input and the output of the latch have the same value?
Viktorinox's user avatar
1 vote
1 answer
125 views

How to make a D-type latch not start in SET condition by itself?

I have this schematic to digitally start and stop a power supply of a Raspberry Pi, and I want to be assured that the latch doesn't start by itself in the ON state when I apply power. Of course, if it'...
Marus Gradinaru's user avatar
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1 answer
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Question about T flip-flop

I am trying to implement a switch that works like the description in the picture. In my research I came across the T flip-flop, however a T flip-flop requires a clock signal. I don't have that. Is ...
tt40kiwi's user avatar
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How do I model switches in Matlab/Simulink?

I am trying to model different types of switches in Matlab/Simulink. There is this type of switch that I can't find a name for or design. I am not an expert in digital logic, I only have the basics ...
tt40kiwi's user avatar
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2 answers
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Is it possible to combat SR Latch oscillation or there are better alternatives?

I need to store a bit value and then ignore any attempts to store/change it again until it's reset by another signal. So I figured the SR Latch is suited for the task. However in my project there is a ...
user64675's user avatar
1 vote
1 answer
274 views

555 timer diagrams Q/Q bar confusion

I've seen this in several places and am perplexed. First, I thought that the output of an SR latch was Q, and the inverted output, or 'not Q' is shown as either Q with a bar over it or denoted with a ...
nuggethead's user avatar
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3 votes
3 answers
845 views

Is the invalid state of an SR latch also undefined?

I understand that if both the Set and Reset inputs of an SR latch are high, the output of both Q and Not-Q is low and this is considered an invalid state. But in this situation is the output also ...
nuggethead's user avatar
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5 answers
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How does electricity flow in this SR latch from Petzold’s Code?

I am confused as to how this circuit is complete and hence how electricity flows through it. Petzold explains earlier in the book that the V refers to a battery connected to ground the way in which I ...
MechSE's user avatar
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1 vote
1 answer
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SR latch effect which only requires one GPIO

I have an STM6821TWY6F watchdog IC for my MCU. When the MCU gracefully goes to sleep it will disable the a watchdog to prevent unwanted wake ups. The watchdog was designed to look for an oscillating ...
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