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Questions tagged [latch]

A latch or flip-flop is a circuit that has two stable states and can be used to store state information. However latch is normally used to describe a simple storage device while flip-flop is normally reserved for clocked devices.

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Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...
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65 views

Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
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What's the difference between a hardware register and a shift register?

There are two different wikipedia articles but they don't articulate the difference very clearly. Is the main difference that the shift registry uses a clock?
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78 views

Why are latches level triggered and flip flops edge triggered?

I know what it means to be edge or level triggered but considering the block diagram or logic diagram of inside of latches and flip flops I cannot see what inside them specifies this property of each, ...
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Can 8051's ALE pin be equivalent to ground?

I want to add another port to the 8051 and I plan to do so by connecting port 2 (pins 21 - 28 of the 8051) to the Q inputs (pins 2 - 9) of an edge-triggered latch (74HC574). I will also connect the ...
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50 views

Capacitor life hours

Working on an existing product which has had field failures. Design is a short (60ms) pulse is sent via microcontroller to activate / deactivate a latching switch. I have determined failure is due to ...
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63 views

Metastable state when S = R = 1 in SR Latch?

According to wikibooks, under the section SR Latch, S = R = 1 is a metastable state. The following things are mentioned under the heading When both inputs are high at once, however, there is a ...
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43 views

Rising Edge-Triggered Truth Tables

I'm trying to debug some issues in an old (early-90's is old now, isn't it?) circuit, and noticed something in at least two different chip's truth-tables, and thought I'd ask here.. In the 74LS74 (...
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Question about SR latch timing

I have a question about how SR latches work: To my understanding the real-world implication is that one of the two gates will receive power first and produce an output signal, and they aren't going ...
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43 views

Difference between low signal and no signal for a SR latch?

I am struggling to understand how the SR latch works. When an input has designation 0, this means "low signal" correct? Is this completely different than "no signal"? Doesn't a logic gate need some ...
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43 views

Some questions about a transistor latch?

Below is a latch made up of two transistors: When the base current of Q2 is increaased this increases also the base current of Q1 which in turn increases the base current of Q2 more. So by such ...
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40 views

Problem based on Latches (Sequential Circuits)

I am trying to solve the following question: I want to know: If the truth table for \$ Q_{n+1}\$ and \$\bar Q_{n+1}\$ is correct. I have found out the Reset and \$Q_{n}\$ conditions. However, I see ...
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92 views

How do we decide which circuit is a latch?

Will A and B always be the complement of one another regardless of what logic gates we use in the latch-like circuit? For instance (the two circuits shown as examples): How do we decide whether A and ...
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Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
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1answer
273 views

Convert a toggle switch into a momentary response

I'm working on a project and I need to use a toggle switch to control a device that expects a momentary signal. What I want is send a momentary pulse when turning it on and off. Ie: swith off to on: ...
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215 views

New to circuits: Creating a toggle button in Logisim using Latch

I have just started doing logic and circuits and I am trying to make a toggle button using a button and a latch. I can't seem to figure out how to make the light toggle instead of turning on when the ...
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51 views

Can you suggest a latch circuit that ignores short duration triggers?

I am looking for a circuit which I can adapt to CNC machine to monitor a panel indicator LED to trigger a solenoid. Since CNC controls are a very mysterious and expensive I don't want to connect ...
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1answer
123 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...
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140 views

Momentary Switch NAND Latching IC Burning and (Possibly) Faulty Logic

Problem: My issue is that the momentary switch with NAND latching logic that I have designed is not functioning consistently. It does work as intended at first, but then fails to work after repeated ...
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1k views

What is the difference between the circuits?

I found the trigger (latch) circuit: When no button is pressed, the LED does not light, if you press SW1, the LED will light up, and will light until you press SW2. This can work for different values ...
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2answers
40 views

Which kind of logic latch for an over-current H-Bridge disable?

I have a simple logic circuit requirement, but can't seem to match any standard flip-flop or latch to my needs (SR, JK, D, MS, level-sensitive or clocked, etc). The circuit is to disable a H-bridge ...
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326 views

Designing an Over-Current Protection Circuit with Delayed Reset

As part of a larger design I am trying to monitor current through a wire and cut it off if it exceeds a threshold. After the current has been turned off it should remain off for a minimum time period ...
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119 views

SR latch conventions

consider this rule: In SR latches using NOR gates the S should be connected to Q and the R should be connected to Q' and for the SR latches using NAND gates vice versa. is this a convention ? or a ...
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270 views

positive edged and negative edged D flip-flops

I want to know that my understanding about D flip-flops is right or not. We have different types of D flip-flops: Some of them are positive edged (0->1) and some of them are negative edged (1->0) ...
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32 views

Set latch and Or gates

I'm really new to Electrical circuits so please bear with me. I studied how set latch works :firstly, input 0 then Q(let's say output and it's 0 i this case) feedback another input resulting output ...
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1answer
312 views

how to make a latching circuit with ground

I have a pump, represented by a lamp in my schematic, i want this pump to be running once i switch the Activate switch, and when ever an alarm(i have 2 different) is triggered (Alarms are ground) the ...
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1answer
133 views

Latching power circuit with short-to-ground switch

I'm trying to build a circuit around an existing switch that allows another component to override the switch state. (Our component is a computer and the feature we're trying to build is remote-...
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2answers
64 views

High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
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35 views

Latch with no Vout

I'm working with the WiPy expansion board at https://github.com/wipy/wipy/blob/master/hardware/ExpansionBoard-v1.2/ExpansionBoard-v1.2_Schematics.pdf On sheet 3, there is what appears to be a latch ...
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1answer
925 views

Transistor latch circuit - what's the capacitor for?

I've been studying this transistor "latch" circuit over the past couple of days and I think I've grasped most of it, but I'm not sure about the purpose of capacitor C1. https://circuitdigest.com/...
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228 views

Latch edge and Launch edge of a clock [closed]

Why does a Destination register starts taking input from a latch edge and not a launch edge
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140 views

How to correct voltage overshoot in clock divider output?

I am trying to make a quadrature phase divide-by-6 clock divider circuit in cadence. I managed to complete the circuit and obtained the correct waveform; however, due to some reason I am getting a ...
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1answer
118 views

Can Latch be used to store voltages? [closed]

What if we put S=5v , R=0v and then detach the latch IC from the circuit what will happen at Q end ?
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104 views

Strange output from latch connected to comparator

I'm trying to make a latch (in ltspice), so if the comparator output (A) goes low, the latch will trigger and C will go high. C should stay high, irrespective of whether A goes high or low after that. ...
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1answer
290 views

Soft-latch auto-reset OFF (hold) / ON (press) button, is the schematic correct?

I'm looking to make a soft-latching interface with a single momentary push button. Required features for my build are (edited, sorry for bad description) : Circuit should always start in OFF ...
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3answers
2k views

One pulse to ON/OFF bistable latching relay

I've been trying to design a latching relay driver circuit, with using a push-button switch. Basically when the circuit is powered on, first press in push-button switch make the relay SET, then the ...
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4answers
337 views

Power circuit with a push button

In my current project, I try to connect a load rated at 5V/2A with a 5V power supply. To avoid plugging and unplugging the supply over and over again, I decided to add a push button. To turn the ...
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2answers
497 views

How do I avoid a race condition in SR latch?

I have designed an SR latch using Cd4001 NOR gate IC. When both S and R are low the circuit refuses to stay in previous state even though I am using appropriate dropping resistors. Is there any way to ...
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212 views

Can latching relay make the switch if the coil is powered by either of its switching circuits?

I am thinking of making a set up whereby the latching relay will switch between two 9V circuits from separate power sources. However the relay coils themselves must be powered by either of the 9v ...
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1answer
365 views

Latching relay not working

I'm pretty new to electronics. I've however recently used mechanical and solid state relays successfully. Now, I am just started trying to use latching relays. I am currently trying to create a set up ...
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55 views

Photocoupler to Latch Microcontroller Power Supply

I'm revising my custom arduino circuit which involves powering an atmega328p. I am using a 9V battery connected to a BS170 MOSFET. Without any voltage applied to the gate of my BS170, the battery is ...
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66 views

Locking latch or flip-flop

I am looking for a specific type of latch or flip-flop or "black box circuit" that will give a constant low output until it receives an input pulse, and will then go high and stay high regardless of ...
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100 views

Dividing pulse train

As requested, to clarify: I am working on constructing a subsystem consisting of a signal generator, a lab instrument, and the interface between them. This control circuit will take a 6kHz clock ...
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2answers
2k views

SR latch timing diagram or waveform with delay, help!

I'm having trouble solving these two problems (my solution and general solution showed): What I did was follow the truth table and based on the combination on the graph draw the appropriate state ...
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2answers
905 views

Why are two transmission used gates to make a D Latch?

In the circuit given below I can't understand what the second transmission gate TG2 is used for. It is connected both to the exit of a Transmission gate and an inverter... so what is the actual input ...
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1answer
126 views

Steady hand game with latch mystery [closed]

I am trying to make a steady hand game with latch. It works perfectly fine in simulation and also work on a breadboard with real stuff. The mystery is it works when power is 5V and do not work when ...
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74 views

Soft latch on/off button simulation

I am trying to simulated in pspice a soft latch on/off circuit but it is not working as expected, even if I double check the implementation. Can someone explain to me why the voltage on the probe is 0....
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3answers
726 views

How do I eliminate latches in FSM Verilog implementation?

I'm trying to create an FSM that left shifts a register until the MSB is 1 while counting the number of shifts completed. However, I have an issue with latches because I don't re-assign each register ...
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1answer
182 views

Latch using only NPNs [closed]

I've been trying to find a way to create a latching circuit with only NPNs and passives. I think I've found way: My logic being that the resistors act like a potential divider and provide power to ...
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1answer
243 views

What is the clock-to-out delay for a pulse triggered flip-flop?

In edge triggered flip-flops, the clock-to-out delay or the flip-flop delay is defined as the time between the triggering edge of the clock till the arrival of stable output from the flip flop. What ...