Questions tagged [latch]

A latch or flip-flop is a circuit that has two stable states and can be used to store state information. However latch is normally used to describe a simple storage device while flip-flop is normally reserved for clocked devices.

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What is the simplest (standard?) way to add a second clock phase that *precedes* the main clock by 90°?

My saga with the 74LS670 4 x 4-bit dual ported level triggered latches continues. I used to have a simple clock which I could run with either a tunable astable multivibrator, or with in single-step ...
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Flip-flop vs latch: Do flip-flops have an edge detector integrated?

As far as I know, a latch and a flip-flop are the same excepting that flip-flop only "works" with an edge of the clock (let's supose rising edge for the question.) To make the flip-flop &...
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Mutually exclusive latching momentary pushbuttons

Here's a circuit which implements a radio button arrangement. All switches activate the clock. One of the switches enables a latch which has no output connection. The other two switches each enable ...
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Problems with OR Gate Latching Circuit [closed]

I was having trouble lately with a simple latching circuit that uses 1 or gate with the input of one side (A) is connected to a push-button switch and the other input (B) is simply attached to the ...
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SR FlipFlop Question

I am studying Digital Logic Circuit right now and I have question to ask. I have searched lot of places in order to find this answer, however due to my lack of searching ability I was not able to find ...
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Outputting correct data on shift register with clocks tied from microcontroller

I want to be able to output correct data from the microcontroller to the 74HC595 shift register without using the clock lines separately. This schematic matches my ideas for 16 bits of data: The ...
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40 views

How to design a latch from a truth table

I am trying to design a latch using a truth table. The inputs to the latch are En and In. I think the circuit implementing the truth table should not change output when En is low, and output In when ...
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32 views

Is there a one trigger latch for AC?

SCR is good for latching DC source, one trigger will turn on the source indefinitely. But how about AC source? Latching mechanical relays is good but it is too big for me. Triac is designed for AC ...
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101 views

Using CMOS logic ICs to drive a P-channel FET

I am attempting to implement a latching circuit without software. The results thus far seem promising, but now I want to drive a control line on a solid-state relay using its output as a high-side PNP ...
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65 views

Are there errors in the CD4013B datasheet by TI?

The CD4013B datasheet by TI contains the following statement: Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively. Table ...
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Latching circuit latches before pushing the latch button

I am a beginner and I am trying to build a latching circuit. In the diagram below, the LED is on while I expect it to be off. The push button should switch the PNP 2N3906 on, which in turn switches ...
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Two SR latch implementations and De Morgan's rule

Here, I modify the encapsulated area of an SR latch(with NOR gates). The encapsulated area on the first circuit(with the NORs) is equal(at least, I think so) to the wider encapsulated area in the ...
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The difference between these two D latch circuits

I simulated both ones and could not see any difference in functionality. So, what is the need for that extra NOT gate? When it is preferred?
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What is the relevance of a !Q in the D Flip-Flop when using for a memory module?

If the purpose of this circuit is to store the value of D in Q, why should I need a !Q? Why don't use a circuit like this instead?:
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Waveform of a SR Latch [closed]

I need some help confirming what my answer sheet is indicating regarding the output waveform. So far, everything I have matches up with the answer sheet except the last peak from output 'U'. The SET ...
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SR Latch output pin biases state of the logic gate under special circumstance

I am having a really hard time putting my question in the right words, but I will try my best. So I am working with an MCU (EFM32TG11) that features a bootloader with pin activation. To make the ...
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Sequential circuits and memory

I read some books to understand why we need to memorise bits in electric circuits and found the sequential logic circuits are designed to achieve that goal. The basic element is the SR Latch which ...
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ESP32 : Latching power switch circuit fails to boot

I tried to reproduce a little circuit I found on the web : source : https://randomnerdtutorials.com/latching-power-switch-circuit-auto-power-off-circuit-esp32-esp8266-arduino/ When I push the ...
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Which is slow among the two? Latches or Flip-Flops?

I have a question regarding latches and flip-flops. Which of them, is faster? Please explain me this with a suitable reason.
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voltage regulator capacitor prevent to work of single button on off circuit

I'm using this circuit to turn on and off the system. The power supply is 12V. I use an LM2576 to decrease to 5V. Here is the circuit: Firstly I build on-off circuit also I added an LED at the ...
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How to build a selector

So I've been looking at this problem for a couple of hours, and I'm pretty sure I need to use finite state machines or at least some kind of memory elements to solve it... it goes as follows: "A ...
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1answer
101 views

JK latch, possible Ben Eater error?

Is it possible that the schematic shown here is wrong? I would expect something more like that... It seems like that he inverted the feedback wires, but I'm quite suspicious because he made the ...
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31 views

What accounts for the current vacillation in this JK latch?

After trying a few different simulators (many of which didn't work for this) I was finally able to model a JK latch with NOR gates. Here is an example: A weird thing seems to happen though (at least ...
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How to design a JK latch

I am trying to simulate a JK latch in a circuit builder. What I have come up with thus far is the following: I don't have control of the wiring (the application automatically does these wirings, ...
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Master-slave flip flop without gate delay?

It seems like a master-slave flipflop always has around a 2-gate delay between the Master and Slave sections of the flip flop. For example: My question is what would happen if, theoretically, there ...
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boolean algebra for a D Latch

I am trying to understand the boolean algebra for what X and Y equals for the D Latch below. By just looking at the circuits and the NAND gates I was thinking that: $$X = (Y * (A*B)')' = (Y * (A' + B'...
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Safety switch to latch when power turns off till reset

So I currently have a drive run by a PSU. I have a thermal controller that will cut power to the drive when it runs over temperature but it doesn't latch off, so as soon as the drive cools a little it ...
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Requesting help with a circuit design

I am looking to build a float sensor for a tank and automating the motor based on sensor input. I am looking to execute this without using a microcontroller. Below is my intended sensor setup in the ...
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Modification to the D flip-flop

When we take a clock and a signal, the D flip flop output always gives "clock edge" AND, and the state will be high unto to the next clock cycle. Now I want my output like like a latch, but timing ...
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Need a modified S-R latch

I have a comparator output who is normally high and goes low from time to time. I need a latch which will change its output from high to low when the comparator's output change to low (and keep it ...
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SR Latch confused about possible Race condition [duplicate]

Totally new to electrical and got confused when reading about SR Latch [ What I am not sure is when R=0 then 2nd input on nor gate comes from output of nor gate below where again only value provided ...
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Inferred latch occurence in verilog

Implement the following circuit: Note that this is a latch, so a Quartus warning about having inferred a latch is expected. This is my implementation ...
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What is this symbol used in this D flip flop circuit? [duplicate]

I'm studying some notes on latches and flip flops. After the introduction of the D flip flop, the notes go on to explain its function - how it works. However, the first circuit diagram contains this ...
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How does an SR Latch get started [duplicate]

Noob question, but I'm not seeing how an SR latch such as the one in the image can "get started". If each input depends on the output from the other, how can there be two inputs to each gate to set ...
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Would this circuit work like an SR latch? Why is it better to use two NOR gates?

I am very new to digital logic, and have just started to learn about feedback in circuits. The basic example of an OR gate with its output connected to one of its inputs creates a circuit that seems ...
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What does fall and rise of clock mean?

Im new to electronics. In fact, I'm a computer scientist looking into embedded systems. I am going through Vol. 1 of Jonathan Valvano's book on embedded systems and got stuck when i read on Gated D ...
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56 views

Why is the SR Flip flop edge enabled

I'm struggling to understand the diference between a Latch and a SR Flip Flop, I know that a latch is level activated, and the SR Flip Flop is edge activated but if the circuit is the same, why is the ...
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Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...
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What is edge trigerring and what's need for it?

I was reading flip-flops and the text-book said that we should edge trigger flip-flops. I didn't get what is edge triggering and why it is needed. Can anyone explain me ?
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Do I understand the off state (0/0) of an SR latch correctly? [duplicate]

Can someone please confirm if I understand this correctly: When neither R nor S are on (both are 0) it seems to me that at first both outputs are 1, then it feeds back through, and both go to 0, and ...
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VHDL: I have a lot of inferring latches due to my case statement

I have coded a project for an FPGA and in one of my files which is a mux, I have a lot of inferring latches, which I think is due to my case statement. The code looks like this: ...
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SR Latch: Why reverse S and R in NAND and NOR if it reverses the outputs too?

Here is a NOR based SR latch: And here is a NAND based SR latch: So, basically first we flipped the orientation of R and S and then declare that in our NAND latch, the output would be flipped i.e. 0 ...
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TTL “radio-button” using priority encoder and latch

I'm liking this site and I am not always using it to just throw a question but to develop ideas all the way. First time I did that was on StackOverflow I need JSZip and gzip for my web page, and JSZip ...
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simplest digital voltage selector circuit using common parts

I found the following circuit for the atmel AT89LP4052 microcontroller programmer, but the bottom right section with all those transistors is an awkward way (to me) to make the input to VPP zero, 5V, ...
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Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
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Understanding complements on inputs

I've got a problem understanding formal writing down of complements on inputs. During my laboratory exercise I was working with a device that had D flip flop embedded in it. The goal was to ...
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Sequential NAND Based Phase-Frequency Detector output

I'm trying to understand the output of my phase detector only for a pulse that goes from zero to one. here is my schematic: (ref is Clk_ref, and Div is Clk_out, both come from an outside circuit) ...
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Which is better latches or flip flop

I was reading about flip flops where author is convincing that it's better to use flip flop than latches. He gave following reason for it. As seen from the block diagram of Fig. 5.2. a sequential ...
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D Latch as Transparent latch

I was reading an article over latches and suddenly a line struck me which says "D latches are also known as Transparent latches.". Anyone who can explain me why D latches are known as transparent ...
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Stable state and don't care

I have a latch but I can't understand what are the meaning of Un/Stable state and ...

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