Questions tagged [latency]

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Low Jitter and Latency on signal trigger using WFI / WFE on STM32F405

I have a hobby project using a STM32F405 MCU, which is intended to respond to a fast clock signal (~1Mhz) connected to Pin 1 of GPIOA. For every transition of the input (both rising and falling), I ...
0
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1answer
44 views

What are the factors that affect delay/latency between base stations?

I am modelling a 5G network, with the uplink and downlink being decoupled and treated as separate networks. I am exploring the integration of fog computing and how latency varies between different ...
22
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3answers
6k views

Why does RAM (any type) access time decrease so slowly?

This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns). A ...
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0answers
27 views

quick path interconnect vs AXI

I want to know the performance difference between AXI and Intel's quick path interconnect which has been replaced by Ultra path interconnect(interms of latency). This is for very low latency(25 ...
2
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3answers
457 views

FT232HL FTDI consecutive SPI bytes delay problem

I have a problem with the FT232HL FTDI ic. Windows application send data to the chip via USB and the chip send the data out with one SPI channel. I did check with a logic analyser, the bytes are ...
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4answers
315 views

Maximum Clock Frequency

As an assignment for the HDL course I'm taking, I've to design an FIR Filter. The module consists of two a small combinational circuit which can be used to reset the module, another combinational part ...
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1answer
92 views

What single feature will enable ultra low latencies for 5G communications? [closed]

there has been a recent buzz around 5G and its ultra low latency use cases. Additionally, some people claim that data rates around 10 Gbps are a feasible scenario if mmWaves are to be used. I was ...
4
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2answers
885 views

How can I measure latency in a CAN bus?

Given a CAN bus with one master and 4 motor drivers, is there a way to measure the time between sending a command from the master (e.g. PC or PLC) and the execution of the said command (e.g. the motor ...
3
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2answers
430 views

How to know the latency of an oscilloscope?

How can I know the latency of a digital oscilloscope in roll mode? By this I mean the time it takes from the signal reaching a certain value to the moment this value is shown on the screen, i.e. the ...
4
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1answer
7k views

Why Bluetooth audio works at so high latency?

Referring to this, the lowest latencies achieved in Bluetooth audio streaming are around 30-40ms. But given the fact that Bluetooth physical layer data rate is of around 2-3 Mbps and today's Bluetooth ...
1
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2answers
504 views

CAS Latency and static RAM (SRAM)

Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However ...
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0answers
141 views

Calculate DRAM latency

I am trying to make some performance on a memory centric network which has one cpu and multiple memory cubes.(HMC) I want to calculate the intra HMC latency which means the latency between sending a ...
0
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1answer
590 views

Understanding USB processing and polling delay in USB host controller

I am doing measurements related USB delay with USB-UART converter chip(CP2102 Silicon laboratories chip). I am sending array of data, when 0xee is received the ...
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1answer
132 views

What limits the length of a cable? [closed]

As far as I can see this question has not been asked up to now but I'm not quite sure though I'm not an engineer.. But anyhow: Which parameters limit the length of a cable? On the one hand I know ...
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2answers
705 views

Communication between two STMs over 2 meter with small latency

I want to send messages back and forth between two STM32s. Probably STM32F407VET6, but it would be nice if I can try already something for a simple one (STM32F103C8T6). My requirements: round trip ...
2
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2answers
187 views

With IP-Cores without handshake protocol, how can I verify (VHDL assert?) their latency?

I'm using an IP-Core of Xilinx that was generated using the Vivado IDE's IP Catalog, specifically I'm using the Accumulator and the Multiplier IP Cores. These cores have a latency configuration of 6 ...
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2answers
277 views

Lowest possible latency, 1-way RF transmission

I am working on a wireless telemetry project with a bit of a twist. I have a CC3220 inside of a rotating shaft connected to an AMS board collecting pitch readings from a magnet mounted inside. The ...
8
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4answers
3k views

Interrupt latency on a STM32F303 MCU

I’m working on a project that involves a STM32 MCU (on the STM32303C-EVAL board to be exact) that has to respond to an external interrupt. I want the reaction to the external interrupt to be as fast ...
1
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1answer
422 views

Cas Latency vs Cpu to Memory Access Time

I'm so confused between cas latency and access time between cpu and memory. According to this wikipedia page, reading 8 word from ddr3-1600 sdram takes 15~ns,so between memory controller and sdram ...
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0answers
77 views

RF “Clock” - repeatable pulse for multiple receivers from master

I need to wirelessly (not optically, due to the distances and 3D volumes involved) transmit a "sync" pulse train from some master transmitter (the "time keeper") to be received by basically any number ...
3
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2answers
721 views

Latency of reading from a large array of i2c slaves?

What kind of latency is involved into the polling of a large number of i2c slaves? I have an array of 64 i2c sensors slaves which need to send 2 bytes each to the master as rapidly as possible. As ...
1
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1answer
130 views

Choosing Latency in an FPU

I wanted to use the Square-Root Operation of the FPU (6.1) in the Xilinx's Logic Core IP. I don't know what latency should I choose. Can someone help me with that? By default it chooses the maximum ...
1
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1answer
247 views

How many bits are addressed through one CAS command in DRAM?

From what I understand one column and row pairing corresponds to 64 bits from the DRAM chip, but this makes me think that one would then incur the CAS Latency (~18 clock cycles in DDR4) for EVERY ...
8
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1answer
2k views

Lowest latency out of the 802.11 Wi-Fi standards

I'm making a project using an Arduino and an ESP8266 module running the esp-link firmware - which gives me the ability to use MQTT for controlling the Arduino. I'd looked at something like an XBee ...
1
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1answer
1k views

Are AVR multi-cycle instructions pipelined?

Since AVR is a RISC architecture, most instructions only take a single cycle to execute. Still some need two or more cycles, e.g. adiw, which performs 16-bit ...
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2answers
105 views

How can light be timed?

There are measuring instruments that measure distance by measuring the time a lightbeam takes to come back. An example is a LICA scanner, that uses this tecnology to make 3D models of objects using ...
1
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1answer
141 views

Which RF comms solution allows unidirectional short distance low data rate, low latency communication to the largest amount of receivers?

I'm interested in delivering 3 bytes to a bunch of recipients roughly every 50ms with a single transmitter. The data sent is unique to each recipient. I am curious which existing wireless comms ...
1
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2answers
205 views

Question regarding 74HC574 (question very difficult to word)

Basically, I have a question regarding the timing of the 74HC574 octal latch. According to the timing diagram, the data pins must be set for so many nanoseconds before the latch pin (rising edge ...
2
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2answers
1k views

What is the precise use of a memory controller and RAM latency?

I'm learning about synchronous DRAM and it often mentioned a memory controller. What exactly is the point of this? Couldn't the cpu just take the job of requesting and receiving data with its own ...
1
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2answers
371 views

Low latency, high channel period wireless protocols

I was wondering if anyone can suggest any low latency high channel period wireless protocols or devices. I have been using the ANT and xbee chips to sample a digital signal however their channel ...
0
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1answer
165 views

Analog latency in an opamp circuit

Say we have 2 audio lines, one is driving an LED via an opamp circuit, and one is driving a speaker. Feeding the same pulse signal to both, are we able to detect latency between the time it takes for ...
4
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2answers
3k views

In an isolated SMPS feedback design, how could optocoupler latency be higher than the switching period?

I often see this in practical SMPS designs. An optocoupler & voltage reference pair is used for informing the controller section about the output voltage level. However, when I read the datasheet ...
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3answers
3k views

USB Device Latency

This is a theoretical question. I would like to know what the lowest latency is which can be achieved when interfacing a microcontroller with USB interface. Consider a USB host (computer) sending one ...
0
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1answer
337 views

Zedboard clock cycles analysis

Based on the example in here, I tried a very similar example (but instead of multiplying two matrices I just multiply all the elements in a matrix by 2.0). However, when comparing the results of ...
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3answers
2k views

What is the fastest and easiest way to transmit arduino's sensor data to a PC wirelessly

I have a specific problem : I'm working on a testing platform. It has to be absolutely isolated, so I cannot wire it back to my PC. I again reiterate it. There is no way to wire it to my PC. IT HAS ...
3
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1answer
636 views

Calculating latency for ADC chips

I am building a realtime based audio processing system that needs to sample 48KHz, 16bit audio, preferably with <0.5ms (the lower, the better) latency (Measured from analog signal -> data sampled ...
1
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1answer
620 views

Low latency rf link

I am working on making a low latency rf link that will be used as part of a feedback loop on a remote sensor. Because it is real-time the delay needs to be as small as possible (if sub milliseconds ...
4
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3answers
381 views

Can a barrel shifter be done combinatorially?

I was told that 66b/64b encoding in 10Gb Ethernet (10GBASE-R) requires a one-cycle barrel stage, which adds a necessary one cycle to the theoretical terminal latency. The Wikipedia page on barrel ...
2
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2answers
2k views

PC to Arduino wireless link (low latency)

I want to build a robot car with an camera gimbal on top of it. This robot and gimbal should be controlled wireless by a gamepad and the head tracking of an Oculus Rift. As it is with the Oculus Rift, ...
4
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4answers
725 views

How are LEDs timed? (How is the pulse latency measured?)

Please excuse the awkward phrasing of the question; it seems that LEDs have pulse latencies of nanosecond and sub-nanosecond durations. The question is, how was it possible to measure such precise ...
43
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2answers
16k views

What is the latency of an LED?

LEDs are known to have a very low, unnoticeable power-cycling latency, but how fast are they when measured? (nanoseconds?) In other words, how long does it take for an LED which is entirely off to ...
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2answers
468 views

Terms (bank,latency) in main memory?

A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c - byte chunks are mapped on consecutive banks with wrap-around. All the k banks ...
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3answers
3k views

Is there a correspondence between cache size and access latency?

Is there is a correspondence between cache sizes and access latency? All other things being equal, does a larger cache operate slower? If so, why? How much slower?
1
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1answer
853 views

DDR2 CAS Latency - is it fixed to clock-cycles or time?

We have a (new, prototype) board that is, at best, temperamental. It's using a Micron MT47H64M16HR-25:H DDR RAM, the design reference board uses a Micron MT47H64M16HR-25E:H. Only one letter different, ...