Questions tagged [latency]

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What does a chip's propagation delay vary on?

When looking up datasheets on logic gates, propagation delay is usually shown as a range. Sometimes there's a "typical" value in the middle, but there's a min and max listed. On what does ...
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2 answers
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Latency time of LED automotive strobe light

I am trying to build an automotive strobe light for a two-stroke engine. The problem with strobe lights sold in the market is I have not been able to find one which works well at high RPMs. My ...
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4 answers
140 views

What is the difference between throughput and operating frequency of a digital system?

I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
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-2 votes
1 answer
98 views

Why does it take so long to join a wifi network? [closed]

Accessing a text-only website, including TLS handshake, averages under half a second from first GET request to completely loaded, using my none-too-fast wifi. Yet ...
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0 votes
1 answer
143 views

Calculate throughput and latency

I have a project with a clock period of 5.9ns. During simulation, it takes 233 clock cycles to produce the output. Therefore, I calculated latency as 233*5.9 = 1347.7ns. Given the latency, how do I ...
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0 votes
1 answer
90 views

Loopback Latency of an Audio CODEC?

I'm thinking way ahead about a possible future project which will contain, among many other things, a "DIY hearing aid" of sorts. Microphones feeding earbuds with some DSP in between, all ...
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1 answer
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Sending an impulse to oscilloscope from software?

I am currently trying to measure the time it takes from [the moment a flag is set programmatically in software before rendering some graphics] to [[the moment the graphic is actually displayed on the ...
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0 votes
3 answers
81 views

Would this type of design be scale-able? [closed]

With current technologies within a modern system, we have pushed the limits of computations within the CPU portion of the system where it now exceeds that of the memory units. Moving memory is slow ...
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0 answers
294 views

How to remove 1 Clock Cycle Read Latency in single port BRAM

M using single port BRAM in always enabled mode, when I want to read the data from BRAM and write into the 2D array , its shows 1 clock cycle read latency means the data is not exact, after adding ...
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1 vote
1 answer
95 views

Latency time for logic gates?

today I learn about latency especially Tpdhl (high to low) and Tpdlh (low to high). My question is, let's suppose a gate has Tpdhl=8 and Tpdlh=6 so how much time it will take to process the input if ...
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2 votes
0 answers
116 views

Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my ...
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2 votes
0 answers
76 views

Approaches to creating better mouse pointing hardware for absolute input?

I play the video game osu!. Osu! is a game that requires the player to quickly move the mouse pointer to different areas of the screen in a precise manner. A game such as osu! lays out unique ...
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2 votes
0 answers
215 views

STM32 Timer Discrete Jitter

I'm using a STM32F746 running at 200MHz. A timer (tim2) is counting up at 100MHz and triggers an update interrupt with the following simplified ISR that writes a pattern to GPIOB ...
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1 vote
3 answers
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How to make fast (low latency) capacitive touch buttons

I'm looking to create low latency capacitive touch buttons for a musical instrument. The response time (from physical touch to touch registered in microcontroller) needs to be around ~2ms or less. ...
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0 votes
1 answer
67 views

Does Bluetooth Latency come from the Transmitter or Reciever?

I'm going to buy a low-latency bluetooth module that functions both as a tramsmitter as both receiver. Should I get just one to connect to my audio interface or do I also need one for my headphones if ...
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0 votes
2 answers
58 views

Uninterruptible power supply - How it manages to provide electricity to electronic devices before it shutting down?

I believe there is a lag in time (I think the latency for the switch over can take some milliseconds) when a switch over to the battery backup happens. I understand the electric appliances like motor, ...
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1 vote
1 answer
185 views

Low Jitter and Latency on signal trigger using WFI / WFE on STM32F405

I have a hobby project using a STM32F405 MCU, which is intended to respond to a fast clock signal (~1Mhz) connected to Pin 1 of GPIOA. For every transition of the input (both rising and falling), I ...
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0 votes
1 answer
48 views

What are the factors that affect delay/latency between base stations?

I am modelling a 5G network, with the uplink and downlink being decoupled and treated as separate networks. I am exploring the integration of fog computing and how latency varies between different ...
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23 votes
3 answers
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Why does RAM (any type) access time decrease so slowly?

This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns). A ...
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2 votes
0 answers
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quick path interconnect vs AXI

I want to know the performance difference between AXI and Intel's quick path interconnect which has been replaced by Ultra path interconnect(interms of latency). This is for very low latency(25 ...
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2 votes
4 answers
1k views

FT232HL FTDI consecutive SPI bytes delay problem

I have a problem with the FT232HL FTDI ic. Windows application send data to the chip via USB and the chip send the data out with one SPI channel. I did check with a logic analyser, the bytes are ...
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2 votes
4 answers
625 views

Maximum Clock Frequency

As an assignment for the HDL course I'm taking, I've to design an FIR Filter. The module consists of two a small combinational circuit which can be used to reset the module, another combinational part ...
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-1 votes
1 answer
98 views

What single feature will enable ultra low latencies for 5G communications? [closed]

there has been a recent buzz around 5G and its ultra low latency use cases. Additionally, some people claim that data rates around 10 Gbps are a feasible scenario if mmWaves are to be used. I was ...
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4 votes
2 answers
3k views

How can I measure latency in a CAN bus?

Given a CAN bus with one master and 4 motor drivers, is there a way to measure the time between sending a command from the master (e.g. PC or PLC) and the execution of the said command (e.g. the motor ...
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3 votes
2 answers
746 views

How to know the latency of an oscilloscope?

How can I know the latency of a digital oscilloscope in roll mode? By this I mean the time it takes from the signal reaching a certain value to the moment this value is shown on the screen, i.e. the ...
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6 votes
2 answers
10k views

Why is the latency so high for Bluetooth audio?

Referring to this, the lowest latencies achieved in Bluetooth audio streaming are around 30-40ms. Given the fact that Bluetooth physical layer data rate is of around 2-3 Mbps and today's Bluetooth ...
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1 vote
2 answers
847 views

CAS Latency and static RAM (SRAM)

Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However ...
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Calculate DRAM latency

I am trying to make some performance on a memory centric network which has one cpu and multiple memory cubes.(HMC) I want to calculate the intra HMC latency which means the latency between sending a ...
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0 votes
1 answer
949 views

Understanding USB processing and polling delay in USB host controller

I am doing measurements related USB delay with USB-UART converter chip(CP2102 Silicon laboratories chip). I am sending array of data, when 0xee is received the ...
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-3 votes
1 answer
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What limits the length of a cable? [closed]

As far as I can see this question has not been asked up to now but I'm not quite sure though I'm not an engineer.. But anyhow: Which parameters limit the length of a cable? On the one hand I know ...
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  • 555
0 votes
2 answers
913 views

Communication between two STMs over 2 meter with small latency

I want to send messages back and forth between two STM32s. Probably STM32F407VET6, but it would be nice if I can try already something for a simple one (STM32F103C8T6). My requirements: round trip ...
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2 votes
2 answers
195 views

With IP-Cores without handshake protocol, how can I verify (VHDL assert?) their latency?

I'm using an IP-Core of Xilinx that was generated using the Vivado IDE's IP Catalog, specifically I'm using the Accumulator and the Multiplier IP Cores. These cores have a latency configuration of 6 ...
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0 votes
2 answers
428 views

Lowest possible latency, 1-way RF transmission

I am working on a wireless telemetry project with a bit of a twist. I have a CC3220 inside of a rotating shaft connected to an AMS board collecting pitch readings from a magnet mounted inside. The ...
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8 votes
4 answers
5k views

Interrupt latency on a STM32F303 MCU

I’m working on a project that involves a STM32 MCU (on the STM32303C-EVAL board to be exact) that has to respond to an external interrupt. I want the reaction to the external interrupt to be as fast ...
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1 vote
1 answer
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Cas Latency vs Cpu to Memory Access Time

I'm so confused between cas latency and access time between cpu and memory. According to this wikipedia page, reading 8 word from ddr3-1600 sdram takes 15~ns,so between memory controller and sdram ...
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0 answers
87 views

RF "Clock" - repeatable pulse for multiple receivers from master

I need to wirelessly (not optically, due to the distances and 3D volumes involved) transmit a "sync" pulse train from some master transmitter (the "time keeper") to be received by basically any number ...
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3 votes
2 answers
1k views

Latency of reading from a large array of i2c slaves?

What kind of latency is involved into the polling of a large number of i2c slaves? I have an array of 64 i2c sensors slaves which need to send 2 bytes each to the master as rapidly as possible. As ...
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1 vote
1 answer
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Choosing Latency in an FPU

I wanted to use the Square-Root Operation of the FPU (6.1) in the Xilinx's Logic Core IP. I don't know what latency should I choose. Can someone help me with that? By default it chooses the maximum ...
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1 vote
1 answer
415 views

How many bits are addressed through one CAS command in DRAM?

From what I understand one column and row pairing corresponds to 64 bits from the DRAM chip, but this makes me think that one would then incur the CAS Latency (~18 clock cycles in DDR4) for EVERY ...
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8 votes
1 answer
2k views

Lowest latency out of the 802.11 Wi-Fi standards

I'm making a project using an Arduino and an ESP8266 module running the esp-link firmware - which gives me the ability to use MQTT for controlling the Arduino. I'd looked at something like an XBee ...
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2 votes
1 answer
2k views

Are AVR multi-cycle instructions pipelined?

Since AVR is a RISC architecture, most instructions only take a single cycle to execute. Still some need two or more cycles, e.g. adiw, which performs 16-bit ...
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1 vote
2 answers
112 views

How can light be timed?

There are measuring instruments that measure distance by measuring the time a lightbeam takes to come back. An example is a LICA scanner, that uses this tecnology to make 3D models of objects using ...
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2 votes
1 answer
164 views

Which RF comms solution allows unidirectional short distance low data rate, low latency communication to the largest amount of receivers?

I'm interested in delivering 3 bytes to a bunch of recipients roughly every 50ms with a single transmitter. The data sent is unique to each recipient. I am curious which existing wireless comms ...
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1 vote
2 answers
329 views

Question regarding 74HC574 (question very difficult to word)

Basically, I have a question regarding the timing of the 74HC574 octal latch. According to the timing diagram, the data pins must be set for so many nanoseconds before the latch pin (rising edge ...
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2 votes
2 answers
2k views

What is the precise use of a memory controller and RAM latency?

I'm learning about synchronous DRAM and it often mentioned a memory controller. What exactly is the point of this? Couldn't the cpu just take the job of requesting and receiving data with its own ...
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1 vote
2 answers
446 views

Low latency, high channel period wireless protocols

I was wondering if anyone can suggest any low latency high channel period wireless protocols or devices. I have been using the ANT and xbee chips to sample a digital signal however their channel ...
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0 votes
1 answer
290 views

Analog latency in an opamp circuit

Say we have 2 audio lines, one is driving an LED via an opamp circuit, and one is driving a speaker. Feeding the same pulse signal to both, are we able to detect latency between the time it takes for ...
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4 votes
2 answers
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In an isolated SMPS feedback design, how could optocoupler latency be higher than the switching period?

I often see this in practical SMPS designs. An optocoupler & voltage reference pair is used for informing the controller section about the output voltage level. However, when I read the datasheet ...
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1 vote
3 answers
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USB Device Latency

This is a theoretical question. I would like to know what the lowest latency is which can be achieved when interfacing a microcontroller with USB interface. Consider a USB host (computer) sending one ...
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  • 1,572
0 votes
1 answer
379 views

Zedboard clock cycles analysis

Based on the example in here, I tried a very similar example (but instead of multiplying two matrices I just multiply all the elements in a matrix by 2.0). However, when comparing the results of ...
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