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Questions tagged [latency]

The time delay between the cause and the effect of some physical change in a system, e.g. the time between a NAND gate's input changing and its output changing accordingly.

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Benefit of bank groups in DDR4 and beyond

I'm trying to understand how grouping the banks together can increase the throughput of DDRx. Reading into the sense amplifier appear to be the main bottleneck in DDRx throughput, however there is ...
Torben's user avatar
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1 answer
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What is the definition of DDR memory latency?

On Corsair's web site, they define memory latency with an equation: (Real Latency) = CAS Latency x 2000 / Data-rate My question is what that means in practice. Is this the delay from the time the ...
Dov's user avatar
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How far down the OSI model does one have to go to reduce latency in wireless protocols

I'm curious about protocols used for low latency peripheral devices. The famous examples would be Logitech's lightspeed, Razer's hyperspeed and Corsair's Slipstream. The main selling point of which is ...
Materia Gravis's user avatar
3 votes
2 answers
515 views

How to pipeline an algorithm that not only has latency but also relies on feedback of the previous run?

Trapped in this problem for several days, I feel I can't think of a proper solution on myself. The problem is as below. Say, a source-input is streaming a sequence of ...
xc wang's user avatar
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1 vote
0 answers
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Latency during UDP transmission via ESP-01S (ESP8266-01)

I'm working on a project that consists in sending data frames at a frequency of 200Hz, from a Teensy 4.1 to another, through two ESP-01S (See diagram and code below). Hardware : The system is composed ...
Juno's user avatar
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3 votes
2 answers
528 views

STM32 Interrupt large latency

I am writing an STM32F303 application to digitize pulse signal amplitudes. There will be a peak detector, that can be reset by the uC pin, so I'm not expecting the uC to instantly digitize as soon as ...
sx107's user avatar
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9 votes
3 answers
2k views

What does a chip's propagation delay vary on?

When looking up datasheets on logic gates, propagation delay is usually shown as a range. Sometimes there's a "typical" value in the middle, but there's a min and max listed. On what does ...
AltF4's user avatar
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Latency time of LED automotive strobe light

I am trying to build an automotive strobe light for a two-stroke engine. The problem with strobe lights sold in the market is I have not been able to find one which works well at high RPMs. My ...
Chinoy's user avatar
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1 vote
4 answers
631 views

What is the difference between throughput and operating frequency of a digital system?

I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
AugmentiuM's user avatar
-2 votes
1 answer
162 views

Why does it take so long to join a wifi network? [closed]

Accessing a text-only website, including TLS handshake, averages under half a second from first GET request to completely loaded, using my none-too-fast wifi. Yet ...
TheEnvironmentalist's user avatar
0 votes
2 answers
646 views

Calculate throughput and latency

I have a project with a clock period of 5.9ns. During simulation, it takes 233 clock cycles to produce the output. Therefore, I calculated latency as 233*5.9 = 1347.7ns. Given the latency, how do I ...
ChrisMcNeill's user avatar
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2 answers
248 views

Loopback Latency of an Audio CODEC?

I'm thinking way ahead about a possible future project which will contain, among many other things, a "DIY hearing aid" of sorts. Microphones feeding earbuds with some DSP in between, all ...
AaronD's user avatar
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0 votes
1 answer
117 views

Sending an impulse to oscilloscope from software?

I am currently trying to measure the time it takes from [the moment a flag is set programmatically in software before rendering some graphics] to [[the moment the graphic is actually displayed on the ...
inquisitiveck's user avatar
0 votes
3 answers
88 views

Would this type of design be scale-able? [closed]

With current technologies within a modern system, we have pushed the limits of computations within the CPU portion of the system where it now exceeds that of the memory units. Moving memory is slow ...
Francis Cugler's user avatar
1 vote
1 answer
213 views

Latency time for logic gates?

today I learn about latency especially Tpdhl (high to low) and Tpdlh (low to high). My question is, let's suppose a gate has Tpdhl=8 and Tpdlh=6 so how much time it will take to process the input if ...
White Force's user avatar
2 votes
0 answers
463 views

Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my ...
Natasha A.'s user avatar
2 votes
0 answers
119 views

Approaches to creating better mouse pointing hardware for absolute input?

I play the video game osu!. Osu! is a game that requires the player to quickly move the mouse pointer to different areas of the screen in a precise manner. A game such as osu! lays out unique ...
Árni Dagur's user avatar
2 votes
0 answers
528 views

STM32 Timer Discrete Jitter

I'm using a STM32F746 running at 200MHz. A timer (tim2) is counting up at 100MHz and triggers an update interrupt with the following simplified ISR that writes a pattern to GPIOB ...
1uk3's user avatar
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1 vote
4 answers
1k views

How to make fast (low latency) capacitive touch buttons

I'm looking to create low latency capacitive touch buttons for a musical instrument. The response time (from physical touch to touch registered in microcontroller) needs to be around ~2ms or less. ...
Jeremiah Rose's user avatar
0 votes
1 answer
110 views

Does Bluetooth Latency come from the Transmitter or receiver?

I'm going to buy a low-latency Bluetooth module that functions both as a transmitter as both receiver. Should I get just one to connect to my audio interface or do I also need one for my headphones if ...
user avatar
0 votes
2 answers
68 views

Uninterruptible power supply - How it manages to provide electricity to electronic devices before it shutting down?

I believe there is a lag in time (I think the latency for the switch over can take some milliseconds) when a switch over to the battery backup happens. I understand the electric appliances like motor, ...
Franc's user avatar
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1 vote
1 answer
278 views

Low Jitter and Latency on signal trigger using WFI / WFE on STM32F405

I have a hobby project using a STM32F405 MCU, which is intended to respond to a fast clock signal (~1Mhz) connected to Pin 1 of GPIOA. For every transition of the input (both rising and falling), I ...
Johnny Egeland's user avatar
0 votes
1 answer
56 views

What are the factors that affect delay/latency between base stations?

I am modelling a 5G network, with the uplink and downlink being decoupled and treated as separate networks. I am exploring the integration of fog computing and how latency varies between different ...
Klaus's user avatar
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23 votes
3 answers
6k views

Why does RAM (any type) access time decrease so slowly?

This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns). A ...
Arseniy's user avatar
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2 votes
0 answers
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quick path interconnect vs AXI

I want to know the performance difference between AXI and Intel's quick path interconnect which has been replaced by Ultra path interconnect(interms of latency). This is for very low latency(25 ...
NIVETHA SUKUMAR's user avatar
2 votes
4 answers
2k views

FT232HL FTDI consecutive SPI bytes delay problem

I have a problem with the FT232HL FTDI ic. Windows application send data to the chip via USB and the chip send the data out with one SPI channel. I did check with a logic analyser, the bytes are ...
ggadde29's user avatar
2 votes
4 answers
1k views

Maximum Clock Frequency

As an assignment for the HDL course I'm taking, I've to design an FIR Filter. The module consists of two a small combinational circuit which can be used to reset the module, another combinational part ...
Mohammed Farahmand's user avatar
-1 votes
1 answer
101 views

What single feature will enable ultra low latencies for 5G communications? [closed]

there has been a recent buzz around 5G and its ultra low latency use cases. Additionally, some people claim that data rates around 10 Gbps are a feasible scenario if mmWaves are to be used. I was ...
Luísa Suda's user avatar
4 votes
2 answers
6k views

How can I measure latency in a CAN bus?

Given a CAN bus with one master and 4 motor drivers, is there a way to measure the time between sending a command from the master (e.g. PC or PLC) and the execution of the said command (e.g. the motor ...
mohsen's user avatar
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3 votes
2 answers
986 views

How to know the latency of an oscilloscope?

How can I know the latency of a digital oscilloscope in roll mode? By this I mean the time it takes from the signal reaching a certain value to the moment this value is shown on the screen, i.e. the ...
freejuices's user avatar
6 votes
2 answers
12k views

Why is the latency so high for Bluetooth audio?

Referring to this, the lowest latencies achieved in Bluetooth audio streaming are around 30-40ms. Given the fact that Bluetooth physical layer data rate is of around 2-3 Mbps and today's Bluetooth ...
Ashutosh's user avatar
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2 votes
2 answers
1k views

CAS Latency and static RAM (SRAM)

Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However ...
Bemipefe's user avatar
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0 votes
0 answers
301 views

Calculate DRAM latency

I am trying to make some performance on a memory centric network which has one cpu and multiple memory cubes.(HMC) I want to calculate the intra HMC latency which means the latency between sending a ...
Arghavan Mohammadhassani's user avatar
0 votes
1 answer
1k views

Understanding USB processing and polling delay in USB host controller

I am doing measurements related USB delay with USB-UART converter chip(CP2102 Silicon laboratories chip). I am sending array of data, when 0xee is received the ...
yadhu's user avatar
  • 101
-3 votes
1 answer
146 views

What limits the length of a cable? [closed]

As far as I can see this question has not been asked up to now but I'm not quite sure though I'm not an engineer.. But anyhow: Which parameters limit the length of a cable? On the one hand I know ...
Ben's user avatar
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0 votes
2 answers
1k views

Communication between two STMs over 2 meter with small latency

I want to send messages back and forth between two STM32s. Probably STM32F407VET6, but it would be nice if I can try already something for a simple one (STM32F103C8T6). My requirements: round trip ...
Michel Keijzers's user avatar
2 votes
2 answers
234 views

With IP-Cores without handshake protocol, how can I verify (VHDL assert?) their latency?

I'm using an IP-Core of Xilinx that was generated using the Vivado IDE's IP Catalog, specifically I'm using the Accumulator and the Multiplier IP Cores. These cores have a latency configuration of 6 ...
Johannes Schaub - litb's user avatar
0 votes
2 answers
763 views

Lowest possible latency, 1-way RF transmission

I am working on a wireless telemetry project with a bit of a twist. I have a CC3220 inside of a rotating shaft connected to an AMS board collecting pitch readings from a magnet mounted inside. The ...
old_dd's user avatar
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9 votes
4 answers
7k views

Interrupt latency on a STM32F303 MCU

I’m working on a project that involves a STM32 MCU (on the STM32303C-EVAL board to be exact) that has to respond to an external interrupt. I want the reaction to the external interrupt to be as fast ...
K.R.'s user avatar
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1 vote
1 answer
530 views

Cas Latency vs Cpu to Memory Access Time

I'm so confused between cas latency and access time between cpu and memory. According to this wikipedia page, reading 8 word from ddr3-1600 sdram takes 15~ns,so between memory controller and sdram ...
spartacus's user avatar
  • 151
0 votes
0 answers
101 views

RF "Clock" - repeatable pulse for multiple receivers from master

I need to wirelessly (not optically, due to the distances and 3D volumes involved) transmit a "sync" pulse train from some master transmitter (the "time keeper") to be received by basically any number ...
KyranF's user avatar
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3 votes
2 answers
2k views

Latency of reading from a large array of i2c slaves?

What kind of latency is involved into the polling of a large number of i2c slaves? I have an array of 64 i2c sensors slaves which need to send 2 bytes each to the master as rapidly as possible. As ...
dtech's user avatar
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1 vote
1 answer
173 views

Choosing Latency in an FPU

I wanted to use the Square-Root Operation of the FPU (6.1) in the Xilinx's Logic Core IP. I don't know what latency should I choose. Can someone help me with that? By default it chooses the maximum ...
Vinam Arora's user avatar
1 vote
1 answer
751 views

How many bits are addressed through one CAS command in DRAM?

From what I understand one column and row pairing corresponds to 64 bits from the DRAM chip, but this makes me think that one would then incur the CAS Latency (~18 clock cycles in DDR4) for EVERY ...
Erik Anderson's user avatar
8 votes
1 answer
2k views

Lowest latency out of the 802.11 Wi-Fi standards

I'm making a project using an Arduino and an ESP8266 module running the esp-link firmware - which gives me the ability to use MQTT for controlling the Arduino. I'd looked at something like an XBee ...
seanlano's user avatar
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3 votes
1 answer
3k views

Are AVR multi-cycle instructions pipelined?

Since AVR is a RISC architecture, most instructions only take a single cycle to execute. Still some need two or more cycles, e.g. adiw, which performs 16-bit ...
polwel's user avatar
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1 vote
2 answers
117 views

How can light be timed?

There are measuring instruments that measure distance by measuring the time a lightbeam takes to come back. An example is a LICA scanner, that uses this tecnology to make 3D models of objects using ...
sharkyenergy's user avatar
2 votes
1 answer
174 views

Which RF comms solution allows unidirectional short distance low data rate, low latency communication to the largest amount of receivers?

I'm interested in delivering 3 bytes to a bunch of recipients roughly every 50ms with a single transmitter. The data sent is unique to each recipient. I am curious which existing wireless comms ...
Sanuuu's user avatar
  • 387
1 vote
2 answers
400 views

Question regarding 74HC574 (question very difficult to word)

Basically, I have a question regarding the timing of the 74HC574 octal latch. According to the timing diagram, the data pins must be set for so many nanoseconds before the latch pin (rising edge ...
KeatonB's user avatar
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2 votes
2 answers
2k views

What is the precise use of a memory controller and RAM latency?

I'm learning about synchronous DRAM and it often mentioned a memory controller. What exactly is the point of this? Couldn't the cpu just take the job of requesting and receiving data with its own ...
Derek Farkas's user avatar