Questions tagged [lattice]

Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.

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Flash terminology and meaning

I am trying to choose an SPI flash device for my FPGA and I want to verify if I am understanding the terminology correctly. Bitstream is the configuration data code used to implement the logic in the ...
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1answer
69 views

FPGA pin numbers

I'm having trouble understanding the structure of FPGA datasheets. From what I can tell, there is usually a table of "Signals Descriptions" with the pin names and their function, but I don't ...
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1answer
82 views

FPGA pins driven high at power-up ‒ what can I do to get around this?

I have a board that uses a Lattice XP2-8 (BGA256, in case it makes any difference). Some FPGA pins are connected directly to LEDs with positive logic. That is: simulate this circuit – ...
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2answers
80 views

IO Type (LVCMOS25, LVCMOS18, etc.) in FPGA pins

In Lattice Diamond, spreadsheet view where I assign the signals to pins of the FPGA chip, there is IO type. Restricting the discussion to single-ended CMOS signals, then my choices are given by the ...
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33 views

Linking/Compiling lib for ModelSim

I'm trying to simulate a SerDes for the Lattice ECP5 FPGA and have an issue linking the correct lib in ModelSim. Error message: ...
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1answer
170 views

Why is this power-on reset generator Verilog module getting optimized out?

I am trying to write a Verilog module that generates a power-on reset signal for a few clock cycles. I am synthesizing using Lattice iCEcube2 + Synplify Pro targeting an iCE40 HX1K on the Nandland Go ...
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85 views

Lattice Diamond: Unconnected input pins

I'm trying to do a simple pin layout exercise and tried a very simple module to begin with. However, when I look to the spreadsheet viewer, my inputs are unconnected: Here is my code: ...
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39 views

Lattice XP2 -- what is the significance of Pin/Ball function?

Looking at the various XP2 pinout files, or the migration files (for example, the BGA256 migration file), I see that GPIO pins have identifiers ("Pin/Ball Function") such as PB20A, PB20B (...
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1answer
44 views

ECP5 Versa Board Example

I'm struggling to get my design on the ECP5 Versa board running. Currently it's just for hardware verification so there's not much going on. So this is my top entity... ...
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Lattice Diamond Clock Assignment issue with ECP5 Versa

I try to get a Lattice ECP5 Versa Board running but I struggle with the port assignment for my clock as I don't understand what exactly Lattice Diamond is doing. It's the first time I'm working with ...
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1answer
66 views

Lattice Diamond — How to identify which parts of design take most of FPGA resources?

I have a Lattice FPGA-targeted design which already takes approximately 95% of the SLICEs available on the device; pretty close to the chip capacity. Unfortunately, I need to add some more logic to it,...
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119 views

Lattice Diamond assign unconnected poin

I used to work with the Lattice IceCube IDE where I just constrained all pins to the corresponding signal not matter whether they were actually used in the design or not. No I have to create a new ...
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23 views

Lattice iCECube2 cannot find clock in .sdc file

I've tried a zillion different ways to get the lattice iCECube2 tools to find a generated clock. How do I specify the .sdc file to see the output of baudgeninst, ...
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1answer
49 views

Which software tools from LatticeSemiconductor do I need to develop design with iCE40 LP FPGA?

There are a lot of programs that can be found here: https://www.latticesemi.com/en/Products/DesignSoftwareAndIP Which of these do I need for creating a design with iCE40 LP FPGA? The reason for my ...
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39 views

Lattice iCEcube2 "unexpected error"

Not sure if anyone can help me with this... I have a rather large/complex design which so far was syntheziable without problems but with the last (although very simple changes) my iCEcube2 gives me an ...
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2answers
81 views

Troubleshooting tinyprog when programming TinyFPGA BX: [Errno 19] No such device

I am using the TinyFPGA BX for the first time, and tinyprog crashes when I try to program the board. First, I run apio build, ...
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1answer
70 views

No port matched and or doesnt connect to anything

Good evening, I'm having some issues with some verilog code, or quiet a lot to be honest. Or with Lattice's software actually.. This was tried in Lattice Radiant. First off, I'm getting these warnings(...
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75 views

ICE40HX8K programming concepts

I have some question about programming options for ICE40HX8K-BG121 These are some facts I’ve collected which are causing some confusion: The iCE40HX-8K Breakout Board uses an FTDI USB-to-SPI chip to ...
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64 views

problems with Lattice Reveal Analyzer - JTAG chain with multiple devices on the chain

I have a board with JTAG chain with 2 devices - (1) TI MCU (2) Lattice MachXO2, in the chain. To be able to program the FPGA, I'm using this configuration in Lattice Diamond: and as can be seen the ...
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1answer
36 views

Can propagation delays be simulated in Active-HDL?

I'm using the Lattice Diamond licensed version of Aldec Active-HDL. The logic circuits I'm working with are complex enough that I believe propagation delays could have an impact on the actual function ...
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Lattice FPGA: Mach X02 7000 Can it be used for DSP?

I have a MachX02 7000 having 6800 LUT's. I want to implement DSP algorithm involving floating-point DSP algorithm on 2 14 bit ADC input data. Is it possible to perform on this FPGA with low LUT's, No ...
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1answer
63 views

Xilinx equivalent for Lattice's Input DDR generic mode in X2 gearing primitive

I used to work with Lattice FPGA (Lattice ECP3) and I used to have this primitive: IDDRX2D1 the block internal circuit: I can't find an equivalent for this kind of input DDR in Xilinx Series 7 ...
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1answer
135 views

JK flip flop using gate level description in Verilog gives me a timing error

I'm still playing in the lowest Verilog level (gate level). I found this post: Is it possible to create a working JK-flip flop using gate level description in Verilog In that, I could understand that ...
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36 views

Lattice ispLSI CLPD dump/transfer hex file

I have two boards that contain Lattice ISPLSI1016-60LT44, one is dead in short circuit (is is very hot when powered also), one is on working condition. Even though this part is discontinued by the ...
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1answer
40 views

Lattice XP2 -- Different voltages for different IO banks?

As the subject indicates: can I use different voltages for the different IO banks? (1.8V for some, 3.3V for some others) Neither the datasheet nor the hardware checklist technical note explicitly ...
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1answer
50 views

Meaning of numbers inside parentheses in Lattice Synthesis Engine Utilization Report?

I'm using Lattice Radiant 2.0 to synthesize a design. In the "Synthesis Utilization Report file", I see the following line: ...
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162 views

Lattice Diamond/Reveal throws error with Bitstream File programming

I recently started using Lattice MachX03L device for a project. I have a design and with Reveal I wanted to look at the signals. When I program a JEDEC file into the FPGA I can observe the signals in ...
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0answers
54 views

Lattice FPGAs -- How to control skew on signals routed to IO pins?

Working with: Lattice XP2-30 or XP2-40 Tentatively a BGA484; almost certainly some BGA 1mm-pitch package Synplify PRO, with SystemVerilog Skill level: Beginner / early-intermediate. If I have a ...
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1answer
187 views

Why can't I assign pin 18 on Lattice MachXO2-256-HC FPGA in my design?

I'm using a Lattice spreadsheet view inside of Diamond with a MachXO2-256-HC-4TG100C. When I assign pin 18 to a port on my design, I get an error: ...
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1answer
45 views

Powering Evaluation Board, Voltage Regulator Fizzles Out

I'm trying to power a FPGA evaluation board using a 5V linear voltage regulator. I supply the 5V through the USB connector as shown: (this goes to the microUSB on the board) For a basic test, I power ...
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1answer
217 views

There is a way to write into FIFO on both clock edges?

Im using Lattice ECP3 FPGA, didnt found any information about it on the internet. I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface: This ...
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2answers
185 views

ice40-hx8k: Weird input pin behaviour regarding digital HI voltage level

I am playing around with a FPGA dev board featuring the Lattice ICE40-HX8K using the yosys/icestorm OpenSource toolchain, and I have noticed very odd behaviour my input pins are showing: When I use a ...
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1answer
137 views

Bad results from using Lattice FPGA Interface to capture ADC data

Im trying to capture DDR data from ADS5463 (TI ADC). As the datasheet suggested I need to delay the clock and sample the data with DRY clock. Im using Lattice FPGA LFE3-35EA.. and using Lattice High ...
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1answer
282 views

Lattice FPGA problems with built-in DELAY module

I'm trying to delay an input data coming from ADC component in DDR to my FPGA, afterwards output it in the clock rising edge. The ADC Im using: ADS5463: Im using Lattice ECP3 FPGA, based on the fpga ...
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2answers
183 views

How to Output DDR data to 1 register

I have an Input which provides DDR data, I need to capture it and output it from the FPGA in one register (12bit). How can I do it? What I did for now is to capture the input data with always block ...
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1answer
80 views

Questions about Interfacing ADC: ADS5463 with FPGA

Im beginner FPGA Designer. I need to interface the ADC component: ADS5463. datasheet: http://www.ti.com/lit/ds/symlink/ads5463.pdf with a FPGA (lattice ecp3). I need suggestions how to start ...
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1answer
249 views

How can I make Lattice Symplify Pro infer RAM correctly from VHDL code?

I have a design on an iCE40 FPGA, I use iCEcube2 to compile the VHDL code and in my design I try to infer two small RAM buffers. The type of the buffers is as follow : ...
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1answer
106 views

IDDRX2 Lattice FPGA module

I saw in a code usage of the module IDDRX2D1, this module is inside the FPGA Lattice ECP3, I found from its Libraries Ref Guide this information: someone can help me about what is it and for what is ...
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Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
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1answer
62 views

TinyFPGA A Series Board programmer compatibility

Since the TinyFPGA programmer writes configurations to the Flash memory of the FPGA chip, can I use that programmer for A series boards on any LCMXO2 chip? Or can I at least use it for the same chip ...
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1answer
447 views

Implementing 4-bit counter on GAL 16V8

I want to use a GAL 16V8 to implement a 4-bit counter using Verilog. I'm using Lattice's ispLEVER software. So far I have had no issues using Verilog to implement combinational logic. However, I ...
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1answer
585 views

Lattice MachXO2 reset

After reading about GSR/PUR facilities in Lattice FPGAs, I'm still a bit puzzled about how to actually get the proper GSR/PUR-based reset functionality on an actual physical FPGA chip. In the How to ...
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1answer
81 views

Lattice — Should I prefer IPX/PMI over Verilog arithmetic builtins?

Like any FPGA vendor, Lattice provides a number of IP modules for users to put in their designs. I tend to use them whenever possible, but sometimes I doubt if they have any substantial benefit over ...
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1answer
65 views

Trouble with double-buffer structure -- MachXO2 using FIFO_DC from IPExpress

In reference to this recent question: I'm seeing a problem with that scheme (the second figure, using the FIFOs as "circular buffers", or shift-registers so that old samples are extracted as discarded ...
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1answer
470 views

Diamond: Warning: logical net has no load

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: ...
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2answers
596 views

Verilog -- how to assign mux/selector output to module's output

Verilog beginner here. Working with Lattice Diamond for a design using the MachXO2. For context: I recently got this answer to a related question. See the second image in the answer. I want to ...
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1answer
82 views

PISO buffer for the MachXO2

I'm trying to design a "double-buffer" structure similar to that used in UARTs (for receiving). In my case, it is for samples from an ADC. I shift them in, and at some point my logic detects a ...
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2answers
736 views

Programming (flashing) MachXO2 chips through JTAG

I'm trying the MachXO2 7000HE Breakout Board --- I could make a simple demo work (following this nice Youtube video). Since I want to include one of these chips in my next design, I want to learn ...
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1answer
184 views

Getting started with TinyFPGA board (Lattice Semiconductor MACHXO2 chip)

I'm a bit of a newbie with FPGAs. Trying to run the project from the "Getting Started" section of the Lattice Diamond manual. These are the source files: count.v: ...
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1answer
496 views

Generate XCF file for Lattice Diamond from command line

I am writing a Makefile for Lattice Diamond and have come as far as to cover all steps from synthesis to bitfile. To program the FPGA (a MachXO3L in my case) I looked for a command line tool, and ...