Questions tagged [lattice]

Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.

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problems with Lattice Reveal Analyzer - JTAG chain with multiple devices on the chain

I have a board with JTAG chain with 2 devices - (1) TI MCU (2) Lattice MachXO2, in the chain. To be able to program the FPGA, I'm using this configuration in Lattice Diamond: and as can be seen the ...
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Can propagation delays be simulated in Active-HDL?

I'm using the Lattice Diamond licensed version of Aldec Active-HDL. The logic circuits I'm working with are complex enough that I believe propagation delays could have an impact on the actual function ...
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Lattice FPGA: Mach X02 7000 Can it be used for DSP?

I have a MachX02 7000 having 6800 LUT's. I want to implement DSP algorithm involving floating-point DSP algorithm on 2 14 bit ADC input data. Is it possible to perform on this FPGA with low LUT's, No ...
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51 views

Xilinx equivalent for Lattice's Input DDR generic mode in X2 gearing primitive

I used to work with Lattice FPGA (Lattice ECP3) and I used to have this primitive: IDDRX2D1 the block internal circuit: I can't find an equivalent for this kind of input DDR in Xilinx Series 7 ...
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61 views

JK-flip flop using gate level description in Verilog give me a timming error

I still playing in the lowest Verilog level (gate level). I found this post: Is it possible to create a working JK-flip flop using gate level description in Verilog in that I could understand that ...
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57 views

Lattice Diamond FPGA set false path in lpf file

For a Lattice FPGA using the Diamond/Synplify Pro tools, I have a clock domain crosser circuit that I'd like to turn off timing analysis for (since it's guaranteed to fail) using *.lpf commands. I've ...
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Lattice ispLSI CLPD dump/transfer hex file

I have two boards that contain Lattice ISPLSI1016-60LT44, one is dead in short circuit (is is very hot when powered also), one is on working condition. Even though this part is discontinued by the ...
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32 views

Lattice XP2 — Different voltages for different IO banks?

As the subject indicates: can I use different voltages for the different IO banks? (1.8V for some, 3.3V for some others) Neither the datasheet nor the hardware checklist technical note explicitly ...
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39 views

Meaning of numbers inside parentheses in Lattice Synthesis Engine Utilization Report?

I'm using Lattice Radiant 2.0 to synthesize a design. In the "Synthesis Utilization Report file", I see the following line: ...
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56 views

Lattice Diamond/Reveal throws error with Bitstream File programming

I recently started using Lattice MachX03L device for a project. I have a design and with Reveal I wanted to look at the signals. When I program a JEDEC file into the FPGA I can observe the signals in ...
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Lattice FPGAs — How to control skew on signals routed to IO pins?

Working with: Lattice XP2-30 or XP2-40 Tentatively a BGA484; almost certainly some BGA 1mm-pitch package Synplify PRO, with SystemVerilog Skill level: Beginner / early-intermediate. If I have a ...
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Mico32 Microcontroller on Lattice ECP3 FPGA

Im trying to design an Ethernet Interface on Lattice ECP3 (versa board), for this I have to use Lattice built in micro-controller on the ECP3 SOC from Lattice: I cant find any reference for how to ...
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42 views

Lattice MachXO2 EFB Timer/Counter timing specification missing

Searching through Lattice FPGA-DS-02056 (MachXO2 Family Data Sheet) and TN1205 (Using User Flash Memory and Hardened Control Functions in MachXO2 Devices), I couldn't find a detailed specification of ...
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116 views

Why can't I assign pin 18 on Lattice MachXO2-256-HC FPGA in my design?

I'm using a Lattice spreadsheet view inside of Diamond with a MachXO2-256-HC-4TG100C. When I assign pin 18 to a port on my design, I get an error: ...
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43 views

Powering Evaluation Board, Voltage Regulator Fizzles Out

I'm trying to power a FPGA evaluation board using a 5V linear voltage regulator. I supply the 5V through the USB connector as shown: (this goes to the microUSB on the board) For a basic test, I power ...
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100 views

There is a way to write into FIFO on both clock edges?

Im using Lattice ECP3 FPGA, didnt found any information about it on the internet. I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface: This ...
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129 views

ice40-hx8k: Weird input pin behaviour regarding digital HI voltage level

I am playing around with a FPGA dev board featuring the Lattice ICE40-HX8K using the yosys/icestorm OpenSource toolchain, and I have noticed very odd behaviour my input pins are showing: When I use a ...
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110 views

Bad results from using Lattice FPGA Interface to capture ADC data

Im trying to capture DDR data from ADS5463 (TI ADC). As the datasheet suggested I need to delay the clock and sample the data with DRY clock. Im using Lattice FPGA LFE3-35EA.. and using Lattice High ...
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167 views

Lattice FPGA problems with built-in DELAY module

I'm trying to delay an input data coming from ADC component in DDR to my FPGA, afterwards output it in the clock rising edge. The ADC Im using: ADS5463: Im using Lattice ECP3 FPGA, based on the fpga ...
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92 views

How to Output DDR data to 1 register

I have an Input which provides DDR data, I need to capture it and output it from the FPGA in one register (12bit). How can I do it? What I did for now is to capture the input data with always block ...
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66 views

Questions about Interfacing ADC: ADS5463 with FPGA

Im beginner FPGA Designer. I need to interface the ADC component: ADS5463. datasheet: http://www.ti.com/lit/ds/symlink/ads5463.pdf with a FPGA (lattice ecp3). I need suggestions how to start ...
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131 views

How can I make Lattice Symplify Pro infer RAM correctly from VHDL code?

I have a design on an iCE40 FPGA, I use iCEcube2 to compile the VHDL code and in my design I try to infer two small RAM buffers. The type of the buffers is as follow : ...
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65 views

IDDRX2 Lattice FPGA module

I saw in a code usage of the module IDDRX2D1, this module is inside the FPGA Lattice ECP3, I found from its Libraries Ref Guide this information: someone can help me about what is it and for what is ...
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Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
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320 views

Implementing 4-bit counter on GAL 16V8

I want to use a GAL 16V8 to implement a 4-bit counter using Verilog. I'm using Lattice's ispLEVER software. So far I have had no issues using Verilog to implement combinational logic. However, I ...
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338 views

Lattice MachXO2 reset

After reading about GSR/PUR facilities in Lattice FPGAs, I'm still a bit puzzled about how to actually get the proper GSR/PUR-based reset functionality on an actual physical FPGA chip. In the How to ...
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61 views

Lattice — Should I prefer IPX/PMI over Verilog arithmetic builtins?

Like any FPGA vendor, Lattice provides a number of IP modules for users to put in their designs. I tend to use them whenever possible, but sometimes I doubt if they have any substantial benefit over ...
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54 views

Trouble with double-buffer structure — MachXO2 using FIFO_DC from IPExpress

In reference to this recent question: I'm seeing a problem with that scheme (the second figure, using the FIFOs as "circular buffers", or shift-registers so that old samples are extracted as discarded ...
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1answer
306 views

Diamond: Warning: logical net has no load

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: ...
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2answers
371 views

Verilog — how to assign mux/selector output to module's output

Verilog beginner here. Working with Lattice Diamond for a design using the MachXO2. For context: I recently got this answer to a related question. See the second image in the answer. I want to ...
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72 views

PISO buffer for the MachXO2

I'm trying to design a "double-buffer" structure similar to that used in UARTs (for receiving). In my case, it is for samples from an ADC. I shift them in, and at some point my logic detects a ...
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493 views

Programming (flashing) MachXO2 chips through JTAG

I'm trying the MachXO2 7000HE Breakout Board --- I could make a simple demo work (following this nice Youtube video). Since I want to include one of these chips in my next design, I want to learn ...
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141 views

Getting started with TinyFPGA board (Lattice Semiconductor MACHXO2 chip)

I'm a bit of a newbie with FPGAs. Trying to run the project from the "Getting Started" section of the Lattice Diamond manual. These are the source files: count.v: ...
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299 views

Generate XCF file for Lattice Diamond from command line

I am writing a Makefile for Lattice Diamond and have come as far as to cover all steps from synthesis to bitfile. To program the FPGA (a MachXO3L in my case) I looked for a command line tool, and ...
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374 views

Lattice Diamond Port 'direction' is unconnected

I am following the tutorial to turn on the LED on the embedded vision development kit found in: C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v ...
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34 views

What is the design tool for Lattice HDR-60 Video Camera Development Kit?

I have recently received HDR-60 Video Camera Development Kit. I was excited to do some verilog coding for HDMI interface. Design software I have downloaded was iCEcube2 2017.08 (Licence will provided ...
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397 views

Lattice Machxo3 FPGA configuration using I2C

I have a Lattice Machxo3 FPGA based design / board and currently I am configuring the FPGA using JTAG. As per the datasheet I2C also can used as the FPGA configuration interface. Is it possible to use ...
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252 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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346 views

Lattice LCMXO2-256HC-4SG32C CHECK_SECURITY_PROTECT_KEY error

Trying to progamm LCMXO2-256HC-4SG32C with this ebay progammer. The programmer works fine with LCMX02-1200HC-4TG144C, but with LCMXO2-256HC-4SG32C it gives me the following output: ...
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1answer
157 views

Should FPGA interface an IC using more than one IO bank?

I would like to interface a FPGA with a fairly fast IC. My FPGA is MachXO2-7000HC while the IC in question is FTDI's FT601, which is a USB 3.0 to FIFO bridge. The FT601 has quite a few control/data ...
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479 views

Creating a Counter in Verilog for Flashing LED on Lattice Starter Kit

I have a lattic X03LF starter board with 6900C FGPA. There are eight LED available on this board and a push button. The goal of my code is to design a 8 bit counter that increments whenever a button ...
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212 views

Problem with adding two counters in series on an FPGA

I am using Verilog in Lattice Diamond IDE with a lattice MachXO2 7000HE breakout board. I built a basic counter with a limit input which generates a variable period clock output. It works fine on its ...
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I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal. I would have understood a Set signal. I would have understood a ...
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679 views

Is it possible to generate internal reset pulse in verilog with machxo3lf fpga?

I have a board without Reset input for my design. But I need to reset at fpga startup. Is there a verilog solution to generate this pulse ?
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How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...
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445 views

How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3

I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their ...
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206 views

What is the exact definition of propagation constant of a two-port network?

Wikipedia says that the propagation constant of a lattice network is $$\gamma = \ln\left[\frac{\sqrt{\frac{Z_a}{Z_b}}+1}{\sqrt{\frac{Z_a}{Z_b}}-1}\right]$$ Wikipedia also says that "In the context ...
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2answers
279 views

digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge

I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this ...
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1answer
2k views

How the slew-rate and drive strength affect the output signal of the FPGA?

Can someone describe the difference between the drive strength and the slew-rate preferences in Lattice FPGA?
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178 views

Packing register pairs on Lattice FPGA slice. How?

On my design (Lattice MachXO2 FPGA) I use a lot of registers set by a signal and reset by another (both synchronous with the clock), like this: ...