Questions tagged [lattice]

Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.

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54 views

Getting started with TinyFPGA board (Lattice Semiconductor MACHXO2 chip)

I'm a bit of a newbie with FPGAs. Trying to run the project from the "Getting Started" section of the Lattice Diamond manual. These are the source files: count.v: ...
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Generate XCF file for Lattice Diamond from command line

I am writing a Makefile for Lattice Diamond and have come as far as to cover all steps from synthesis to bitfile. To program the FPGA (a MachXO3L in my case) I looked for a command line tool, and ...
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58 views

Lattice Diamond Port 'direction' is unconnected

I am following the tutorial to turn on the LED on the embedded vision development kit found in: C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v ...
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30 views

What is the design tool for Lattice HDR-60 Video Camera Development Kit?

I have recently received HDR-60 Video Camera Development Kit. I was excited to do some verilog coding for HDMI interface. Design software I have downloaded was iCEcube2 2017.08 (Licence will provided ...
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115 views

Lattice Machxo3 FPGA configuration using I2C

I have a Lattice Machxo3 FPGA based design / board and currently I am configuring the FPGA using JTAG. As per the datasheet I2C also can used as the FPGA configuration interface. Is it possible to use ...
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93 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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160 views

Lattice LCMXO2-256HC-4SG32C CHECK_SECURITY_PROTECT_KEY error

Trying to progamm LCMXO2-256HC-4SG32C with this ebay progammer. The programmer works fine with LCMX02-1200HC-4TG144C, but with LCMXO2-256HC-4SG32C it gives me the following output: ...
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103 views

Should FPGA interface an IC using more than one IO bank?

I would like to interface a FPGA with a fairly fast IC. My FPGA is MachXO2-7000HC while the IC in question is FTDI's FT601, which is a USB 3.0 to FIFO bridge. The FT601 has quite a few control/data ...
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1answer
147 views

Creating a Counter in Verilog for Flashing LED on Lattice Starter Kit

I have a lattic X03LF starter board with 6900C FGPA. There are eight LED available on this board and a push button. The goal of my code is to design a 8 bit counter that increments whenever a button ...
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127 views

Problem with adding two counters in series on an FPGA

I am using Verilog in Lattice Diamond IDE with a lattice MachXO2 7000HE breakout board. I built a basic counter with a limit input which generates a variable period clock output. It works fine on its ...
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I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal. I would have understood a Set signal. I would have understood a ...
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212 views

Is it possible to generate internal reset pulse in verilog with machxo3lf fpga?

I have a board without Reset input for my design. But I need to reset at fpga startup. Is there a verilog solution to generate this pulse ?
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588 views

How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...
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1answer
175 views

How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3

I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their ...
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62 views

What is the exact definition of propagation constant of a two-port network?

Wikipedia says that the propagation constant of a lattice network is $$\gamma = \ln\left[\frac{\sqrt{\frac{Z_a}{Z_b}}+1}{\sqrt{\frac{Z_a}{Z_b}}-1}\right]$$ Wikipedia also says that "In the context ...
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2answers
227 views

digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge

I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this ...
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How the slew-rate and drive strength affect the output signal of the FPGA?

Can someone describe the difference between the drive strength and the slew-rate preferences in Lattice FPGA?
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105 views

Packing register pairs on Lattice FPGA slice. How?

On my design (Lattice MachXO2 FPGA) I use a lot of registers set by a signal and reset by another (both synchronous with the clock), like this: ...
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321 views

What is the purpose of this Verilog code for implementing 3-port Block RAM?

LatticeMico32 (LM32) is a royalty-free CPU that I use to study how a pipelined in-order CPU may be implemented. One particular troublesome point I have trouble with is how the register file is ...
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1answer
404 views

Lattice iCEcube2, error synplify_pro 321

I just made a fresh install of iCEcube2, first time i'm using it, and whatever design files I use I've got this error when I try to synthetize : ...
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362 views

Error on Lattice Diamond: “core0 incorrect response (Write: 512 != Read:0) … Problem cause is sample clock too slow or not continuous”.

Question for persons experienced on Lattice Diamond, I'm trying to test a previously developed project on Lattice Diamond. The project initially shouldn't have any problems because it was implemented ...
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1answer
258 views

VHDL tutorial for the Lattice ECP5 Versa Development Board [closed]

I have got this Lattice ECP5 Versa Development Board and I am going to be working with it in the future. Right now I am looking for some good VHDL tutorial which will help me Play with the board and ...
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1answer
704 views

Fairly Simple VHDL SPI bus working in simulation but not on FPGA (Lattice MACHOX3LF-6900C FPGA and Lattice Diamond software)

I am new to VHDL and FPGA programming, and although I know of a fair number of problems that could exist between simulation and synthesis, this particular issue had me stumped. My design is fairly ...
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291 views

How does lattice determine signal type?

I am using Lattice Diamond, I wonder how does lattice recognize the type of signal when synthesizing vhdl/verilog. I have a module such : ...
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45 views

How to test synthesizability and time characteristics of an isolated Verilog module?

How to test synthesizability and time characteristics of an isolated Verilog module which can have its own interface much wider than pins number of choosen FPGA?
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321 views

Cannot get Active-HDL to run in Lattice Diamond

I have the latest version of Lattice Diamond installed and a freshly generated Free license. However, when I try to run a simulation, I get an a window that says "FLEXlm not initialized.". After ...
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1answer
409 views

passing Synplify options from Lattice Diamond TCL code

I would like to pass, from the TCL file that is commanding the Diamond tool of Lattice, some options to the Synplify synthesis tool. E.g.: It is possible to set a value of the VHDL generic at ...
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1answer
669 views

Lattice MachXO3L: MIPI CSI2 bridge

I would like to design a MIPI CSI2 bridge with a MachXO3L. I leverage the LVDS25 input/output of this FPGA family with the adequate resistors for HS traffic. (I think) I don't care about LP as the ...
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2answers
1k views

Correctly initialize a shift register (Verilog)

I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.) The ...
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1answer
908 views

Example code to read device ID of MachXo2 with FTDI -JTAG

In my project I am working on MachX02 programming with FTDI master using JTAG functionality. I am trying to read device ID of MachX02, but not working, here is my sample code to read device ID of ...
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1k views

Pin Assignment in ispLEVER Classic

I have an ispGAL22LV10C that I'm trying to program. I wrote and synthesized the VHDL in ispLEVER Classic, but I cannot seem to figure out how to create pin assignments. Documentation on this is kind ...
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241 views

iCEstick40HX1K device is malfunctioned, and windows does not recognize it when programming bitstream on Diamond Programmer 3.5

I'd designed a " SPI Flash Erase, program,verify with iCEstick 40HX1K. I programmed on Diamond Programmer 3.5. it had done successfully only one time.then i want to reprogram, but when I connect it to ...
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1answer
234 views

How to programm a Lattice board?

I wrote a few lines in VHDL and I declared pins into a lpf file for my Lattice MarchX03 board. But now I want to flash the board and honestly the documentation is very unclear. So I got Diamond ...
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1answer
1k views

Lattice FPGA - declare pin

I am learning VHDL and I am using the Lattice boards. I want to know how to declare a GPIO. I found the following block of code in the diamond software folder example. It is ".lpf" file and I guess it ...
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2answers
549 views

Putting Linux on a Lattice ECP3 FPGA

On my Xilinx Zedboard, I booted Linux from an SD card and then ran a Linux application (written in C) from the SD card. This application created a server using sockets that would return whatever is ...
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1answer
2k views

In a Lattice MachXO2, how can I use the EFB SPI slave and configuration SSPI (multiplexing)?

I am using a Lattice MachXO2 FPGA eval board and Lattice Diamond 3.4.0.80 on Linux. I want to use the configuration SSPI to update the FPGA configuration. During user mode, I want to use the same ...
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1answer
1k views

Lattice Diamond 3.4. template/schematic generation

I'm following this tutorial: Lattice Diamond Hierarchical Design Test Bench Tutorial However i am using Lattice Diamond ver. 3.4.1, and some details are different. The Problem i am facing is with the ...
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1answer
625 views

Delete or ignore I/O from a schematic block in Lattice?

I am programming with a Lattice ispMACH 4000ZE Pico DevKit and with the software ispLEVER Classic Project Navigator. I want to use in my schematic file the OSCTIMER block from the Lattice library, but ...
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2answers
1k views

windows can't recognize my lattice machxo2 board

I purchased a MACHXO2 - 1200ze evaluation board a few days ago. I started with designing and programming simple projects as blinking leds, which worked perfectly. After that at the same day I tried ...
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2answers
860 views

Create breakout for small FPGA in BGA package

I'm going to buy a MachXO3 FPGA by Lattice, famous for the low cost, in order to create a bridge between an HDMI input and a MIPI DSI output for low cost/high res display. Lattice lets you buy only ...
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543 views

Why would my Lattice IceStick stop working when configuring the PLL?

I'm using a Lattice FGPA IceStick with the newer IceCube2 programming environment and the Diamond 3.0 programming tool. The 'iCEstick LED Rotation' example runs OK but when I attempt to enable the PLL,...
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1answer
380 views

How to read Map-Report in FPGA Synthesis Tools

I have this Map-Report piece product by Lattice Diamond: ...
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2answers
331 views

Encrypting a JDEC file in Lattice MachxO2

I am working on lattice MachxO2 FPGA. Our customer is asking to to encrypt the JDEC file (the bit file). How do I do this? There is sample Unencrypted JDEC file and some information given here ...
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913 views

Trouble with VGA Controller on CPLD

What I am attempting to do is create a VGA controller from a Lattice MachXO CPLD in Verilog. The Problem I am attempting to display the color red with a resolution of 640x480 @ 60Hz using a 25.175 ...
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1answer
200 views

Integrating IP core to a project

I'm working on a Lattice board and I'm want to to use IP cores for my project. I have a license to a third party IP core but I have no idea how to integrate the IP to my project. My research shows me ...
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1answer
1k views

Connecting RS232 output of Lattice XP2 Brevia Kit to PC USB (virtual COM port over USB) using a FTDI RS232RL based board

I have a Lattice Brevia XP2 Kit (the older one that came out in 2010/2011, and the not the newer version 2). The only PC connectivity it has is through serial (rs232). I have anetbook that does not ...
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1answer
292 views

Lattice HDR-60 board download problem

I'm working on Lattice HDR-60 board which is pre loaded with a default program. When I try to load a program it disappears on restart. Recently I downloaded a design which downloaded successfully but ...
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2answers
1k views

Arduino to CPLD to toggle an LEDs using I2C

I have a a CPLD (Lattice MachXO2) that echos a signal from an Arduino to turn on an LED. Arduino: ...