Questions tagged [lattice]

Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.

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Lattice FPGA problems with built-in DELAY module

I'm trying to delay an input data coming from ADC component in DDR to my FPGA, afterwards output it in the clock rising edge. The ADC Im using: ADS5463: Im using Lattice ECP3 FPGA, based on the fpga ...
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54 views

How to Output DDR data to 1 register

I have an Input which provides DDR data, I need to capture it and output it from the FPGA in one register (12bit). How can I do it? What I did for now is to capture the input data with always block ...
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ADC output is stable, fpga interface

Im trying to build ADC interface with FPGA. Im using ADS5463: http://www.ti.com/lit/ds/symlink/ads5463.pdf time diagram: after getting some help here I wrote a simple verilog code that just waits ...
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Questions about Interfacing ADC: ADS5463 with FPGA

Im beginner FPGA Designer. I need to interface the ADC component: ADS5463. datasheet: http://www.ti.com/lit/ds/symlink/ads5463.pdf with a FPGA (lattice ecp3). I need suggestions how to start ...
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How can I make Lattice Symplify Pro infer RAM correctly from VHDL code?

I have a design on an iCE40 FPGA, I use iCEcube2 to compile the VHDL code and in my design I try to infer two small RAM buffers. The type of the buffers is as follow : ...
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39 views

IDDRX2 Lattice FPGA module

I saw in a code usage of the module IDDRX2D1, this module is inside the FPGA Lattice ECP3, I found from its Libraries Ref Guide this information: someone can help me about what is it and for what is ...
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36 views

The port [clk_ch1_p_i] doesn't exist in the design

I am working on verilog project in lattice diamond. I synthesize and compile correctly my code. I write my lpf (constraints file) to place pins,but when i try to visualize the pin/port assignment in ...
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Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
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114 views

Implementing 4-bit counter on GAL 16V8

I want to use a GAL 16V8 to implement a 4-bit counter using Verilog. I'm using Lattice's ispLEVER software. So far I have had no issues using Verilog to implement combinational logic. However, I ...
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110 views

Lattice MachXO2 reset

After reading about GSR/PUR facilities in Lattice FPGAs, I'm still a bit puzzled about how to actually get the proper GSR/PUR-based reset functionality on an actual physical FPGA chip. In the How to ...
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36 views

Lattice — Should I prefer IPX/PMI over Verilog arithmetic builtins?

Like any FPGA vendor, Lattice provides a number of IP modules for users to put in their designs. I tend to use them whenever possible, but sometimes I doubt if they have any substantial benefit over ...
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38 views

Trouble with double-buffer structure — MachXO2 using FIFO_DC from IPExpress

In reference to this recent question: I'm seeing a problem with that scheme (the second figure, using the FIFOs as "circular buffers", or shift-registers so that old samples are extracted as discarded ...
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86 views

Diamond: Warning: logical net has no load

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: ...
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2answers
104 views

Verilog — how to assign mux/selector output to module's output

Verilog beginner here. Working with Lattice Diamond for a design using the MachXO2. For context: I recently got this answer to a related question. See the second image in the answer. I want to ...
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49 views

PISO buffer for the MachXO2

I'm trying to design a "double-buffer" structure similar to that used in UARTs (for receiving). In my case, it is for samples from an ADC. I shift them in, and at some point my logic detects a ...
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155 views

Programming (flashing) MachXO2 chips through JTAG

I'm trying the MachXO2 7000HE Breakout Board --- I could make a simple demo work (following this nice Youtube video). Since I want to include one of these chips in my next design, I want to learn ...
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Getting started with TinyFPGA board (Lattice Semiconductor MACHXO2 chip)

I'm a bit of a newbie with FPGAs. Trying to run the project from the "Getting Started" section of the Lattice Diamond manual. These are the source files: count.v: ...
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Generate XCF file for Lattice Diamond from command line

I am writing a Makefile for Lattice Diamond and have come as far as to cover all steps from synthesis to bitfile. To program the FPGA (a MachXO3L in my case) I looked for a command line tool, and ...
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154 views

Lattice Diamond Port 'direction' is unconnected

I am following the tutorial to turn on the LED on the embedded vision development kit found in: C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v ...
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What is the design tool for Lattice HDR-60 Video Camera Development Kit?

I have recently received HDR-60 Video Camera Development Kit. I was excited to do some verilog coding for HDMI interface. Design software I have downloaded was iCEcube2 2017.08 (Licence will provided ...
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218 views

Lattice Machxo3 FPGA configuration using I2C

I have a Lattice Machxo3 FPGA based design / board and currently I am configuring the FPGA using JTAG. As per the datasheet I2C also can used as the FPGA configuration interface. Is it possible to use ...
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153 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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240 views

Lattice LCMXO2-256HC-4SG32C CHECK_SECURITY_PROTECT_KEY error

Trying to progamm LCMXO2-256HC-4SG32C with this ebay progammer. The programmer works fine with LCMX02-1200HC-4TG144C, but with LCMXO2-256HC-4SG32C it gives me the following output: ...
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120 views

Should FPGA interface an IC using more than one IO bank?

I would like to interface a FPGA with a fairly fast IC. My FPGA is MachXO2-7000HC while the IC in question is FTDI's FT601, which is a USB 3.0 to FIFO bridge. The FT601 has quite a few control/data ...
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267 views

Creating a Counter in Verilog for Flashing LED on Lattice Starter Kit

I have a lattic X03LF starter board with 6900C FGPA. There are eight LED available on this board and a push button. The goal of my code is to design a 8 bit counter that increments whenever a button ...
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142 views

Problem with adding two counters in series on an FPGA

I am using Verilog in Lattice Diamond IDE with a lattice MachXO2 7000HE breakout board. I built a basic counter with a limit input which generates a variable period clock output. It works fine on its ...
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I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal. I would have understood a Set signal. I would have understood a ...
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375 views

Is it possible to generate internal reset pulse in verilog with machxo3lf fpga?

I have a board without Reset input for my design. But I need to reset at fpga startup. Is there a verilog solution to generate this pulse ?
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950 views

How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...
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1answer
250 views

How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3

I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their ...
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112 views

What is the exact definition of propagation constant of a two-port network?

Wikipedia says that the propagation constant of a lattice network is $$\gamma = \ln\left[\frac{\sqrt{\frac{Z_a}{Z_b}}+1}{\sqrt{\frac{Z_a}{Z_b}}-1}\right]$$ Wikipedia also says that "In the context ...
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2answers
249 views

digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge

I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this ...
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1answer
2k views

How the slew-rate and drive strength affect the output signal of the FPGA?

Can someone describe the difference between the drive strength and the slew-rate preferences in Lattice FPGA?
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135 views

Packing register pairs on Lattice FPGA slice. How?

On my design (Lattice MachXO2 FPGA) I use a lot of registers set by a signal and reset by another (both synchronous with the clock), like this: ...
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373 views

What is the purpose of this Verilog code for implementing 3-port Block RAM?

LatticeMico32 (LM32) is a royalty-free CPU that I use to study how a pipelined in-order CPU may be implemented. One particular troublesome point I have trouble with is how the register file is ...
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2answers
503 views

Lattice iCEcube2, error synplify_pro 321

I just made a fresh install of iCEcube2, first time i'm using it, and whatever design files I use I've got this error when I try to synthetize : ...
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426 views

Error on Lattice Diamond: “core0 incorrect response (Write: 512 != Read:0) … Problem cause is sample clock too slow or not continuous”.

Question for persons experienced on Lattice Diamond, I'm trying to test a previously developed project on Lattice Diamond. The project initially shouldn't have any problems because it was implemented ...
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271 views

VHDL tutorial for the Lattice ECP5 Versa Development Board [closed]

I have got this Lattice ECP5 Versa Development Board and I am going to be working with it in the future. Right now I am looking for some good VHDL tutorial which will help me Play with the board and ...
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1answer
775 views

Fairly Simple VHDL SPI bus working in simulation but not on FPGA (Lattice MACHOX3LF-6900C FPGA and Lattice Diamond software)

I am new to VHDL and FPGA programming, and although I know of a fair number of problems that could exist between simulation and synthesis, this particular issue had me stumped. My design is fairly ...
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1answer
386 views

How does lattice determine signal type?

I am using Lattice Diamond, I wonder how does lattice recognize the type of signal when synthesizing vhdl/verilog. I have a module such : ...
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46 views

How to test synthesizability and time characteristics of an isolated Verilog module?

How to test synthesizability and time characteristics of an isolated Verilog module which can have its own interface much wider than pins number of choosen FPGA?
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1answer
355 views

Cannot get Active-HDL to run in Lattice Diamond

I have the latest version of Lattice Diamond installed and a freshly generated Free license. However, when I try to run a simulation, I get an a window that says "FLEXlm not initialized.". After ...
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1answer
452 views

passing Synplify options from Lattice Diamond TCL code

I would like to pass, from the TCL file that is commanding the Diamond tool of Lattice, some options to the Synplify synthesis tool. E.g.: It is possible to set a value of the VHDL generic at ...
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1answer
696 views

Lattice MachXO3L: MIPI CSI2 bridge

I would like to design a MIPI CSI2 bridge with a MachXO3L. I leverage the LVDS25 input/output of this FPGA family with the adequate resistors for HS traffic. (I think) I don't care about LP as the ...
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2answers
1k views

Correctly initialize a shift register (Verilog)

I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.) The ...
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1answer
995 views

Example code to read device ID of MachXo2 with FTDI -JTAG

In my project I am working on MachX02 programming with FTDI master using JTAG functionality. I am trying to read device ID of MachX02, but not working, here is my sample code to read device ID of ...
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Pin Assignment in ispLEVER Classic

I have an ispGAL22LV10C that I'm trying to program. I wrote and synthesized the VHDL in ispLEVER Classic, but I cannot seem to figure out how to create pin assignments. Documentation on this is kind ...
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249 views

iCEstick40HX1K device is malfunctioned, and windows does not recognize it when programming bitstream on Diamond Programmer 3.5

I'd designed a " SPI Flash Erase, program,verify with iCEstick 40HX1K. I programmed on Diamond Programmer 3.5. it had done successfully only one time.then i want to reprogram, but when I connect it to ...
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1answer
254 views

How to programm a Lattice board?

I wrote a few lines in VHDL and I declared pins into a lpf file for my Lattice MarchX03 board. But now I want to flash the board and honestly the documentation is very unclear. So I got Diamond ...
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1answer
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Lattice FPGA - declare pin

I am learning VHDL and I am using the Lattice boards. I want to know how to declare a GPIO. I found the following block of code in the diamond software folder example. It is ".lpf" file and I guess it ...