Questions tagged [lattice]

Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.

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Generate XCF file for Lattice Diamond from command line

I am writing a Makefile for Lattice Diamond and have come as far as to cover all steps from synthesis to bitfile. To program the FPGA (a MachXO3L in my case) I looked for a command line tool, and ...
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There is a way to write into FIFO on both clock edges?

Im using Lattice ECP3 FPGA, didnt found any information about it on the internet. I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface: This ...
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ADC output is stable, fpga interface

Im trying to build ADC interface with FPGA. Im using ADS5463: http://www.ti.com/lit/ds/symlink/ads5463.pdf time diagram: after getting some help here I wrote a simple verilog code that just waits ...
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The port [clk_ch1_p_i] doesn't exist in the design

I am working on verilog project in lattice diamond. I synthesize and compile correctly my code. I write my lpf (constraints file) to place pins,but when i try to visualize the pin/port assignment in ...
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Lattice Diamond Port 'direction' is unconnected

I am following the tutorial to turn on the LED on the embedded vision development kit found in: C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v ...
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What is the exact definition of propagation constant of a two-port network?

Wikipedia says that the propagation constant of a lattice network is $$\gamma = \ln\left[\frac{\sqrt{\frac{Z_a}{Z_b}}+1}{\sqrt{\frac{Z_a}{Z_b}}-1}\right]$$ Wikipedia also says that "In the context ...
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Error on Lattice Diamond: “core0 incorrect response (Write: 512 != Read:0) … Problem cause is sample clock too slow or not continuous”.

Question for persons experienced on Lattice Diamond, I'm trying to test a previously developed project on Lattice Diamond. The project initially shouldn't have any problems because it was implemented ...
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How does lattice determine signal type?

I am using Lattice Diamond, I wonder how does lattice recognize the type of signal when synthesizing vhdl/verilog. I have a module such : ...
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How to test synthesizability and time characteristics of an isolated Verilog module?

How to test synthesizability and time characteristics of an isolated Verilog module which can have its own interface much wider than pins number of choosen FPGA?