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Questions tagged [layout]

Layout is the process of designing a PCB including placement of parts and routing of traces.

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analog and digital ground connection point selection

I've read some articles that say the connection point of digital ground and analog ground should be at the power supply output port. However, when there are two or more power supplies which are ...
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47 views

AC power tracks, PCB design guides

I was wondering about this board Im reviewing. Theres a switching power supply module in this board (red rectangle). switching power supply used: https://pt.aliexpress.com/item/220-v-a-3-3-v-5-9-12-...
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39 views

SMT electret microhone PCB mounting

I see a lot of SMT microphones in vendors' lineups. All of them orient normal to the PCB--either up or down. I'm working on a design where the microphone has to point parallel to the PCB. On the ...
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77 views

How important is it to track from centre of pad in PCB routing?

When reading through the review comments of a PCB, there was one which raised some questions for me: "Aim to route tracks out of pad centres and in line with the pad, not exiting at an angle." I ...
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62 views

High current on PCB to through hole connector

If I have a though-hole connector with 3.5mm pin spacing and the manufacture rates it for 14 amps per contact, how am I supposed to safely carry anywhere near that current over the PCB? Specifically, ...
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28 views

Marchand balun layout

For this marchand balun schematics in ADS, how to instruct the ADS layout generator to use coil shape (for area saving in IC) ? Besides, anyone have any experience with planar layout of marchand ...
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1answer
40 views

how will a connector affect a transmission line?

I am laying out an RS485 driver and read a few design guides which recommend a 120 Ohm termination resistor. This makes sense since the characteristic impedance of twisted pair cables is in the 100 ...
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3answers
100 views

RF loop Antenna design layout

I am designing a bioimplantable circuit for a biomedical implant. The goal is to have an extremely tiny device in a flexible substrate (Dupont Pyralux) that must be powered wirelessly. My problem ...
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27 views

Highlighting feature of any net becomes latched on in Altium 17.1 PcbDocs

When routing a net, highlighting of startpoint/endpoints is great, but when a net I am no longer working on remains highlighted, it becomes an annoyance. This is happening multiple times a day and the ...
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1answer
63 views

Differential pairs; length matching between pairs

I'm currently busy routing a high speed design containing MIPI signals @ 2,5Gbit / lane to a connector on an 8 layer board. As MIPI also contains a clock pair, it is advisable to match the length ...
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40 views

7030 SMD LED pad configuration

I have not done a lot of work with SMD LEDs and have a question about the pad layout. I have done quite a bit of research and haven't found much helpful info yet. I am working with 7030 SMD LEDs ...
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1answer
32 views

Unlock movement/edit of internal polygon layers in altium 19?

I changed an internal plane to a signal layer and now I want to be able to move objects in this layers like polygon, however I seem to be unable to do so. How can I unlock polygon move/edit in this ...
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45 views

EAGLE Names not showing up on board after footprint update

I added the >NAME attribute to the footprint of a device and now the names are not shown on the board. I have already tried to update the library (with library --> update all) and also the replace ...
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2answers
126 views

PCB input smoothing capacitor layout

I got some 0.1uF ceramic capacitor in front of my mcu IO pins to smooth the inputs values/spikes I was wondering if this placement is bad or not because their position is "over" the input so maybe (...
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1answer
41 views

Compare (Diff) ODB++ Files

A few years ago I was making layout changes to a PCB and wanted to be 100% sure that one particular interface did not change at all. My layout contractor generated an ODB++ compare file (I would also ...
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1answer
38 views

how to confirm that PCB Ethernet layout does not affect perfornace

short version: - How to test if ethernet traces on PCB causing any distortions to the signal? - Is it possible to generate ethernet signals from a windows computer and measure them with an ...
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1answer
90 views

ESP-WROOM-32 layout USB-UART

I want my layout will include female headers to connect CP2102 MICRO USB to UART TTL Module 6Pin so I could just 'stick' it to my PCB while uploading the code. The 5V for the ESP will be supply from ...
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1answer
69 views

Ground planes disposition in Ethernet connection

I am designing a board that will have sensible analog signals and a processor communicating with the external word via Ethernet and I want to avoid that common mode currents couple into my analog ...
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31 views

Cheap RF 433.92MHz design, PCB track antenna [duplicate]

I'm doing a RF remote control project using a PCB with microcontroller and with simple onboard antenna layout as transmitter and a 433.92MHz receiver RWS-371F-6 model. Here is the datasheet of the ...
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1answer
45 views

On-PCB SPI Distance Considerations

I've been reading about ringing and overshooting and all sorts of things, but all without getting a real "feeling" for how likely these things are to affect my circuit. I've got a chip generating an ...
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1answer
60 views

Can I bridge output IO's from an FPGA that is driving a clock source to drive longer tracks?

Scenario I have a motherboard and a daughterboard that couple through two headers. The motherboard has a 16x16 array of ultrasound speakers each with their own drivers, that works. I drive them ...
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68 views

UnRouted Net Constraint in Altium after Via Stitching

I am just wrapping up my Design of one of my project in Altium 17. I was done with adding ...
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2answers
235 views

12V to 5V buck converter 3A PCB

I am creating my first 12V to 5V buck converter with the TI TPS56339. I've heard that the PCB layout is critical and before I send the PCB to production I wanted to get it reviewd. I tried my best to ...
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1answer
101 views

Use of internal PCB ground plane as ESD baseplate/EMC reference plane of product in plastic enclosure

I am designing an electronic product which will be housed in a plastic (non-conductive) enclosure. There are a number of, mostly shielded, I/O cables (Copper 10/100/1000Mb/s Ethernet, USB 2.0, RS232, ...
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132 views

Connecting the Chassis Ground and Signal Ground in my PCB

I have been reading alot of questions on this site to clear my understanding on Chassis, Signal Ground, ...
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3answers
407 views

Modifying land patterns generated with IPC-7351B wizard

I generated a 4x4mm 0.45mm pitch QFN28 according to the Atmega328P datasheet: However, the pads on the corners (1+28, 21+22, 14+15, 7+8) are too close to each other, less than 0.2mm apart (when ...
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2answers
146 views

Using polygon pours for small signals in PCB design

I'm trying to improve my PCB routing skills. When I started out a few years back, I just layed out the components and ran tracks with a fixed width between them. I didn't even know about polygon pours....
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75 views

What happens if two N-wells touch each other?

When designing the layout of a CMOS inverter, we need to use an NWELL to build the PMOS. Following scalable rules, when desining the masks I have to be sure that if I want to build two NWELLS using ...
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1answer
51 views

PE pin position

I have one question. I'm designing a PCB which is a sort of smart switch (so, basically, you have one 230V input and one 230V output, where the output and the input share two wires, N and PE, and the ...
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2answers
132 views

How to separate ground efficiently in a thyristor circuit controlled by sensitive microcontroller

I've been trying to design capacitive discharge ignition circuits using a microcontroller ARM (Texas and ST) without success. Each circuit using them presents intereference problems during spark ...
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0answers
39 views

How to simulate a piezoresistive pressure sensing MEMs layout without COMSOL?

I have a masks layout of a Piezoresistive MEMs pressure device that I've designed in LEdit(Tanner Tools Eda). The device consists of 4 piezoresistors bonded onto a thin diaphragm which deforms ...
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2answers
129 views

IC layouts - Transistors (Body)

I'm trying to get into IC layouts... Why do I see some IC layouts with or without the body terminal on the transistors. Do MOSFet transistors need a body terminal in an integrated circuit? Or should ...
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1answer
58 views

SATA 2.0 to M.2 (NGFF) design

I am designing a PCB with a A20 (allwinner) SoC. This SoC has a SATA 2.0 host (RXP RXM TXP TXM) that I have to route to a M.2 "M" key connector. I found only one source for pin out, but I can't find ...
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62 views

Creating a balanced dipole from two monopole chip antennas for use on small PCBs

I'm trying to use a monopole chip antenna on a PCB much smaller than the one recommended in the datasheet. I am wondering if I can get away with a much smaller board by using two monopole antennas ...
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2answers
185 views

Bypass caps under BGA: Should I isolate vias from planes?

I'm placing bypass capacitors underneath a BGA package. In some cases the caps cannot land directly on the vias-in-pad ("VIP"), so I'll need short traces from the VIPs to the caps: In this example ...
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3answers
390 views

Cost optimization - PCB Area vs. Double-sided load

If one has an opportunity to choose between laying out a PCB as either a single-side load (components all on one side, so it goes through reflow only once and requires only one stencil) or a double-...
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3answers
165 views

PCB trace width can't meet the rated current

The rated current for VCC5_AC from AC adaptor is 2A. According to the calculation on http://circuitcalculator.com, the trace width for 2A should be 30.3mil. However, as indicated above, the width of ...
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1answer
185 views

Shunt resistors and PCB layout

I have several questions about the current sensing through a resistance. The resistances are 2-SMD package and I will use the 4-wire kelvin method for the layout.(see image) Specifically, there are ...
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1answer
63 views

Split Ground plane with motor drivers

This is a PCB with few stepper drivers. I have a question about the ground plane. I have this idea to split the ground plane for each driver, so, I force the return path to pass through the capacitor....
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1answer
186 views

Machine learning for floorplanning

I have an educational assignment to make an floor-planning tool. Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
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1answer
244 views

Grounding and Signal Integrity of my PCB Layout (ADC, SMPS, SD card, USB)

I am currently designing a battery monitoring system for an 8 cell lithium battery pack. I originally made the device using a STM32 dev board and breadboard, with an SD card to log data. The system ...
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2answers
86 views

Do cascoded MOSFETs need to be in their own wells in order to properly connect bulk to source?

I am learning to design CMOS layouts. When creating the layout for something like a cascoded current mirror, are individual wells needed to properly connect the bulk to source? For example, for the ...
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1answer
70 views

Is it acceptable to split one wide wire into two narrower wires in PCB layout?

I have an issue about connecting power wire to the IC. The power wire (50mil) is wide than the pin width of destination IC, so I want to split the wide wire into two narrower ones(20mil) which match ...
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1answer
187 views

Connection of ESD return path the System GND

In my current design I have one RJ45, one RS232 and two RS485 ports. I have TVS diodes CDSOT23-SM712 for serial channels and ESD7104MUTAG for Ethernet port. Now I have connected the ESD GND of the TVS ...
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4answers
251 views

Full bridge driver capacitor ringing problem

This is my first time designing a full bridge driver. I am experiencing problems with ringing on the output. I have made a pcb for it. This is a picture of the top side of the board. Backside Input ...
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1answer
91 views

RF layout bend over Component

We lay out the RF trace for below model. GSM 900MHz RF trace maintain at 50Ω impedance. As I know, the RF trace needs to be as short as possible for better signal. Do we need to bend RF trace ...
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1answer
37 views

Cadence Virtuoso - Cell Parameterized [closed]

Please see attached. I am unable to view the Poly, Metal, Cont layers for the PMOS & NMOS instances. Need a bit of assitance on how to fix this issue
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361 views

USB 3.0 Length matching in PCB Layout

I'm doing PCB layout for a USB 3.0 connection and I'm curious about if there's a length match requirement between the unidirectional super speed pairs and the bidirectional high speed pair. This isn'...
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1answer
137 views

PCB layout rules

What are the design rules that should be applied when designing a PCB layout ? I am currently using Kicad, because it is free and it is simple to use. I made a layout for a L200 power supply. I wand ...
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1answer
2k views

What breadboard simulation software is this?

I'm not familiar with what software is available and cannot recognize the origin of this diagram. Does anyone know what software this is? I'm only guessing that it can perform simulation; it may just ...