Questions tagged [layout]

Layout is the process of designing a PCB including placement of parts and routing of traces.

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PCB Design Review Request

I am designing a MIDI controller board. It's my first board ever and I was just wondering if people could check a part of my design for potential problems and shortcomings. Each section is controlled ...
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1 answer
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Breadboard Layout Validation

I have a breadboard with a bridge rectifier circuit that I am hoping to have someone validate for me. The circuit with breadboard pins is: And a picture of my breadboard is: Thank you!
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10 votes
6 answers
2k views

How does current flow in multiple vias?

How does current travel in multiple vias from one layer to other? For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of ...
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The parasitic parameters on layout

I would like to know why using polygon pour traces could reduce the parasitic element. the parasitic element includes L, R. any theory could support this one?
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2 Layer PCBA routing strategy for high current design

I have a very simple pcba design. The only thing of value is that the traces will carry up to 30A of current. I have already decided to increase copper thickness to 2 oz for improved current capacity. ...
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3 votes
1 answer
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Two layer PCB vs. four layer PCB for simple design with 30A current

I have a design which is literally just 2 connectors (input and output), a relay and a diode. Basically using the relay to connect a charger to a battery. The board size is predetermined and I can't ...
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Trace to Pin connection

I am having the issue of connecting my voltage regulator to the trace. The trace must be thick but the pins are too small. What is the best solution? I am using proteus. Does making a solder Paste ...
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1 vote
1 answer
51 views

Layout for MOSFETs (copper area for source vs drain)

I have a schematic. Here is a section of it: The FETS are being driven by the chip to behave as ideal diodes. Plus two FETs in series to block current path when chip is in shut down stage. I've seen ...
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2 answers
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How do I place a component in the center of the board? Altium

I'm attempting to align some components, such as an OLED display and a push-button, to the pcb board's centerline. The board was imported as STEP from Solidworks and has a non-uniform format (not a ...
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What is the minima rule for a Metal 1 layer for the 2 contacts on a poly shown on the figure? I'm using 0.18um library

Contact on a poly using 0.06 spacing for the metal 1 layer
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3 votes
1 answer
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Why is this recommended in PCB layout: 2 leads between pads

Why is the connection recommended as in the top picture?
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2 votes
1 answer
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Xilinx FPGA decoupling cap layout (traces and vias)

I have the decoupling capacitors located close to sparatan 7 (<2000 mil). I'm trying to route these and connect it to the BGA pin. According to xilinx UG393, I shouldn't use same vias. PCB layout ...
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Having problems going from KiCAD -> Panelizer -> FlatCAM, outline not recognized

I'm a total newbie to FlatCAM but not to PCBs. I'm trying to use KiCAD and send the files through the common Panelizer (ThisIsNotRocketScience) software, I want to do two layer boards on my 3018 (...
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How to make an L shaped through hole pad in Altium

I need to make a footprint for a USB type C connector in Altium, and two of the shield pads are shaped like an L. Technically this is a component for Altium 365, but I'm not sure that will make a ...
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4 votes
2 answers
1k views

Find the centre point of a PCB board?

Is there a smarter way to find the centre of a board in Altium? I just used linear dimensions to find the midpoints and the intersections.
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Altium Harness Conflict

Has Altium fixed the issue where Harnesses override the net names and cause a 'nets with multiple names' warning? Has anybody found a way past without net ties? I can't afford net ties at my speeds ...
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Keeping shapes/ polygons from going over same net trace in Cadence OrCAD?

I have an interesting situation where I have a current sense line that needs to be differential to ground. I'm trying to add copper pours to the top and bottom layers, however I can't pour over these ...
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How to wire USB-C connector?

I am trying to add USB-C to an ESP32 module. I am using a [CP2102][1] This is the USB-C connector I was planning to use, simply because JLCPCB has tons of them and ...
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1 vote
1 answer
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How are courtyards on PCB layouts defined?

Let's say I have two premade PCB footprints with courtyards already defined (either from some tool like a footprint generator, from a vendor, etc). Are courtyards usually defined that the courtyards ...
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How to connect wires from Orange Pi to DIP8 board without a numbered layout?

I read the documentation, it doesn't tell how to do it. I have an EEPROM chip containing the BIOS on my laptop's motherboard - an MX25L06E if you need the name. I have an Orange Pi Lite board, and I ...
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2 votes
1 answer
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Multiple SMPS placement layout advice

I'm planning a mixed signal board with the following power rails: +3.3V +5V -5V +12V -12V +Adjustable voltage (2-10V) -Adjustable voltage (2-10V) Each of the rails are supplied from an external +...
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ESP32 Pad 39 - Where do I add vias?

I am building my first PCB ever with an ESP32. I want the PCB to be built by JLCPCB (or similar) and I am not sure what to do with the Pad39 I read these opinions: Do not add vias in pad, and if you ...
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MCP1612 - circuit debugging

I am designing an adjustable voltage regulator using MCP1612 and DAC signal from a microcontroller. I designed the following schematic and PCB (I tried to cut out only the relevant part) The resistor ...
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3 answers
100 views

Circuit Frequency Check - Mentor PCB Layout

I have a problem - this is my created layout for the HMC414 amplifier. I'm wondering, if looking at this layout you can see that this circuit is at 50 Hz or at 2.4 GHz? Apparently, you can tell just ...
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2 votes
1 answer
109 views

PCB layout and stackup for space application

I've been tasked with the design of a PCB for a CubeSat project in my univesity and I'm trying to figure out exactly how the layout and stackup of my board should be done. The board I have to design ...
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1 vote
0 answers
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PCB Layout Mentor Graphics - basic question about transmission lines and components

I am currently doing a PCB Layout for an amplifier and would like to know if there is any way to add a transmission line to the Layout. As far as I noticed there is no corresponding symbol for such a ...
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1 vote
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How can I find the errors on my layout?

I am losing my mind not being able to find the error on my layout. I feel like I am looking for a nail in the mud. I am getting the DRC error : MET1 pin outside met1 But I look and look and LOOK and ...
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1 answer
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What is this error on DRC Cadence layout

I'm doing the layout of an amplifier on Cadence. I've run the DRC error checker and I don't understand what message is this, can someone help me?
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2 votes
2 answers
104 views

OrCAD Footprint in .brd layout different from the .dra file

I made a custom footprint for an 8 pin TSSOP IC, using custom padstacks and creating a new package (no wizard). Each of the four pins on a side are 0.3mm wide and 0.5mm apart (BSC). In the .dra file ...
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1 vote
2 answers
126 views

Are my tracks too close?

I'm working on a digital circuit that I plan to run at ~1MHz. After finishing the PCB I looked back at my work and saw that my tracks are quite close. For a size reference, the tracks are 0.254mm ...
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What is meant by "Kelvin connected to capacitor" in layout terms?

In the MPS5496 PMIC layout guidelines on page 37, they mentioned that you should connect the feedback pins to the buck output capacitor "kelvin connected." What does that mean? Can anyone ...
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3 answers
146 views

Do TVS diodes have polarity?

I am making a USB to UART circuit for ESP32. Why does the LESD5D5.0CT1G datasheet show a polarity marking? Aren't TVS bidirectional? What is the right position for such a diode? My circuit:
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Troubleshooting 3:1 Audio Muxing with Relays. Crosstalk? How to test?

I am switching between 3 audio inputs out to 1 single output. Each input has 4 signals (left and right x positive and negative). I am using 4 DPDT relays (like 8 2:1 muxes). Inputs 2 and 3 switch ...
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What causes my inverter MOSFET to produce this incorrect output?

I'm new to layout. I followed a couple of tutorial on youtube to create an inverter using Magic VLSI, despite following step by step I cannot obtain the same output. I'm using scmos library. Is there ...
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-3 votes
1 answer
96 views

Can color blindness be a disqualifying factor for a person applying for chip layout engineer positions? [closed]

Chip design engineers use software for laying out the wire routing and connections of transistors, to make standard cells or higher logic/functional components, where the distinction between different ...
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1 vote
0 answers
80 views

VCC and GND islands on TOP layer

I was checking Intel Tiger Lake UP3 reference board layout and I noticed that they made core VCC islands on top layer and through vias they connected to a layer that has the bigger/continuous plane of ...
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Flex PCB USB traces layout

I am designing a FPCB and I'm trying to figure out how to make sure the USB traces impedance is 90 Ohms differential. The USB traces from the USB connector to the MCU are about the same lenght, 27.1mm ...
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4 answers
144 views

Any examples of layout where analog ground and digital ground are connected together

I have read about layout where analog circuit ground is separated from digital ground. Though, I have not seen any examples and unable to find on google, can someone help me with some pictures on how ...
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Can I use a split power plane as an alternative to traces?

I am designing a 4 layer PCB with a separate power and ground plane. The electronics is all low speed. The majority of my design is 3.3V low power but the left side requires 24V and the right side has ...
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Is this crystal layout OK?

I have a 2 layer board where I have a crystal running at (16.3840 MHz 18 pF). This crystal is used in a component that has internal caps. Does this layout look OK? Or should change anything? On bottom ...
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1 vote
1 answer
83 views

Is it OK to route under small mosfet transistor?

I have a 2-layer board where I am thinking of routing TX and RX to microcontroller under a small P-channel mosfet. I know some parts can be considered sensitive and one should not route under them. Is ...
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0 votes
2 answers
142 views

SPI questions: EMC and signal integrity

I have an SPI line going at a speed of 12Mbit/s on a 2-layer PCB. This is for a product so it needs to pass EMC tests (as well as just work well). Questions: Should I use series resistors for all the ...
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1 vote
1 answer
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In Altium Designer how do I hide component origin markers and crosshairs in PCB view?

I am trying to clean up the view in PCB, it is cluttered with unnecessary noise, including component origins and these crosshair structures that serve no purpose for me while placing or routing. They ...
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2 votes
1 answer
545 views

Blind Via vs. Buried Via

Are these two things similar? Online guides overlapped the definition between the two. From this website, it states that blind vias are a through-hole that connects inner layers, but it can't be seen ...
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1 vote
0 answers
65 views

DDR4 Routing Consideration

I'm designing a new PC based on Intel Tiger Lake UP3. In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2). each BO has different impedance ...
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1 answer
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Would this circuit work for driving an internal buzzer?

A quick note, I had asked a similar question around driving an external buzzer previously: Driving external piezo buzzers This is a question in regards to driving an internal buzzer, so not a ...
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1 answer
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CMOS layout: Simplification and Euler path

what is the simplest form of Y = (logic)' in order to find a Euler path common for pull-up and pull-down network and then implement it through CMOS layout? I have issue finding the best form of the ...
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0 votes
0 answers
29 views

MAX Layout System wiring parameters

I am using max layout system. I went to the wiring parameters and see a number of options. "WIRE WIDTH" which I can change the width of wire as I draw it. but what the "WIRE GRID " ...
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5 votes
1 answer
692 views

What does "strap" mean in this context?

This is one common error in layout IC. What does "strap" mean in this context? LUP.6 { @ Any point inside NMOS source/drain space to the nearest PW STRAP in the same PW <= 30 um @ Any ...
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How to cross differential traces in Altium using the interactive differential pair routing tool?

I am every day more and more baffled by how Altium seems to do everything, but in such counterintuitive ways. My latest struggle was trying for an hour to learn how to use the differential pair ...
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