Skip to main content

Questions tagged [layout]

Layout is the process of designing a PCB including placement of parts and routing of traces.

Filter by
Sorted by
Tagged with
0 votes
0 answers
47 views

How to add text on PCB Pads?

How to add text on PCB Pads in Altium Designer I just this Image Im Interest to known how to do this
Monesh Rathod's user avatar
0 votes
1 answer
40 views

PCB microprocessor 16MHz oscillator layout feedback

I thought I'd give an update to the changes I've made for my 2 layer PCB regarding the 16MHz crystal oscillator that I've added. Yes, this is a continuation of PCB layout for 16 MHz crystal oscillator....
hdaniu's user avatar
  • 31
3 votes
0 answers
50 views

How are pad impedance discontinuities precisely compensated for in high speed PCB layouts?

I stumbled across a recommendation in an 850MHz opamp datasheet that said the following: All ground and power planes under the input and output pins must be cleared of copper to prevent the formation ...
Polynomial's user avatar
  • 10.8k
2 votes
3 answers
776 views

PCB layout for 16 MHz crystal oscillator

I'm barely getting started with PCB designing. I'm working on my dissertation project and I want to develop a PCB board with an integrated microcontroller (ATmega2560-16AU) and some motor drivers as ...
hdaniu's user avatar
  • 31
2 votes
1 answer
86 views

Implementation of Circuit in AN104 for Load Transient Test

I have been testing the transient response of line regulator simply with a MOS and the resistor, this method, however, cannot generate arbitrary current and the current is not accurate. To improve the ...
cc Lau's user avatar
  • 23
2 votes
1 answer
195 views

SEPIC DC-DC converter

I want to do the layout for a SEPIC DC/DC converter as follows: In the datasheet of the driver LM3488, they have recommendation for layout, which means the traces should be as short as possible for ...
Andromeda's user avatar
  • 477
0 votes
1 answer
42 views

What should I do when clearance boundaries overlap with SMD pins?

I am brand new to layout design. I am using the TPS62136RGXR buck converter in my design. However, according to the attached image, the pin's clearance boundaries (0.2mm according to JLCPCB's assembly ...
NickRand's user avatar
1 vote
0 answers
27 views

SDRAM Clock routing. Top Layer vs Sandwiched between GND/Power Planes. What's is better for EMC?

Planning a new design, were I finally removing a termination resistor on SDRAM_CLK line. Planning to increase the clock speed to 200MHz as well. Previously it looked like a straight forward decision ...
MMG's user avatar
  • 41
3 votes
1 answer
190 views

LM2675 outputs wrong voltage, not sure about layout

I'm making an ESP32 board to control some 12V outputs, so I got an LM2675-3.3 buck converter IC (datasheet) to power the MCU. This is my first time designing and soldering a PCB and I'm guessing I may ...
Axl Vang's user avatar
3 votes
1 answer
132 views

KiCad footprint pad clearance not applied

I have an IC with tight pad spacing. As such I want to override the global clearance settings for this footprint to be able to route it. If I go to the footprint properties clearance overrides>...
Alexander Ohm's user avatar
1 vote
3 answers
76 views

Do I have to place a gap in the GND plane to reduce noise from DCDC?

In the past I made few designs with switching power supplies and I'm aware about the needs to keep traces short and with low impedance (i.e. where possible use filled zone instead of tracks) and to ...
Mark's user avatar
  • 1,235
4 votes
2 answers
495 views

PCB layout for crystal of MSP430FR6047

I want to design a layout for MSP430FR6047 and I was reviewing a reference design form TI for MSP430FR6047 Evaluation board, then I noticed the are 4 different GNDs as follows: (USSXTAL_GND, ...
Andromeda's user avatar
  • 477
1 vote
1 answer
47 views

Impedance of different track widths - Should I compute the average width?

Assume that you having one track that goes from 0.11mm in width to 0.09mm in width. I want to compute the impedance, but I need to select the width. What option should I select? The largest width of ...
euraad's user avatar
  • 1,324
0 votes
1 answer
67 views

Should I connect my mechanical spacer pad to GND?

Is there any advantages for connecting the mechanical spacer pads on the corners of the PCB to GND? 2D view: 3D view:
Andromeda's user avatar
  • 477
0 votes
2 answers
55 views

Using transfer via in PCB

From which frequency we need to consider a transfer via, when there is a transition of a signal on different layer in a PCB? higher than 1GHz? I need to know the threshold for considering these types ...
Andromeda's user avatar
  • 477
0 votes
1 answer
56 views

Editing 3D model in Altium

Would you please let me know how can I edit a 3D model for Altium? I want to do it in Altium not with a second party software. For example in this example this pins are too long and I want to make ...
Andromeda's user avatar
  • 477
1 vote
1 answer
55 views

Placing the feedback components close to the inverting input pin or output pin?

In closed-loop operation amplifiers design, should we place the feedback components close to the inverting input pin or output pin in our layout? and why? For example for this design: I put the ...
Andromeda's user avatar
  • 477
0 votes
0 answers
30 views

Two different snap to Grid area in a PCB

I one of my projcts I faced with an PCB that there are two regions with different snap to grip values (software Altium Designer): Why would we need this in a PCB? How should I make it or remove it?
Andromeda's user avatar
  • 477
2 votes
1 answer
63 views

Un Tented pads on PCB [duplicate]

Would you please let me know what would be the purpose of the following Un Tented round pads in a PCB? Regards
Andromeda's user avatar
  • 477
0 votes
1 answer
38 views

Altium designer DRC Configuration

In my schematic, I have jumpers to separate the power of an IC from the supply rails as follows: I have many of these jumpers in my circuit, when I run DRC, it says all the Vn net should be connected ...
Andromeda's user avatar
  • 477
0 votes
0 answers
38 views

Operation amplifier optimized layout- Noise- Signal Integrity

I was watching a seminar from Fedevel academy, in this seminar as all the datasheet has mentioned, we need to remove GND and PWR plane underneath the negative inverting pin and the output pin of the ...
Andromeda's user avatar
  • 477
1 vote
2 answers
79 views

Adding a ground loop on the edge of the PCB [duplicate]

I saw on some PCB, the they have added a ground loop on the edge of a PCB, I wonder what would be the benefits of this?
Andromeda's user avatar
  • 477
0 votes
0 answers
44 views

Operational amplifier layout- Controlled impedance

In the following picture, we can see a reference layout by Texas instrument for OPA838: I noticed, in the polygon on the top layer, they have used a specific gap=0.5 mm, I wonder if they used a ...
Andromeda's user avatar
  • 477
0 votes
1 answer
58 views

A question about layout: How to connect the gate to metal 1 layer?

I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer) In the process I used, there's a design rule ...
Jack Black's user avatar
0 votes
0 answers
62 views

Capacitance on op-amp input (inverting pin)

I have the following configuration for my amplifier, which is an transimpedance amplifier: I need to connect my transducer to the inverting pin of my amplifier by using a dip switch to be able to ...
Andromeda's user avatar
  • 477
0 votes
1 answer
104 views

Removing GND and Power planes under the feedback pins and traces in opamp layout

I want to use a reference design form Texas instrument as a reference for my layout for OPA838, I noticed this reference design is a 4-layer board (signal-GND-Power-signal): Reference: the image is a ...
Andromeda's user avatar
  • 477
1 vote
1 answer
57 views

How to Add White Sheet Page and Template to Altium PCB Doc?

I want to add this kind of white sheet page to my PCB layout. Can anyone can help me with this? There is no option sheet template for PCB.
Monesh Rathod's user avatar
0 votes
1 answer
65 views

Why routing orthogonal signals with reference to the same plane?

In the book "ELECTROMAGNETIC COMPATIBILITY ENGINEERING" from Henry W. Ott it is often mentionned that orthogonally routed signals should reference the same plane. But I don't understand the ...
raphaelb's user avatar
0 votes
0 answers
16 views

How to set Tanner L-EDIT and convert polygons to boxes

when I use LEDIT v12.x, I can use "Merge" to convert rectangles (polygons) to rectangles (boxes), but in the new version (v16.x) I cannot do this. I guess I can modify the default parameters ...
陳立豪's user avatar
3 votes
3 answers
752 views

Return current on PCB

As PCB designers we all know that for high frequency signal (MHz), we should design return path (reference GND plane) underneath the signal as follows: https://www.allaboutcircuits.com/technical-...
Andromeda's user avatar
  • 477
1 vote
0 answers
72 views

PCB layout recommendation for Op-Amp [duplicate]

When designing a PCB for Op-amps normally there are some guidelines in the datasheet of the device. For example, for OPA838 the suggestions are: Signal routing must be direct and as short as possible ...
Andromeda's user avatar
  • 477
0 votes
1 answer
104 views

Investigating the effect of PCB layout parasitic in an op-amp amplifier by simulation

Would you please let me know what components I should add to my schematic as result of PCB parasitic to make my simulation more accurate? As an example, the following image shows an amplifier ...
Andromeda's user avatar
  • 477
2 votes
2 answers
173 views

Which shunt resistor placement is best?

I came across this picture in a LinkedIn post recently. I understand the reason behind the top two pics. The tracks are too thin to handle the current. However, I do not understand the bottom two ...
JoeyB's user avatar
  • 2,389
8 votes
3 answers
2k views

Is it good practice to place decoupling capacitors near connector pins?

I’ve seen some notes online about placing decoupling capacitors near I/O connector pins, as well as some saying power lines of connector pins. Despite this, I feel that I haven’t often seen capacitors ...
cs_eng_516's user avatar
0 votes
1 answer
37 views

I am not able to see trace attached to component while dragging component in Altium

While dragging the component in Altium, I cannot see a trace attached to the component. I checked all the settings, I even reset all settings but it is still not working. Can anyone help me? I want ...
Monesh Rathod's user avatar
0 votes
2 answers
186 views

Is this a "good" PCB layout for the BQ25798 IC?

I want to know if this is a good PCB layout. The ground pours are on the top and bottom layers. This is a two-layer PCB design. The PCB is based on the BQ25798 IC from TI. The blue traces are all the ...
JoeyB's user avatar
  • 2,389
0 votes
0 answers
118 views

LUP.6 DRC ERROR

I got a latch up #6 error while performing a DRC. LUP.6 { @ Any point inside NMOS source/drain space to the nearest PW STRAP in the same PW <= 30 um @ Any point inside PMOS source/drain space to ...
rosetta's user avatar
0 votes
0 answers
32 views

Is it possible to implement shunt stubs to replace shunt capacitors for differential matching?

I am reviewing the subject of stub matching. For example, consider Network D: Example photo screen-shot from TI documentation: https://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-...
j c's user avatar
  • 45
0 votes
1 answer
35 views

LED PWM traces splitting reference power plane adjacent to bottom 5V DC supply ground zone on 4-layer PCB

I have almost finished my first 4-layer PCB design using Signal(Top)-Ground-Power-Signal(Bottom) stack-up and have some questions before sending it to production. Due to the very tight space on the ...
Semih's user avatar
  • 67
0 votes
0 answers
34 views

Routing power return path between battery holders on opposite edges of the PCB

What is the best way to route the current path between two battery holders on opposite edges of the board where the shortest, most direct path would cross clock generator or would be near a sensitive ...
try-catch-finally's user avatar
0 votes
1 answer
58 views

Altium Top Paste not fully poured

In the picture below, Top Paste's 3 of 4 FETs is not poured well. I can't see the reason for this. Any suggestions?
MSB's user avatar
  • 27
8 votes
5 answers
2k views

How necessary are gate resistors for MOSFET gate driving?

I've been studying MOSFET gate driving recently, aiming to understand the importance of layout. To investigate this, I designed a PCB as shown below: In this PCB, I used the FD6288T (https://static....
0x1a551e2's user avatar
  • 105
2 votes
1 answer
95 views

In a footprint spec, what does "Do not use gilded pattern" mean?

Looking at the recommended footprint for a CM choke, Murata# DLW43SH110XK2 It warns "Do not use gilded pattern". I've never noticed such a thing before Should that be interpreted to mean ...
Pete W's user avatar
  • 1,537
1 vote
3 answers
63 views

IC thermal pad: Place heat sink directly over bottom-side thermal pad and thermal vias

If a VQFN package (below) has a thermal pad and thermal vias beneath it, the bottom layer should have an identical pad to act as a heat sink. Is it typical to surface mount a heatsink on the bottom-...
kando's user avatar
  • 437
0 votes
1 answer
61 views

IC thermal pad: Duplicate zone in inner layers also?

Question For a passively-cooled portable device (fanless, ambient cooling), what are typical methods to supplement the thermal pad of an IC to mitigate device temperature rise, (beyond efficient ...
kando's user avatar
  • 437
2 votes
1 answer
104 views

AC line filter polarity

Currently I working on very simple AC power mains distribution board. I want to use PCB-mounting AC line filter SCHAFFNER FN405-10-02 for EMI reasons. The datasheet provides simplified schematic: ...
plumbum_by's user avatar
1 vote
1 answer
83 views

PCBWay : Minimum SMT Width

Question Is it bad design to alter the manufacturer-recommended VQFN footprint as follows: • Pin copper width: 0.2 [mm] --> 0.3 [mm] • Pin copper to copper spacing: 0.2 [mm] --> 0.1 [mm] and if ...
kando's user avatar
  • 437
3 votes
1 answer
200 views

Ethernet controller EMC failure

I designed my very first Fast Ethernet PCB and it is having a hard time passing Radiated Emissions. The result came back from the test lab shows that it is radiating strongly at 125 MHz: In the ...
HV16's user avatar
  • 345
0 votes
1 answer
87 views

A 10cm long trace runs through the middle of a 2 layer PCB and cuts the ground plane in half one one layer. How to prevent this?

Basically, my PCB has one side that will be facing an enclosure's panel with IO. This side has a slide switch that needs to power a 12V power relay that draws 37.5mA when turned ON, but is located in ...
StickySli's user avatar
0 votes
2 answers
107 views

Flyback converter sense resistor placement and wiring

I am designing my first ever Flyback converter. The Fsw = 100kHz. Peak primary current = 3.26A. The converter has to fit in a very small space, so I'm making a lot of compromises. For example, I could ...
slimcolt's user avatar
  • 297

1
2 3 4 5
17