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Questions tagged [layout]

Layout is the process of designing a PCB including placement of parts and routing of traces.

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29 views

Use of internal PCB ground plane as ESD baseplate/EMC reference plane of product in plastic enclosure

I am designing an electronic product which will be housed in a plastic (non-conductive) enclosure. There are a number of, mostly shielded, I/O cables (Copper 10/100/1000Mb/s Ethernet, USB 2.0, RS232, ...
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48 views

Connecting the Chassis Ground and Signal Ground in my PCB

I have been reading alot of questions on this site to clear my understanding on Chassis, Signal Ground, ...
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3answers
387 views

Modifying land patterns generated with IPC-7351B wizard

I generated a 4x4mm 0.45mm pitch QFN28 according to the Atmega328P datasheet: However, the pads on the corners (1+28, 21+22, 14+15, 7+8) are too close to each other, less than 0.2mm apart (when ...
2
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2answers
116 views

Using polygon pours for small signals in PCB design

I'm trying to improve my PCB routing skills. When I started out a few years back, I just layed out the components and ran tracks with a fixed width between them. I didn't even know about polygon pours....
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2answers
60 views

What happens if two N-wells touch each other?

When designing the layout of a CMOS inverter, we need to use an NWELL to build the PMOS. Following scalable rules, when desining the masks I have to be sure that if I want to build two NWELLS using ...
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1answer
38 views

PE pin position

I have one question. I'm designing a PCB which is a sort of smart switch (so, basically, you have one 230V input and one 230V output, where the output and the input share two wires, N and PE, and the ...
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2answers
112 views

How to separate ground efficiently in a thyristor circuit controlled by sensitive microcontroller

I've been trying to design capacitive discharge ignition circuits using a microcontroller ARM (Texas and ST) without success. Each circuit using them presents intereference problems during spark ...
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0answers
26 views

How to simulate a piezoresistive pressure sensing MEMs layout without COMSOL?

I have a masks layout of a Piezoresistive MEMs pressure device that I've designed in LEdit(Tanner Tools Eda). The device consists of 4 piezoresistors bonded onto a thin diaphragm which deforms ...
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2answers
49 views

IC layouts - Transistors (Body)

I'm trying to get into IC layouts... Why do I see some IC layouts with or without the body terminal on the transistors. Do MOSFet transistors need a body terminal in an integrated circuit? Or should ...
2
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1answer
39 views

SATA 2.0 to M.2 (NGFF) design

I am designing a PCB with a A20 (allwinner) SoC. This SoC has a SATA 2.0 host (RXP RXM TXP TXM) that I have to route to a M.2 "M" key connector. I found only one source for pin out, but I can't find ...
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0answers
39 views

Creating a balanced dipole from two monopole chip antennas for use on small PCBs

I'm trying to use a monopole chip antenna on a PCB much smaller than the one recommended in the datasheet. I am wondering if I can get away with a much smaller board by using two monopole antennas ...
1
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1answer
75 views

Bypass caps under BGA: Should I isolate vias from planes?

I'm placing bypass capacitors underneath a BGA package. In some cases the caps cannot land directly on the vias-in-pad ("VIP"), so I'll need short traces from the VIPs to the caps: In this example ...
4
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3answers
322 views

Cost optimization - PCB Area vs. Double-sided load

If one has an opportunity to choose between laying out a PCB as either a single-side load (components all on one side, so it goes through reflow only once and requires only one stencil) or a double-...
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3answers
126 views

PCB trace width can't meet the rated current

The rated current for VCC5_AC from AC adaptor is 2A. According to the calculation on http://circuitcalculator.com, the trace width for 2A should be 30.3mil. However, as indicated above, the width of ...
2
votes
1answer
96 views

Shunt resistors and PCB layout

I have several questions about the current sensing through a resistance. The resistances are 2-SMD package and I will use the 4-wire kelvin method for the layout.(see image) Specifically, there are ...
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0answers
44 views

Split Ground plane with motor drivers

This is a PCB with few stepper drivers. I have a question about the ground plane. I have this idea to split the ground plane for each driver, so, I force the return path to pass through the capacitor....
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1answer
85 views

Machine learning for floorplanning

I have an educational assignment to make an floor-planning tool. Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
2
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1answer
162 views

Grounding and Signal Integrity of my PCB Layout (ADC, SMPS, SD card, USB)

I am currently designing a battery monitoring system for an 8 cell lithium battery pack. I originally made the device using a STM32 dev board and breadboard, with an SD card to log data. The system ...
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2answers
50 views

Do cascoded MOSFETs need to be in their own wells in order to properly connect bulk to source?

I am learning to design CMOS layouts. When creating the layout for something like a cascoded current mirror, are individual wells needed to properly connect the bulk to source? For example, for the ...
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1answer
59 views

Is it acceptable to split one wide wire into two narrower wires in PCB layout?

I have an issue about connecting power wire to the IC. The power wire (50mil) is wide than the pin width of destination IC, so I want to split the wide wire into two narrower ones(20mil) which match ...
1
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1answer
90 views

Connection of ESD return path the System GND

In my current design I have one RJ45, one RS232 and two RS485 ports. I have TVS diodes CDSOT23-SM712 for serial channels and ESD7104MUTAG for Ethernet port. Now I have connected the ESD GND of the TVS ...
4
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1answer
114 views

Full bridge driver capacitor ringing problem

This is my first time designing a full bridge driver. I am experiencing problems with ringing on the output. I have made a pcb for it. This is a picture of the top side of the board. Backside Input ...
3
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1answer
75 views

RF layout bend over Component

We lay out the RF trace for below model. GSM 900MHz RF trace maintain at 50Ω impedance. As I know, the RF trace needs to be as short as possible for better signal. Do we need to bend RF trace ...
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1answer
28 views

Cadence Virtuoso - Cell Parameterized [closed]

Please see attached. I am unable to view the Poly, Metal, Cont layers for the PMOS & NMOS instances. Need a bit of assitance on how to fix this issue
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1answer
143 views

USB 3.0 Length matching in PCB Layout

I'm doing PCB layout for a USB 3.0 connection and I'm curious about if there's a length match requirement between the unidirectional super speed pairs and the bidirectional high speed pair. This isn'...
4
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1answer
119 views

PCB layout rules

What are the design rules that should be applied when designing a PCB layout ? I am currently using Kicad, because it is free and it is simple to use. I made a layout for a L200 power supply. I wand ...
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1answer
2k views

What breadboard simulation software is this?

I'm not familiar with what software is available and cannot recognize the origin of this diagram. Does anyone know what software this is? I'm only guessing that it can perform simulation; it may just ...
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0answers
61 views

GDS, OASIS, etc. vs LEF/DEF: which is better?

I have two questions here. By the way, I have searched about the differences but I wanna know more. So, Can LEF/DEF format describe everything that GDS, OASIS, etc. formats, can? What can I do with ...
6
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3answers
2k views

Is it ever bad to run an IC VCC trace next to a ground plane with 1mm clearance?

Since my last board flopped, I looked at it again and noticed a ground loop (because the DB9 casing completed the loop). Now I adjusted my board so that there is no loop of any kind. Instead, I'm ...
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2answers
63 views

How can I attach the same footprint to subparts of the same IC in Altium?

I have two sub parts of the same IC (STM32L476RG). I have added these sub parts as two components in the same schematic library and have attached the same footprints for both of them. But when I ...
0
votes
1answer
32 views

How to get isolated area using Eagle CAD?

I've created an area using ratsnest and a simple route as you can see in the first example layout. Both belongs to the VIN net. Then I added a GND polygone. Using the ratsnet function I'm expecting ...
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2answers
59 views

How to generate board plot/image in Eagle

I designed my own PCB in Eagle so I have both the schematics and the board files. I would like to generate a figure like this one made for Arduino board in order to include it in the user manual that ...
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2answers
96 views

Putting GND on POWER layer

I have a four layer PCB, with a traditional: signal layer, power layer, ground layer and final signal layer. Due to the set up with the power rails, there are some large spaces on the power plane ...
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1answer
170 views

Creepage Distance in Altium Designer

I have a design with a high voltage and a low voltage part. Between the two I need to have a creepage distance of 8mm. Some optoisolators I use in my design are not wide enough on the PCB footprint, ...
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1answer
277 views

Defining a circular cutout in a pad in Altium

I'm creating the footprint for a Wurth inductor, 744043100. The recommended land pattern is below. They use a radius 1.8 mm circle in the middle of the component to define a void in the pad. I'm ...
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0answers
34 views

Maximum metal length and single connection routing in Virtuoso Layout XL

In our process technology we have only 2 metal layers. The first metal layer can be used for routing but the second metal layer is used to make a jumper over metal layer 1 (in case of crossover) by ...
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0answers
36 views

CADSTAR PCB layout pad name

I am new to CADSTAR. But I have learned a lot in 2 months. I have the Schematic as shown. But when I generate the PCB file , I don't see the IC pad name/ number.(Marked in the following picture with ...
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1answer
81 views

Routing of PCB layout/layout review after the schematics [closed]

How do I learn PCB layout review by myself?
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2answers
116 views

Non-isolated DC-DC buck converter layout - which one is better

I'm doing a DC-DC buck converter routing, using TPS62130. As known, the key point to route a DC-DC converter is to reduce the current loop area. In my design, I have a dedicated ground plane, so I ...
7
votes
2answers
717 views

Single ground plane vs split planes?

I have seen conflicting sources about ground plane design. I have been told at my work many times, just slap a single massive ground plane in and that works well enough, we don't deal with anything ...
3
votes
2answers
282 views

Ethernet ground multilayer pcb

I'm currently re-designing a 12-layer pcb. The only thing I am still struggling with is the routing of the ethernet. The layer stackup is as follows: Top Layer GND_1 MidLayer_1 PWR_1 MidLayer_2 ...
1
vote
2answers
91 views

Thermal stabilization of TH LED (layout recommendations)

I have to develop a circuit for LED-based optical reference. Due to specific requirements, only available LEDs are in TO-18 packages with metal cans. The problem is that LEDs experience spectral ...
5
votes
2answers
549 views

STM32 MCU PCB layout review (crystal & decoupling & ADC)

Introduction: I am designing a hobby electronic for first time, using STM32 to control a soldering tip. I read many documents of PCB layout, and also many information from this forum. And this is my ...
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3answers
155 views

Is it possible to request a mapped diagram of electricity usage from your provider? [closed]

Whenever I see our electric bill, it just shows the amount owed, and the amount used (in kWh). However, it would be really nice if we could request or pay a premium per month, for a service that ...
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0answers
583 views

RN2483 PCB Layout

I am designing a board based on RN2483. As i have none experience on RF design i am following the guidelines from microchip's datasheet as the pictures bellow. So my question is about the many vias....
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votes
1answer
57 views

Do I have to route VCC and GND signals on PCB if planes are used

I am designi a board where I have a VCC plane and a GND plane.I have decoupling capcitors and was wondering if I should manually connect these decoupling capacitors with a trace since I plan to have a ...
5
votes
2answers
570 views

Unused area on layout

I have prepared the following PCB layout I am a hobbyist and when I look at other - professional - boards, mine looks a little strange when considering the empty spaces to the right, and to a lesser ...
2
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1answer
126 views

Mark decoupling capacitor

I'm working on a PCB. As ECAD software I am using KiCAD. All ICs will get two decoupling capacitor. One 100n ceramic and a 10uF electrolytic. For now I place them like shown in the picture at each ...
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0answers
191 views

6 layer PCB layout with RF antenna track

I am doing my first 6-Layer PCB with RF antenna connection tracks. I am using this stack-up: L1 Signal Layer L2 Ground Plane L3 Power Plane L4 Signal Layer L5 Ground Plane L6 Signal Layer I ...
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3answers
93 views

Plated PCB Hole Shorting Power to GND?

I’ve been soldering components to my PCB; all has been good, but recently, after soldering a big electrolytic through hole cap, the power and gnd plane were shorted. This persisted even after removing ...