Questions tagged [layout]

Layout is the process of designing a PCB including placement of parts and routing of traces.

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Layout polygon pour connect to GND or VGND noise reduction

I am using MCP6V02 as transimpedance amplifier as shown below schematic, I want to know is it better to connect polygon pour to GND or VGND to reduce noise on the amplifier. (Below schematic is for ...
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24 views

Altium Library Issues- Replace uknown schematic library with know library

I am using Altium 20.1 and my question is regarding the sch library. I generated a schematic library and I want to use that as my default library for the components. When I try to update the schematic ...
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35 views

Shielding a signal with both GND and supply? [closed]

What happens if a net is shielded by GND on one side and VCC on the other side inside an IC? Assume that the 3 lines are on the same metal layer. This is an interview question and I would like to know ...
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86 views

PCB Layout Optimization Regarding VCC and GND

I have two questions regarding routing power and ground. With respect to power, is it generally better to flood copper planes and have one via per pin/pad connecting directly to the plane under, or ...
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65 views

PCB Layout: Variant A, B or C

I've just started dabbling with hardware design and I'm a little confused. Which one of the following variants for the battery protection circuit is the most optimal one? I've been trying to follow ...
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15 views

Current sensing, clearance, trace width

I have to design simple PCB that will measure current by shunt resistor(R7, R8, R9) and voltage by divider. Board has 3xin and 3xout for different voltage/current specifications. I have the following ...
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35 views

Power Electronics - Voltage Sensor Layout

I have the following voltage sensor to place in a layout of a low voltage converter (800 V dc link). The input voltage dividers need to be located in the power-stage section of the PCB. The question ...
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88 views

4 layers PCB mixed signal GND review

I'm a beginner at PCB design. We've subcontracted routing for a PCB; it contains mixed analog and digital signals and it's a 4-layer PCB with an inner split GND plane (Signal - GND - VCC - Signal). ...
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38 views

High-speed IC GND next to oscillator GND

I am designing a board, 4 layer with a ground plane. In my current layout, the ground VIA of an oscillator IC is very close in proximity with the ground VIA of a high speed IC. Is there a chance that ...
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594 views

High-speed signal across plane gap

I need to do a PCB layout where I have one digital signal that has relatively short rise/fall times crossing a slot in a GND plane. I know that this should not be done, because the signal return ...
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298 views

Design a high accuracy ADC circuit (example of differential ADC LTC2348 for PSD signals)

Context: I am about to send a board to manufacturing which includes the LTC2348 for high-precision acquisition of the 3 analog outputs (single-ended) of a PSD frontend. The 3 signals are Xdiff (...
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71 views

Are these ground stitching vias? If so, why are they placed in this manner?

For reference this is a cheap analog RCA capture card I got from amazon a while back. Today I broke the enclosure on accident and as a studying EE who does some PCB design, I was curious about this. I ...
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47 views

FET electrode convention?

Are there any conventions that allow one to tell which electrode is source and which one is drain?
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44 views

Resistors in high-speed I/O trace when impendance mismatching

I am little bit confused over impedance matching when dealing with high-speed digital I/Os. I would like to share some perspectives in hope to clarify a few things. Let's consider a digital output ...
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60 views

Unknown indicator of package specification

I am creating the footprint of an IC, and the manufacturer has specified this below: I cannot figure out what C0.3 stands for. Is it the length of the diagonal? If it helps, according to another ...
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1answer
82 views

Reduced pad size

I am working with an LGA packaged IC. Each pad has a diameter of 0.5 mm and the distance between them is 0.3 mm. I need to pass tracks between those pads. According to the design rules, min (and ...
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40 views

High Voltage NMOS layout design in UMC130nm process using Cadence Virtuoso

I am required to design an NMOS switch in UMC130nm process which is capable of enduring approximately 10V VDS (drain to source) when the gate is 0V. And a current of approximately 50mA when the gate ...
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65 views

PCB Layout - Transistor to convert analog signal to digital pulses - how to connect emitter GND

If have designed the following circuit to convert a certain analog signal of an amplifier to digital pulses. The circuit works well - except for one point. My prototype PCB has 4 of these amplifiers ...
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64 views

KiCad placement using coordinate system

I am new to KiCad but have extensive experience with Allegro: The goal create a rectangular board outline that is 55 x 30 mm with the top left corner at x,y 0,0. This is possible in OrCad through the ...
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34 views

Can an ExpressPCB “.pcb” file be converted/imported to any other format?

I was given a .pcb file and I'd like to view it to confirm it's a valid file and at least minimally what I was expecting. ExpressPCB .pcb files are a proprietary format. I use MacOS so a native app ...
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30 views

Is it necessary to remove ground on all layers when using isolated DIO

So, I am using uptocouplers and digital isolators for a project connected to a microcontroller GPIO. I removed the ground (ground plane cutouts) under the load side of the components, is it necessary ...
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1k views

Why do layout footprints for Crystals often define via keepouts?

For example, one of the EagleCAD standard footprints for an HC-49U package through-hole crystal (mounted horizontally, so that length of the "can" lies against the PCB) looks like this: The ...
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75 views

Crystal Layout for RTC

I require recommendations for the layout of crystal. I am designing a board which uses an external RTC. The Mfr. part number for RTC is PCF8523TK/1,118 and Mouser part number is 771-PCF8523TK/1118. It ...
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28 views

Design guidelines for RF castellated edge connections

I've seen many examples online of castellated vias at board edges used for module connections. However, all of these seem to be for low frequency signals. When using a castellated via to connect an RF ...
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2answers
77 views

Potential Difference in the Ground plane

I am new to layout designing. I am using Eagle 9.5. Here is the layout design of my project: Right section of the PCB is for analog circuit. middle section is for DAC and ADC and digital output of ...
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55 views

Chip antenna layout suggests shorting feed line to ground?

I'm working on layout and trying to replicate the test configuration for this chip antenna. I'm a bit confused, however: From datasheet: https://media.digikey.com/pdf/Data%20Sheets/Yageo%20PDFs/...
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3k views

How do I separate ground planes on a PCB with two different voltages?

I am using a four-layer PCB with the following stack up: top signal, ground, 3.3V VCC, and bottom signal. All of my components require a 3.3V input except for this sensitive optical sensor (MAX30102) ...
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Analog CMOS IC layout: DRC, DFM, DFR

Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR? What I understood during research: DRC (Design Rule Check) - checks if a laid out block follows technology rules what ...
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38 views

Do I need to Reduce the Width of a Power Trace for Thermal Relief When it's Passing Through a Pin on the Chip?

I'm routing a PCB. Currently, all power traces are 20 mils. A QFP chip on the board requires multiple voltage rails to operate, I found the easiest solution is passing a power trace through a pin on ...
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106 views

Best practice for layout of balanced audio grounds

I'm designing a simple board with a differential ADC. The inputs are from TRS jacks that will (usually) carry balanced audio signals. The datasheet, and general best practice, advises keeping analog ...
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89 views

LM2678 PCB Layout question / review

After my initial question about switching regulators I had decided on trying to use an LM2678 for an adjustable/variable voltage form 5-24V and 5A max with an input of ~30VDC. The application will be ...
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67 views

Step-up layout - Is important trace order?

I am adding step-up to my PCB and I wonder if I have to make trace order like in this design. I mean if input voltage has to go first through power inductor, then capacitor and finally step-up ...
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30 views

Check my battery powered layout

Few days ago I had topic about issue with power inductor crashing circuit. I almost resolved issue without making new by 90%. However sometimes circuit crashes -> I did some updates based on replies. ...
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4k views

PCB Crystal Layout

I'm designing PCB with 16MHz crystal for ATMega328p. Right now that is my layout. VIAs ring around edge of board is to stop EMI radiation from edges. There is no Ground plane under capacitors and ...
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65 views

How do I decide on a proper PCB ground layout?

I'm trying to figure out best practices regarding ground layout, but it seems the more I read the less I understand about the subject as many recommendations seem to contradict themselves. So far I ...
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1answer
114 views

When to Remove the Ground Plane under SMD components for High-Speed Signals?

I'm reading TI's recommendations on routing high-speed signals. Most of the guidelines are common sense, but there's one guideline that I haven't read before: It recommends completely removing the ...
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148 views

A few questions about High Current on PCB

Original schematic: My attempt at drawing the PCB: The routes are drawn on both layers and the thickness of the power route is 600 mil(300 on top and 300 on bottom). It is necessary to support ~15A. ...
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100 views

High current on pcb traces

Is it ok to put the vias like that, help with something for a high current? The thickness of the route is 400 mil (200 on top and 200 on bottom). It is necessary to support ~15A. In the right corner ...
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22 views

TI webbench PCB

Looking at TI's TPS56339 and looking at what TI outputs for Altium opens up some questions for me. In the following image, the highlighted component is the TPS56339. Has the assembly process ...
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40 views

How to connect multiple star points and ground zone together on PCB?

I have designed this PCB layout for an all analog Op Amp circuit plus LM386 for headphones pictured right in the yellow section: Are we allowed to have multiple star points, as I have on the PCB? And ...
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109 views

Layout PCB High Current

If i have a high current (12 amps) passing through my route is it ok to put via on it or to duplicate the route (150 mil on top and 150 mil on bottom)?
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153 views

How to connect the power plane Microchip AN2587

In microchip AN2587: EMI, EMC, EFT, and ESD Circuit Design Consideration for 32-bit Microcontrollers Page 50 . The following power connection for Vdd is recommended (similar diagram in datasheet) . I ...
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48 views

Determining width and length from CMOS inverter layout

How do I determine the width and length from the following cmos inverter layout, given that lambda=0.25um? The answer is Wn=1.0um, Ln=0.25um, Wp=0.5um, and Lp=0.25um. I know that the length is equal ...
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37 views

Get net names from LEF files

I'm analyzing the layout of a circuit by parsing the LEF and DEF files with PyParsing (Python). I parsed everything, no problem in this part. I also have on the side the netlist of the circuit. My ...
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79 views

Pads very close together, no space for guard ring? What should I do?

Introduction to the problem I use an OpAmp to buffer the output of an InAmp and to drive the input of an ADC, so the signal path looks basically like this: InAmp -> OpAmp -> ADC The device of ...
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2answers
41 views

Layout of Power lines to extension board (Temperature Sensor)

I'm designing an (single sided) extension board that will hold a 3-pin temperature sensor (TSIC 506). As the order of the pins go from 1 Vcc, 2 Signal, 3 GND I wonder if I should follow the same order ...
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110 views

20MHz clock signal over several PCBs

I am running a 3.3V 20MHz clock signal for LED drivers over 10 PCBs that are connected to each other over short cables. Overall, the clock signal must travel 1m. Is this even possible with a 20MHz ...
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25 views

Orcad hierarchical design alias / physical net

A hierarchical based Orcad schemactic has two children blocks and the parent one. Each child block is connected through the parent via the net called VDD_IN. However, once I hover on the net, a ...
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82 views

How to place SDRAM data-lane correctly in 4-layer PCB?

I'm thinking about the trace/lane ordering to 167Mhz SDRAM with 4-layer PCB: Now its follow: Data traces CLK (only) DQM traces Address + control + command (Ax + BAx + Strobes and CKE) Is it better ...
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31 views

what is exposed ground meaning in passive antenna layout?

Could someone help me understand what is the meaning of exposed ground in pcb layout. I'm designing layout of my project and one of the component on it is passive antenna. What does exposed ground ...

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