Questions tagged [layout]
Layout is the process of designing a PCB including placement of parts and routing of traces.
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Crystal, PCB Layout
I've completed a few circuit board layouts before, however this is my first time doing a layout with a oscillator/MCU. After doing some reading (via this site and datasheets) I've come up with the ...
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SMPS transformer orientation with respect to PCB: what's best for EMC?
I have the option of either using a vertical or horizontal bobbin for a flyback SMPS transformer, and I can't conclusively decide which would be best for minimal radiated interference to be picked up ...
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How do I separate ground planes on a PCB with two different voltages?
I am using a four-layer PCB with the following stack up: top signal, ground, 3.3V VCC, and bottom signal.
All of my components require a 3.3V input except for this sensitive optical sensor (MAX30102) ...
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CAN bus layout design
I am trying to design a CAN bus node. The CAN bus shall be split-terminated with 120Ohm, 60Ohm for each line.
Therefore i tried using this paper to calculate a characteristic impedance of 60Ohm for a ...
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Is it ever bad to run an IC VCC trace next to a ground plane with 1mm clearance?
Since my last board flopped, I looked at it again and noticed a ground loop (because the DB9 casing completed the loop).
Now I adjusted my board so that there is no loop of any kind. Instead, I'm ...
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Decoupling Capacitors on each VDD pin on a tiny 36/49 ball WLCSP/µBGA chip really necessary?
I've searched this and many other sources on Info on decoupling capacitor placement, but couldn't find any info specific enough to my current problem.
I'm currently doing a PCB Layout for a tiny, ...
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Feedback on this PCB
May I ask your comments on the layout below? Specially the via under the MCP16322. The layout is still missing the connector for the in/out voltages, but would love to have your opinion at this point.
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Four layer PCB layout suggestions
I have recently designed a four-layer PCB in KiCad. It is a spectrometer having PIC24EP and a CCD linear image sensor (TCD1304). The layer stack up is as follows:
Signal (no copper pour)
Ground
3.3 V ...
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Breadboard component layout design
What techniques are useful when layout a circuit on a breadboard? Specifically, making it as least cluttered and readable as possible. My circuits always come out looking horrible and really messy.
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Cost optimization - PCB Area vs. Double-sided load
If one has an opportunity to choose between laying out a PCB as either a single-side load (components all on one side, so it goes through reflow only once and requires only one stencil) or a double-...
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Can Altium do via stitch patterns when interactive routing a group?
I am currently only able to route a group to the next layer with a line of via's like below:
I would like to be able to route them something like this:
It would really save space but it takes a ...
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Controlled impedance in presence of vias and through-hole components (PTHs)
We have some controlled impedance traces on layer 4 of a board. Layer 3 is a GND plane. Layer 5 is a 3.3V plane. Both planes are unbroken (they occupy the entire layer), with the exception of vias and ...
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What is the purpose of this layout feature
I have been researching some TI power supply ICs and came across the following diagram in the datasheet for TPS40200.
Can anyone explain why the trace circled in red is connected as it is instead of ...
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Stripline reference plane discontinuity in reference design
According i.MX6 SMART DEVICE SYSTEM of freescale layout board, it uses 8 layers, my question is about the inner layers, they are striplines with a continuos GND plane in one side but in the other side ...
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Ethernet 100 ohm differential pair layout
I'm finishing off the layout of a board in Eagle which has a LAN8710A 100Mbps Ethernet PHY on it. The SMSC documentation is really pretty good but I'm stuck on the important detail of how to do the ...
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Critique of my Data logger's Power circuit design
I am laying out my first full device, a fairly simple sensor-data logger, with these specs in mind:
I'm running microcontroller and sensor @ 3.3V, with load varying from 10 mA to 400 mA
device will ...
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getting rid of little air wires in Eagle
I am just about done with a layout. But Eagle says I have 23 air wires left. It turns out they are little tiny ones, e.g. where traces overlap, like this one:
There is a tiny yellow dot where the ...
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Split ground or continuous ground
I'm trying to design a grid tie inverter.
I have designed a 4-layer PCB and I have a few questions about the layout and grounding.
I have been closely following this reference design but I'm using ...
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Why are the USB signal pins always swapped on USB bridges?
So I've been looking around for quite some time for a USB<->UART transceiver that has the pins properly ordered.
If you'll look at the picture here, you can see that the pin order of the connector ...
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Ground and power PCB layout for MCU
As you know most of the MCU's has several Vdd and Vss pins. In the case of two-layer PCB it seems convenient to use some polygons beneath MCU (like on the figure below). The first option is treat the ...
user11057
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PCB layout rules
What are the design rules that should be applied when designing a PCB layout ? I am currently using Kicad, because it is free and it is simple to use.
I made a layout for a L200 power supply. I wand ...
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I2C PCB Layout Considerations
I wanted to ask, what general layout guidelines and/or routing concerns exist for I2C in a PCB design?
Edit - Consider a 31mil thick, 4Layer PCB with stack up:
L1 = signal - 0.5oz + 1oz plating
L2 =...
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PCB layout for 8-16MHz crystal very near WiFi module AND small DC motor
I'm designing an "Internet of Things" appliance where space and layout are constrained by mechanical and cost requirements. The main processor is a PIC18 and its crystal (probably 8MHz, maybe 16) is ...
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What do 3-digit reference designators mean?
While looking at many circuit boards and schematics, I often notice that 3-digit designators are used, for example R101 instead of R1.
What do these digits actually mean? The numbers are not in ...
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Why do PCBs have big interfaces?
I am not sure if this is a good question but I am curious. Consider the following PCB:
I have realized that although the lines leaving the IC in the middle start fairly close to each other, they are ...
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Do I need a decoupling cap for ICs that do not switch very fast?
I am designing a space and cost constrained layout. On it I have two analog muxes (ADG719 (datasheet) or similar.) Both switch states a maximum of two times a second. They do carry video signals with ...
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Learning PCB Layout Strategy
A number of projects I have been working on have outgrown the breadboard phase, and I have been learning how to do PCB layout. My first tiny project (a cable adapter) went smoothly, but as I have ...
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Can a trace connect to a pad on the top layer?
I'm making my first two layer PCB and have am unsure of whether it's ok to connect a trace to a pad on the top layer (if the pad is on the bottom layer, that is). Here's a picture to show what I'm ...
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What precautions should I take when mixing analog audio and digital on the same board?
What precautions should I take when mixing analog audio and digital (uC control) on the same board? I don't want to hear the I2C bus in my speakers. I'm thinking about
Separate power supplies ...
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Through hole SMA parasitic effects
I'm designing a PCB involving signals up to 6 GHz. I want to use through-hole SMA connectors like these:
If I route the RF traces on the top of the board, will the center contact of the through-hole ...
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High DPI (4K) And EAGLE CAD
Anyone know how to make UI text and objects display larger in EAGLE CAD. I just got a laptop with a 4K display and it looks beautiful but the text in some programs is microscopic
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Signal integrity: ground plane vs ground traces between signals
I am designing a 2 layer PCB with high speed signals (200 MHz range) AND 4 layer PCB is NOT an option. Which of the following would be a better scenario for signal integrity, and if possible, explain ...
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Off-center via-in-pad
I am designing a board for a 0.8 mm pitch large BGA component. I will be using via-in-pad. There are some differential pairs that need to escape the pin field. The smallest my board house can do (...
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PCB layout review: ground layout for CC step down converter
I'm laying out a step down converter based on the ST L5973AD being used in constant-current layout to drive LEDs, per Application note 2823.
My previous question was what is the datasheet telling us ...
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Better single via with long GND path or multiple vias with short GND path?
I want to ask if it's preferable to have a single via that connects multiple decoupling caps and components to a single point of main GND plane, like in this image: (of course all will be filled with ...
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Polygons pours under BGAs?
Is it a good practice to put polygon pours on the top layer underneath a BGA?
I've occasionally got several GND or VCC pins in a row/column, and I'd like to pour around them all. I've got the same ...
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What does "strap" mean in this context?
This is one common error in layout IC. What does "strap" mean in this context?
LUP.6 { @ Any point inside NMOS source/drain space to the nearest PW
STRAP in the same PW <= 30 um @ Any ...
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Unused area on layout
I have prepared the following PCB layout
I am a hobbyist and when I look at other - professional - boards, mine looks a little strange when considering the empty spaces to the right, and to a lesser ...
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PCB Layout - Ground Plane Return Path
I am designing a 4 layer PCB with power planes and a ground plane, with mixed voltage signals and high currents. I have two possible isolated ground plane configurations, and I am wondering which ...
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Altium PCB Layout: The Difference of Through Via, Micro Via, and Burried Via
This is my very first time doing 4 layers PCB layout.
What is actually the difference between Micro Via and Buried Via?
Say I have Layer 1, Layer 2, Layer 3, Layer 4. What I know I use the Through ...
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Placement of two independent crystals
This one is completely about PCB layout. I have two 26MHz crystals in the design, one for each processor on the board (TXC
7M-26.000MEEQ-T, datasheet: http://www.txccrystal.com/images/pdf/number-...
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Routing Digital Signals to an Analog Circuit
I'm working in a mixed (analog and digital) PCB layout where I need to route some tracks from digital to analog ground area. They are general I/Os signals to control MOSFETs and clocks/data signals (...
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Placement of undervoltage monitor and cutoff
Suppose I have a circuit running at 3.30V, supplied via an LDO regulator (e.g., ADP124), powered by a Li-ion battery. In other words:
Now, I would like to implement an undervoltage cutoff to "turn ...
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Use of internal PCB ground plane as ESD baseplate/EMC reference plane of product in plastic enclosure
I am designing an electronic product which will be housed in a plastic (non-conductive) enclosure. There are a number of, mostly shielded, I/O cables (Copper 10/100/1000Mb/s Ethernet, USB 2.0, RS232, ...
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What is a switching node island?
I was reading the LM2734Z datasheet and in the PCB Layout Considerations section, it says "There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching ...
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Analog Video PCB Layout
What special considerations and/or constraints are typically applied when routing analog video signals on a PCB (e.g. VGA, NTSC, etc). I'm thinking try and keep them routed on a single layer (i.e. at ...
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Why would a wireless smart card antenna have one larger loop and three smaller loops instead of four similar size loops?
This image is originally from here. I added some annotations. The picture shows an x-ray shot of a smart card with wireless capability (and also a contact pad for direct connection to a terminal).
...
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What is the purpose of irregularly shaped SMD pads?
Looking at a this buttons recommended footprint, I found these irregularly shaped pads:
The protrusions from the pads are way to small to act as solder thieves, and the button itself has gull wing ...
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Bypass caps under BGA: Should I isolate vias from planes?
I'm placing bypass capacitors underneath a BGA package. In some cases the caps cannot land directly on the vias-in-pad ("VIP"), so I'll need short traces from the VIPs to the caps:
In this example ...
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First DDR2 Layout - How much of a data lane must have the same reference?
Doing my first DDR2 layout and I'm hitting some conflicting requirements.
I have dogbones to an internal ground-referenced layer, and then short top layer traces at the other end going from the ...
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