Questions tagged [libero]

Libero is the software for the design of Actel (Microsemi) FPGAs.

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Top-level HDL File with Libero SOC

I'm using Libero SOC for the first time. I've used Quartus and Vivado before. I notice in the tutorials ways to use the graphical "Smart Design" file type as a top level module. But I can't ...
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Libero does synthesis again before programming the device

I am using a ProASIC3E PQ208 FPGA and Libero tool to write the vhdl code and program the board on which the FPGA is soldered. When I try to open Libero again to program file, it starts the synthesis ...
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Microsemi Libero tool version shell command

Is there any shell script command for getting the libero tool version ? I want that shell script command. As far as I know, libero tools have get_libero_release command for getting the tool version ...
Niranjan Nimgaonkar's user avatar
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Smartfusion2 Programmer Error

I have recently start using the M2S150 Development kit from Microsemi and have run into an issue when attempting to program the board (via Libero 12.1). When running the "Run PROGRAM Action" ...
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Is using floor plan tool during FPGA design ever actually useful or required?

I have used Intel Quartus and Microsemi Libero. Both of these tools contain a method whereby we are able to view the floorplan of the FPGA, hover the mouse around to see what parts of netlist have ...
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Why do FPGA projects always take the same amount of time to compile?

With software, when we compile the project for first time it may take a while but afterwards, it does not take so long anymore. If we change a single file in the project, everything does not need to ...
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How to use "AND" statement in Verilog

I am trying to create a counter that starts counting when a start signal goes from 0 to 1. Then, I want the counter to keep counting until both the start and stop signal are 1. Once both signals are 1 ...
yer's user avatar
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Trying to measure a pulse width and then send pulse of same width using Verilog [closed]

I am trying to write Verilog code which will measure the width of a pulse and then send a return pulse which has the same width. So far, I have created a counter which counts the number of periods ...
yer's user avatar
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Using a counter to count how many clock cycles a signal is high using Verilog

I want to use a counter to count how many clock cycles an input signal is high. The issue I am running into is that once the input signal returns back to zero, my counter resets which causes my output ...
yer's user avatar
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ModelSim does not run until "$stop" command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
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How do I use command line to compile Libero SoC projects?

I want to use a shell script to compile my Libero projects. How can this be achieved? If anyone has done it, please let me know. The documentation from Libero is not very helpful at all.
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Why is my 8-bit counter only counting until 127?

I recently coded an 8-bit counter in Libero and simulated it in ModelSim using Verilog. When I simulated my design, it only went up to 127. Shouldn't an 8-bit counter go up to 255? Here is my HDL Code:...
yer's user avatar
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Is Microsemi Libero supposed to have many arithmetic cores inside its catalogue?

Here is a screenshot of the Libero catalogue tab in my machine. I am using Libero 11.9. There are only 3 design blocks which frankly are trivial. There is no divider, no floating point maths blocks, ...
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Is there a Quartus Signal Tap II equivalent for the Microsemi Libero SoC?

Quartus Signal Tap is extremely beneficial in debugging complex problems. However, there is no such toolset in the Microsemi Libero SmartDebug toolset. I would expect that Microsemi does provide ...
quantum231's user avatar
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Can items in Microsemi Libero SmartDesign canvas be rotated?

I am sure there is a way to rotate or flip the things we put into the canvas of the Microsemi Libero SmartDesign Canvas but it is not clear how to do this.
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Why are VHDL "external names" that are used to create alias to signal at another level of hierarchy, not synthesizeable?

I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error: Error (10500): VHDL syntax ...
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What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
quantum231's user avatar
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Force LiberoSOC to particular FCCC?

In the IGLOO2 FPGA, I know there are several FCCC available for use. As best I can tell, which one is used is picked at synthesis. Is it possible to force the LiberoSOC tools to use a particular FCCC ...
Drew's user avatar
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0 definitions of operator "*" match here for signed type (numeric_std, VHDL)

I'm writing a package to add supporting functions and types for creating an FIR filter. In the mult function, I'm trying to multiply two signed types, which should ...
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Gate-level design with a Smartfusion2

I am working with a SmartFusion2 FPGA, and I am trying to implement a fine delay line. For that, I would like to control exactly the content of some LUTs, to get cells with no logic properties but ...
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TCL command in Libero SOC [Microsemi] to generate the IP cores

Does anybody knows the TCL command to generate the IP cores in a design for the Libero Soc tool of Microsemi (v11.4 SP1)? So the IP core (e.g. a FIFO) is configured and in the design. However, the ...
vermaete's user avatar
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What are the various files types in Actel (Microsemi) Libero?

While researching What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?, I found about various files types. But not all are defined in the Libero SoC or Design Constraints, ...
Brian Carlton's user avatar