Questions tagged [logic-gates]

Symbolic representation of ideal devices implementing boolean functions

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What's the problem with this four-transistors XOR gate?

I aimed to design a XOR gate using as few transistors as possible. Eventually, I came up with this: Designed and simulated here. The two terminals on the left are inputs, where the "low" ...
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"Tiny " XOR gate simulation not working

I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at ...
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supplying logic 1 or 0 to logic gates & pull-up/down resistor values

I need to supply logic 1 or 0 (selected by a DIP switch) to NAND gates. Input 'A' & 'B' are inverted to each other. My Question: 1: Is the below circuit okay or its better to use inverter IC on A ...
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Logic Circuit - Integrated circuit to omit one pulse over two

I am trying to make a simple circuit to control two MOSFETs with only one PWM generator. I would like to send the red waveform to the PWM generator and I would like that after a simple circuit the ...
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Transistor Not Entering in Cutoff region

I have made these circuits (DTL or TTL). And I want to enter these transistors (T1, T2, T3) in the cutoff region. But I am not able to do so. Which parameter I have to change so these transistors ...
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Delay of ripple carry adder

I denote delay timing as "@ value". As you can see the picture above, C_in0(carry in 0), A0(input A's 0th bit), and B0 are initially ready so there is no delay which means they all have @0 ...
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Speed of electrical NOT gate

How fast could a NOT gate theoretically work? Like minimal size and maximal transfer speed (I don't know if this would be lightspeed or not)? It's because I'm researching Domain-wall logic and want to ...
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Turn on switches sequentially - ONLY ONCE - when triggered

I have some circuits in which I have to give two signals (I mean signals as positive) through push buttons to do some work like latch, and it is the only work of these buttons. I feel that this should ...
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Minimizing number of logic gates

For a boolean function, after drawing K-map we got that function in the form of the sum of products (minimal representation) but problem is that when we implement that minimal representation we use ...
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Why do logic gates need multiple MOSFETs?

I've just started learning about physics and electronics, and right now I'm learning about creating logic gates with CMOSFETs (Complementary MOSFETs). I'm interested in this because I'm a "high-...
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Why is current flowing through the transistor though the base is off?

What could be wrong in this circuit? I'm new so I'm still figuring it out. I assume it's because I don't have a resistor placed at the emitter. I did that on purpose because I'm just testing it out. ...
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"Double-pumped" flip-flop?

As of this moment, does anybody make a single-chip flip-flop that latches its state on BOTH the falling AND rising edges of a clock? In other words, instead of latching an input's state and setting ...
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NEC asic information from around 1990

I'm looking for datasheets with specification for the NEC ASIC/Gate Arrays from around 1990. More preciselly, any information with specifications of their ASIC/Gate Array lines. I would like to known ...
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How can I combine 4 separate bits into one 4 bit output?

Say I hypothetically have four switches 0-3. I want each switch to represent a bit in a four bit long number, switch 0 being the first bit and switch 3 being the last. The end goal is to be able to ...
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Parallel several inputs of a multi-input gate

Often I see the following circuit (example 1.), e.g. using an additional gate of an NAND gate to invert a signal when using only one 74xx00 CMOS IC with 4 x 2-NAND gates: simulate this circuit –...
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What's the difference between these two logic diagrams?

I have these two xor logic diagrams, they seem to work the same on inputs which are not even, but what is the difference between them? What is the purpose of it and which one would be faster?
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TinkerCAD 7-Segment Display Not Showing on Simulation

I am only on my 5th week trying out TinkerCAD for our Logic Circuits course. We are tasked to create a 7-Segment Display Using Logic Gates only. I did all the boolean expressions needed for each ...
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Convert boolean expression to nand gate only. X = A'B'C+AB'C'+A'B'

I have already made a diagram. However, it won't match the truth table that I have made, which I got from the logic converter in multisim. Could you please help me out with where did I go wrong? Is it ...
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How do you go from gate level to transistor level?

Is there a good method to go from circuit at gate level or truth table to transistor level, other than trial and error? I have an example here to illustate what I am asking. We have the function \$X=(...
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What is the best way to make an inverter from a NAND or NOR?

As stated in this answer, there are two ways to make an inverter out of a NAND gate, and similarly for NOR: Connect the signal to both inputs. Connect the signal to one of the inputs, and the other ...
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How to build boolean expression from these logic gates [closed]

I have these xor logic gates and I want to create a truth table from it. However I am having issue reading it from logic gate. Could anyone show me a minimal ...
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How to determine if a gate/inverter can drive a fanout of 4 gates?

I have a circuit in which a driving inverter output (Fanout of 4) with equal Wn Wp sizing (m=4) is driving 4 other gates having same equal Wn Wp sizing (m=1). How to calculate if the inverter fanout ...
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How to make a D flip flop circuit that pulses 4 times per switch toggle?

For a school project we must design an ALU and its control circuit (see schematic). As part of the controller, we must make a circuit that clocks our registers (one is PISO, the other SIPO). The ...
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Prime implicant and essential prime implicant problem

Hello I had a question in my exam that asks how many prime implicants and essential prime implicant with this k-map below. I tried it and it's came with me 6 essential prime and also 6 prime. I got ...
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Is it necessary to take into account the actual state of a combinational circuit's signals to calculate its maximum delay?

I'm doing an exercise in which I need to calculate the maximum delay of a 1-bit full adder. In a full adder, the slowest path is the carry_out. Here is how I have designed it: Let's suppose all gates ...
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Is there a way of converting easily binary numbers to its ASCII equivalent?

I have this digital circuit design problem where we receive two two-digits numbers in ASCII, I have to convert them to binary, add them, and the result I have to encode it to ASCII again. I actually ...
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Implementing boolean operations using decoders

Is it possible to implement boolean operation gates such as AND, OR NAND, etc. by using decoders? Further, is it possible to implement n-input AND, OR gates using decoders?
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1-bit Full Adder is a universal gate, like NAND gate? [closed]

I want to know if a 1-bit Full Adder can be considered a universal gate.
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How to invert a NAND gate IC and have it work like an AND gate IC?

I have created this circuit design using tinkercad. I thought I had two 74HC08 IC:s. Turns out I only have one. Can I replace the second 74HC08 with an inverted 74HC00 and if so how do I do this? If ...
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Unclocked NOR gate SR latch not latching [closed]

I am starting to learn computer architecture and decided to try building an SR latch using NOR gates and without a clock (basically copying this video) on a breadboard. My circuit is pictured, it is ...
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What does a chip's propagation delay vary on?

When looking up datasheets on logic gates, propagation delay is usually shown as a range. Sometimes there's a "typical" value in the middle, but there's a min and max listed. On what does ...
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How can I make a 7-segment display driver immune to intermediary states using basic logic gates (where each gate has a 1hz refresh rate)?

How can I make a hexadecimal 7-segment display driver immune to intermediary states using basic logic gates (where each gate has a 1hz refresh rate)? The problem I'm running into is that on the first ...
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How does Virtual I/O Core work in Vivado?

I've recently started to learn programming in Verilog by using Vivado simulator and I noticed that the testing/checking part of your Block Design plays a very important role in obtaining the final ...
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If two Boolean functions \$f_1\$ and \$f_2\$ have same truth table, does that means they have exactly same characteristic? can one f1 numerate to f2?

if \$f_1(x,y,z)=\neg xz+x\neg y+\neg xy\neg z+xy\neg z\$ determine if \$f_1\$ is symmetric and whether it is unate. What I thought is: \$f_1\$=¬xz+x¬y+y¬z, the truth table of \$f_1\$ has the same ...
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Is there any source of gate counts for components of a modern processor? Specifically looking for AVX2 implementation

I just wrote a simulation of a SIMD unit based on my perceptions of the weaknesses in AVX2, but while the system can generate the underlying gates and have estimates of the cost in silicon of each ...
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Preset data inputs at 74HC163

After looking at datasheet for 74HC/T163 devices from Nexperia, I have some doubts regarding the input D3-0 pins of the device. If you follow the logic from these inputs (logic diagram at page 3), at ...
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Line follower robot using only NAND gates

I'm stuck on this and would appreciate some pointers. So for class I have to figure out the logic for a line follower robot using at maximum 8 NAND gates (two 74HC00 Quad NAND ICs). The robot has ...
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Logic Gates using only conductive material

Is it possible to build logic gates (at least only OR, AND gates) by just using electric wires and resistors with no semi conductors (no diodes, no transistor or any other semi conductor material or ...
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How to understand this combinational cyclic circuit made of interconnected SR latches?

I'm trying to understand the following circuit, or better said, what must be the approach to analyze other similar ones: What I'm doing for now is forget about the clock signal and the ...
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Equivalent of multiple emitter transistor using regular one emitter NPN BJT transistor

I want make a simple NAND gate using transistors with transistor-transistor-logic aka (TTL). I saw on tge Internet (Wikipedia) that it requires two emitters as inputs. Source: https://id.m.wikipedia....
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CMOS logic gates | Number of Logic Gates issue

I came across this question for CMOS logic gates: Question - "Draw the schematic diagrams for CMOS logic-based implementations of f = a(b + c) + bc. Use minimum number of gates. Assume that all ...
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Frequency of a ring oscillator using transistors only

This is the standard design of a NOT gate without much sophistication: I've used R1 = 1k \$ \Omega \$ and R2 = 100k \$ \Omega \$. The transistor model I use is BC107B. In an attempt to create a seven-...
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Is it possible to get this truth table working using only 2 gates?

Is it possible to get the following truth table to work using only 2 logic gates? W and CHS are inputs, and S and R are outputs. W CHS S R 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 Basically, I'm trying ...
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RTL to Gate Level Design - Verilog

I have written the following code for sinc3 flter in verilog (Vivado). I need to ask how shall I now convert this RTL design to a logic Gate level design in verilog (add AND, NOR, flip flops, etc.)? ...
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Creating only NAND/NOT circuit from POS expression [closed]

I created Product Of Sum (POS) expression using a Karnaugh map, and now i have to create its circuit using only NAND and NOT gates. At the start, I created this circuit based on OR and AND gates: ...
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Analog mux with active low enable.I/P and O/P state when enable is High

I am using this mux (74LV4051D,118)from Nxperia for one of my applications.The functional table is given below. When the Enable is High S0, S1, S2 are don't care, and the switch is off. May I know ...
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What is the simplest possible (as in fewest logic gates) 4-bit by 4-bit binary multiplier?

I am working on a science fair project, where I am 3d printing a calculator, using water as bits. I have hit a roadblock with my multiplier, however, as my current design uses an absurd amount of ...
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Are the following boolean expressions correct according to De Morgan's laws?

Are the below boolean expressions correct according to De Morgan's laws? I am trying to realise a three input NOR gate using a four input NOR gate, but I suspect I did a wrong transform. \$\:\:\:y=\...
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NAND circuit from boolean expression

What is the best way to convert following boolean expression to circuit based only on NOT, NAND gates? I already done OR, AND circuit. But what is the method to receive that?
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Is it possible to make a XNOR gate only with diodes without using a transistor?

I created almost all logic gates with diodes and resistors NOT, OR, NOR, AND, NAND, XOR but i have problems with XNOR and i doubt if it is even possible. I found one but this using a transistor, so my ...
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