Questions tagged [logic-gates]
Symbolic representation of ideal devices implementing boolean functions
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Why are there no single logic gates in through-hole packages?
If I'm not mistaken, single logic gates (i.e. a single NOT, OR, NOR, AND, NAND, XOR, etc.) do not exist (anymore?) in through-hole packages.
At least, on Digikey, when searching for active in-stock ...
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D latch: understanding its practical design
I know that a D latch is built by using an SR latch, but I am interested in understanding the practical reasons.
Logically the D latch can be described by \$Q = \text{clock} \land D \lor \lnot\text{...
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Why do both of these logic gate designs for an OR gate from NANDs work?
I was fiddling around with logic gate designs because I'm self-educating myself about electronic circuits and as a programmer the logic gate aspect intrigued me. I came across the simple "task&...
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One BJT NOR gate resistor values [duplicate]
What is the purpose of this RD resistor and how do I calculate all the values in this one bjt NOR circuit to have something reliable. And how do I measure fanout of this gate?
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NAND gate with two vs. one BJT transistor(s)
Why is everybody discourage from this paired NAND BJT Transistor "design"? I already saw a few posts where somebody asked something about the paired BJT NAND "design" and the ...
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AND gate in Verilog high-Z output
I implemented an AND gate with Verilog, but the waveform keeps showing high-Z on the output (t1 and t2 are OK, but the others ...
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Can the output of a logic gate be split to serve as input for other logic gates?
In the textbook picture, they use 5 NOT gates, repeatedly splitting the R input only to have it go into a different NOT gate. Are you allowed to put the input of R into a single NOT gate, and split ...
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Similarity in "carry and sum" and "difference and borrow"
i know carry and sum from all the sources i studied in YT (particularly KNOWLEDGE GATE) except neso academy that teaches using difference and borrow in same place as carry and sum
Sources:-
Knowledge ...
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Chaining NAND gates does not work and results in wrong simulation with LTspice
I started building basic logic gates. I wanted to start basic and understandable so I started building some NAND gates just using two transistors. On its own hooked up to a switch and a LED they work ...
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Using watchdog to control load switch with STM32
I want to use STM32 and Watchdog to Loadswitch device that controls some other load(INTERLOCK).
The way I want to implement it if the STM gets stuck in a certain state (when not toggling the WDI)
the ...
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CD4059 behavior with invalid jam inputs
I am currently working on a circuit for a electronic synth module that should function as a random clock generator. My idea is to use a high frequency clock (relatively speaking for musical ...
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Does taking dual of a boolean expression also result in its complement?
I was revisiting XOR and XNOR and the form of their different equations.
XOR = A ⊕ B = A'B + AB'
I took the dual of it:
Dual of XOR
= (A'+B) (A + B')
= AA' + AB + A'B' + BB'
= AB + A'B'
This is ...
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What is a simple explanation of a NOT gate circuitry that fits with the binary representation?
How is it that a NOT gate sets the output voltage based on the input voltage?
Is it possible to get a simple, maybe diagramatic, explanation of this?
For example, in the "transistor switch" ...
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Logic gate: electricity, voltage and meaning [duplicate]
I am confused by this kind of diagram (simplest, NOT gate):
------1------___Gate Here___-------0--------
Because my book tends to talk about electricity.
So if I ...
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How does a 0 as a binary input work if it is given by off?
In electronic circuits, for binary operations we use on as 1 and off as 0. Like in the data transmitted through fiber optic cables is sent using light going on and off. How can an output be generated ...
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Why does the 74LS08 see an input logic level even if the inputs are not connected?
I have an 74LS08 (AND gate.) I did not connect any inputs to the IC, but it gives me voltage at the outputs. Should I separate VSS?
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How to generate a single pulse for certain milliseconds or second without microcontroller?
I'm using an IR sensor as an input and I want that when IR sensor (A) goes high, then a single 300-ms pulse is generated at (B), such that even if (A) stays high, it doesn't generate any other signal ...
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How to command several devices simultaneously from MCU?
I want to control several devices using one MCU. Each device will receive either 1V or 3V depending on the application. I want to use only 2 analog pins from the MCU to send either 1V or 3V to several ...
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Cascading counters
I'm cascading two HEF4017 counters as described in page 12 in order to drive 13 LEDs.
Instead of using a logic AND gate (cause I don't have one, and I like to use the components I already have when ...
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Ensure that cable is not disconnected from my custom board
I designed a custom board, the board includes stm32 that turns on a control voltage that operates SSR and the SSR goes to the load:
CTR comes from the GPIO of STM32.
in my custom board, there is some ...
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Is there a minimum voltage for digital logic (eg XOR) in CircuitLab?
I am trying to design an edge to glitch converter (XOR time delay) that works at 3 V.
For context: This is to wake an ESP8266 when a sensor value changes. I am fairly certain at this point that the ...
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74HC being labelled as 74LS?
Bought several tubes of 74LS00. We test the datasheet spec for VIH by sweeping one input from 0 V to 5 V while holding the other input at 5 V, and checking the output. Usually we expect to see a ...
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How does a D flip-flop stabilize?
I am trying to understand how a flip-flop stabilizes internally after setting up, before the clock starts ticking.
I assume:
An electric signal takes no time to transmit from one end of a wire to ...
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What is the internal schematic for a 74HC series gate (NAND gate as an example)?
It's rather easy to find the schematics for a CMOS NAND gate on the net -- two series NMOS transistors as the pull-down network, two parallel PMOS transistors as the pull-up network.
What would an ...
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Creating Boolean sequence using SPDT switches
I am experimenting with digital counters and for one application it would be useful to generate a set of four pairs of 3-bit values used for comparing (Cx) and resetting (Rx) a counter. Since there ...
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Why do we use an inverter at the end in CMOS AND and OR gates?
I know it is a very basic question but I couldn't really find an answer on the internet. Our lecturer told us it is used to reduce the number of transistors used in the design.
Our first case without ...
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CD4098 as an astable multivibrator
I have a bunch of unused CD4098 ICs available and I was hoping to use them in DIY-project to drive a counter (therefore duty cycle % does not matter) in astable multivibrator mode with adjustable ...
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Circuit help required - press two buttons to trigger third input using common ground fightstick board
I have a gaming fightstick which I don't want to install any additional buttons into. I need help with connection or a circuit so when I press two buttons (eg select & start), it triggers a third ...
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Unexpected voltages on home-made OR gate
I've created some home-made gates using discreet components onto strip board.
So far I have an OR gates, an AND gate and 4 NOR gates.
Logically they all work as expected but on only one of my 4 NOR ...
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(Logisim) D-flip-flop asynchronous reset not behaving as intended
I made the following 1-minute clock circuit in logisim that's supposed to count up to 59 seconds and then loop back to zero:
It works mostly fine, but the problem happens when it reaches 59 and loops ...
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Information leakage due to fault propagation in XOR gates
From the paper Fault Template Attacks on Block Ciphers Exploiting Fault Propagation, in the concept of Automatic Test Pattern Generation (ATPG), two events are required to perform in sequence: Fault ...
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How can I set time for this circuit the easiest way?
Can I do it in lab like Proteus and can I change the resistor and capacitor for the timer 555 to equal 1.023, like:
r1 = 10 kΩ
r2 = 10 kΩ
c1 = 47 μf
Is there a way without a resistor for AND gate or 7-...
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Does the 74LVC1GU04 actually have "Schmitt-trigger action" on its input?
The 74LVC1GU04 is an unbuffered inverter, which (according to the datasheet) is intended to be used in linear mode in applications, such as crystal oscillators and linear amplifiers with negative ...
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Did I create this Karnaugh map correctly?
I'm tasked with making a 4-7 decoder for a 7-segment LED (common anode).
I am an extreme layman (1st year EEE student)
I have 4 inputs (A,B,C,D)
...
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What are the considerations of using a common anode 7-segment display over a common cathode?
Common anode:
Do I need resistors here? Where would I connect them?
Common cathode:
Common anode seems simpler circuit wise - but I like the idea that "1" represents "ON" that ...
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What's the meaning of this yellow color in Proteus?
What's the meaning of this yellow color in proteus?
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Can I construct a logic AND on a "power" line
I have two 12W LED bulbs which are wired in parallel. I control them both with a MOSFET (M1.) Now I want to be able to dim one of the bulbs, but it should still only light up when the "original&...
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NOT gate output question
Newbie here with a very basic circuit question. I believe I understand how the transistor portion of the NOT gate depicted below works. What I am unclear about is why the output voltage Y changes from ...
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Is the invalid state of an SR latch also undefined?
I understand that if both the Set and Reset inputs of an SR latch are high, the output of both Q and Not-Q is low and this is considered an invalid state.
But in this situation is the output also ...
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How do I change an input from active high to a positive edge trigger? [duplicate]
know that flip flops are edge-triggered, but I'm not knowledgeable enough to know how to replicate that for my own circuits.
On a gate level, how does a pos-edge happen?
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How do I find resistors values for a TTL to ECL interface?
This is the photo of the ttl to ecl interface
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How to use the output pin of OR gate as one of its inputs?
I am trying to make a circuit using transistors that consist of an OR gate, but the output of the OR gate is used as B input.
As expected the LED should remain on as soon as an input is 1, and the ...
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Floating ttl input and ground short without pulldown
A pulldown resistor seems to always be used for configurations where when the switch is open the normal state is low.
For example
The reasons always given are to avoid a short between voltage and ...
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Solar panel as light sensor to switch a battery and LED circuit
I have a project powered by a solar panel which is supposed to charge a battery and then light up an LED only when it's dark outside. I made the initial circuit using an LDR and a potentiometer and ...
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D flip-flop circuit to show nine hex numbers alternately on one seven-segment display
I tried to make a circuit with a D flip-flop to show a hex number of F1D021301 alternately on a single seven-segment display, but it can only do F1D02130 or F1D0213 and return back to 0 and repeat to ...
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CD4018 divide by 11
I am making a circuit that creates various subdivisions of input frequency by integer values from f/2 down to f/12. Division by 2, 4, 8 are straightforward using JK flip flops. Divisions by 6, 9, 12 ...
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Which of the following input binary conditions will produce an ambiguous state in the flip flop?
For ambiguous state, both outputs x and y must be zero(for active low) to be considered invalid i.e. of both PRESET and CLR are logic "0". Now, analysing the circuit, $$ x=a \oplus D_0 $$
...
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How to find the Signal Probability equation of XOR gate with N inputs
2-input XOR gate truth table
The signal probability for a XOR gate with 2 inputs is: \$sp=(1-p_A)p_B + p_A(1-p_B)\$
3-input XOR gate truth table
The signal probability for a XOR gate with 3 inputs ...
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Implementing three-state logic
Can we build a three-state logic gate using only transistors (or basic logic gates)? If so, how is it built?
I'm trying to build a model for an 8-bit computer in LogiSim, and I'm trying to find out if ...
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For the 4x1 MUX shown below the Boolean Expression F(x,y,z) is [closed]
The output to a 4x1 MUX is : \$Y=S_1'S_0'I_0+S_1'S_0I_1+S_1S_0'I_2+S_1S_0I_3\$
My answer was : \$F=A_{1}'A_{2}'x+A_{1}'A_{2}x+A_{1}A_{2}'y+A_{1}A_{2}y' \Rightarrow xyz'+xyz+y'z\$
The correct answer is ...
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