Questions tagged [logic-gates]

Symbolic representation of ideal devices implementing boolean functions

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Is is possible to create modular logic gates from transistors for teaching purposes?

I'd like to work through some basic logic circuits with some youngsters and wanted to build them up from scratch (transistors), not logic gates if possible. We've done the basics: buffer, NOT, AND, OR,...
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1answer
43 views

“Noise” in simulator

I have been working on a simple circuit which performs XOR operation. The problem is that I am seeing a noise-like graph when both inputs are set to 1 (5V) and I have been doing a research on what it ...
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71 views

Adding a new instruction to a MIPS

heyy, I study software so i'm absolutely new when it comes to drawing electrical circuits and I need to add a new instruction to This MIPS machine here The new instruction i have to add jt - jump ...
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1answer
56 views

SR FlipFlop Question

I am studying Digital Logic Circuit right now and I have question to ask. I have searched lot of places in order to find this answer, however due to my lack of searching ability I was not able to find ...
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2answers
47 views

adder in binary addition: XOR instead of OR gate

I am just a newbie starting out in electronics with no experience. Why do we need XOR and AND gate for the binary adder? is there any particular reason why only these two specific gates are needed ...
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2answers
88 views

High Voltage OR Gate

I am currently controlling 120VAC solenoids with panel-mounted switches. Each solenoid controls the air line for a single disk brake. Now I need to incorporate an NI CompactDAQ. My boss has asked that ...
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1answer
51 views

Question On Logic Gates

In a small railway station, there are three platforms, #1, #2, #3. Up and down trains can enter in platform number #2 and #3, but platform #1 is only devoted to up trains. Design a logic circuit using ...
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1answer
34 views

4 bit adder(SN74LS283N) not working properly

simulate this circuit – Schematic created using CircuitLab Hey guys I've been trying to use a 4bit adder IC, but there are 2 main problems I've found which prevent me from using it: If power ...
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1answer
40 views

How to design a latch from a truth table

I am trying to design a latch using a truth table. The inputs to the latch are En and In. I think the circuit implementing the truth table should not change output when En is low, and output In when ...
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1answer
46 views

T Flip Flop Application

Good day all. I am trying to process two signals to produce an output signal. I will be posting a picture for clarity (sorry if I used pencil, I am stucked at home). My two input signals are sig, ...
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23 views

Finding the worst case and best case 4-bit Ripple Carry Adder

"The below diagram represents the 4-bit ripple-carry adder. In this adder, four full adders are connected in cascade. C0 is the carry input bit and it is zero always. When this input carry ‘C0’ is ...
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1answer
66 views

Control Board with simple logic

We are using an old electrical system in industry. My task is to digitalise it. As i saw, PLC is too expensive and large scale for our operation. Also, microcontroller needs programming which makes ...
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1answer
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S Bracket Transistors and Reverse Breakdown diodes in Texas Instrument 74LS32 DataSheet?

Hi, I have included the image of the schematic of the Texas Instrument 74LS32. Basically the chip consists of 4 OR gates and the schematic shows the logic how 1 of those gates is set up on the chip. ...
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1answer
38 views

design a logic circuit odd/even driver to check if a number 044 is odd or even [closed]

simulation in a multisem and steps truth table and k-map and circuit diagram of 044 design a logic circuit odd/even driver to check if a number 044 is odd or even
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T-type flip flop based on SR without additional gates?

I have a question that keeps bugging me. I know how to make a T-type flipflop from SR flipflop by using 2 additional AND gates, but I was wondering, if it is possible to create T-type from SR without ...
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1answer
80 views

Circuit Idea about 555 Timer

I have a 555 timer which outputs an enable high 500ms after power-up. So it is basically a step response at t = 500ms. I am tasked with processing this enable signal with a 20 Hz square wave signal ...
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1answer
89 views

Input and Output Impedance of a TTL NAND Gate

Basically I wanna know how to calculate the input and output impedance of this basic TTL NAND gate I have looked at several books and websites but found nothing useful , can anyone help me please. ...
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Why simple digital multiplexer uses OR gate to combine chip parts outs?

Why not just wire together outputs of the internal AND gates. For instance, consider the following Mux scheme: Here outputs of the internal AND gates are combined using out OR gate to produce output, ...
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0answers
76 views

Build a T flip-flop with enable and reset using only a JK flip-flop (without enable or reset) and some necessary logic gates

Can someone help me to check whether my answer is correct or wrong, because I am confused with some of the condition of enable and reset. I am confused if the enable is low and the reset is high, ...
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1answer
32 views

Compatibility of devices with different voltage thresholds/noise margins/static disciplines

tl;dr included at the bottom. Suppose we have two logical buffers from different logic families, where buffer A drives buffer B. Buffer A has the following voltage thresholds: \$V_{OH}=8\ V\$, \$V_{...
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1answer
52 views

What is the result of 1 and float on OR gate?

If only one input is 1 into an OR gate, the output is 1, but does that still count if there is no input from other sources? (like float) Or is the output simply float as well?
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3answers
74 views

Implement \$AB \overline{C}+\overline{BC}\$ using only a maximum of three 3-input NAND gates only

I need help with this question, I am lost.
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1answer
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Making flip-flops using logic gates in Proteus - I'm getting gray (unknown) signals

for my school project i have to use Proteus to design my circuit. My professor told us that we cannot use any flip-flops and if we had to use them we should make them by using logic gates. I'm trying ...
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1answer
45 views

Recommendations for On-Hand 74xx (and others?) ICs

I've been learning about logic gates (from Ben Eater's videos, etc.) and I find myself constantly having to order more ICs, especially 74xxs. Is there a list of ones I should keep on hand to help ...
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2answers
95 views

How to convert 8 bit binary to BCD using logical gates on multisim?

I have a task to convert analogue signal to digital on multisim. But multisim have no Ic to convert 8 bit binary to BCD. Now I have to make logic circuits to convert 8 bit binary to bcd. I have used ...
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4answers
91 views

Logic design for 27 inputs

I have 27 inputs on a pcb. I need to build a circuit on this pcb that checks if only one of these inputs is high. So more than one input high is not allowed. What is the best way to make this ...
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24 views

Temperature Effect on Schmitt Trigger Threshold Levels

I have found minimal information on the internet, as well as in multiple data sheets I have looked at. I'm designing for a large temperature range of 150°C. I require a fairly consistent voltage ...
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5answers
85 views

Validation of data in electronics

Suppose, I have data which is stored in some EEPROM memory. The EEPROM is connected via an I2C interface to a microcontroller, and this microcontroller is connected to an RF receiver circuit. Assume ...
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3answers
42 views

Understanding flow of current from diagram using AND gate

I have a question about current flow in the diagrams below, which are from my textbook. I'm in a class called "digital logic" and we are using a zyBooks.com textbook, and it's HORRID, and we are ...
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4answers
91 views

Is it possible to build an AND gate from a NOT gate?

I'm reading through an old physics book and the author is speculating how could he build logic gates using black holes. Taking aside the "black holes" thing, I have stumbled upon his ...
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1answer
46 views

Why does my synchronous up counter count enable not function properly?

I have designed a simple 4-bit synchronous up-counter, using master/slave JK flip flops in Logisim. Here is my JK design: And my counter design: It works perfectly as intended, however if the INC (...
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1answer
56 views

Open collector and open drain logical gates

Can somebody explain what open collector and open drain mean? I'm a CS student, and I'm really a newbie in terms of electronics and I only managed to find some "expert level" explanations, which I ...
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1answer
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Two SR latch implementations and De Morgan's rule

Here, I modify the encapsulated area of an SR latch(with NOR gates). The encapsulated area on the first circuit(with the NORs) is equal(at least, I think so) to the wider encapsulated area in the ...
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4answers
1k views

The difference between these two D latch circuits

I simulated both ones and could not see any difference in functionality. So, what is the need for that extra NOT gate? When it is preferred?
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4answers
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What is meant by 'On-chip 2-cycle Multiplier' for AVR microcontroller?

While checking the datasheet of ATMEGA 32 I have found a feature called 'On-chip 2-cycle Multiplier'. Can anyone explain to me what's that and what's the advantage of it?
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How to achieve this logic function simply?

I need logic gate that behaves like this: A=1, B=1, Y=1 A=0, B=0, Y=1 A=0, B=1, Y=1 A=1, B=0, Y=0 The tricky part is (A=1, B=0, Y=0) while (A=0, B=1, Y=1), AFAIK no logic gate distinquish between ...
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2answers
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I am looking for a 40 input OR gate which minimize PCB space

I am using 40x ICs INA301 to measure overcurrent in 40 interfaces Finally I want to have 1 single "output" to signal if there is an overcurrent in ANY of the 40 interfaces I don't want to utilize any ...
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1answer
57 views

Logic Gate's Scheme

I have a logic gate function like this : (A+B)•A+(A’•C) but i dont understand how to make the logic gate scheme based on that function, can anyone help me ? I'm sorry if my English is bad. thank's ...
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1answer
61 views

VTC of Pass Transistor AND gate in LTSPICE

I am trying to plot the voltage transfer characteristic of this pass-transistor AND gate in Ltspice in order to obtain the following graph: However, when I tried to do it, I did not obtain the ...
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1answer
43 views

I search a PNP array IC [closed]

i have a print where i need like 8 PNP transistors. They are all connected the same: The Emitter is connected to VCC, the Base is connected to a GPIO and a Pullup and the Collector is connected to ...
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0answers
47 views

How do I implement a Barrel Shifter?

I'm using Multimedia logic for this particular assignment, I am to implement an ALU that performs Bitwise Rotation on the input from "A" by the amount defined by "B". Not quite sure how to approach ...
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2answers
45 views

SN74LS26 2-input NAND gate. No output

I purchased SN74LS26N quadruple 2-input NAND Gates chips for my circuit. Before I insert any chip into circuit I test it on separate breadboard. So I did with this chip and I get NO output when my ...
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1answer
38 views

Why do we reset/clear at 1010 (10) when designing a BCD Ripple Counter

Shouldn't we reset at 9, I believe that a decade counter goes as follows '0->1->2->3...->8->9->0" or at least that's how its done for synchronous BCD counters.
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1answer
47 views

What happens when you nand the same input?

I am trying to conceptually understand what happens to the output of the second nand gate when input into the 1st nand gate are combinations 00, 01, 10, 11.
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84 views

Logic network with NAND gates [closed]

I did a logic network with only NAND gates to function below: and my logic newtork Is it correct?
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1answer
41 views

Process function to NAND and use only negative conjunction functions

I have a system built only NAND implementing this function. I have to process this function using only De Morgan's law and finally get only negation conjuction functions. I did it but I'm not sure ...
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114 views

Task:Design a“Disinfection Chamber”. Solved it using s-r latches. However, since it was not taught, it was not allowed. How to solve this without it?

Here is my design: I was asked to design a digital circuit of "Disinfection Chamber" (Below). I solved it using 2 s-r flip-flop. But apparently, I can't use flip-flop because it hasn't been taught. ...
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2answers
81 views

Why is the last carry block's gate in a full adder an OR gate (and not a XOR)?

It seems that a half adder (there are 2 inside a full adder) can't output both HIGH values for sum and carry, it's either Sum is 1 and Carry is 0 or the inverse. It's never Sum = 1 and Carry = 1. To ...
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1answer
94 views

Having trouble with determining why my XNOR transistor circuit is not behaving

this is my first post. I've been working on creating logic gates from 2N2222 transistors. I've build a basic switch, NOT Gate, OR, NOR, AND, NAND, and XOR (from a combination of the others). However, ...
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1answer
42 views

Having trouble with deriving the state diagram for an exam problem

The Problem: Derive the state diagram for a circuit that takes one input, A and gives out one output X, X is to be one, if and only if it detects a sequence "101" in A. Understanding The problem: if ...

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