Questions tagged [logic-gates]

Symbolic representation of ideal devices implementing boolean functions

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Why are there different types of flip-flops (D,JK,T)? [closed]

Is there any practical reason for having more than one type? Isn't it easier to just use D flip-flops for sake of simplicity?
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Frequency of a ring oscillator using transistors only

This is the standard design of a NOT gate without much sophistication: I've used R1 = 1k \$ \Omega \$ and R2 = 100k \$ \Omega \$. The transistor model I use is BC107B. In an attempt to create a seven-...
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Is it possible to get this truth table working using only 2 gates?

Is it possible to get the following truth table to work using only 2 logic gates? W and CHS are inputs, and S and R are outputs. W CHS S R 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 Basically, I'm trying ...
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1answer
68 views

RTL to Gate Level Design - Verilog

I have written the following code for sinc3 flter in verilog (Vivado). I need to ask how shall I now convert this RTL design to a logic Gate level design in verilog (add AND, NOR, flip flops, etc.)? ...
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51 views

Creating only NAND/NOT circuit from POS expression

I created Product Of Sum (POS) expression using a Karnaugh map, and now i have to create its circuit using only NAND and NOT gates. At the start, I created this circuit based on OR and AND gates: ...
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2answers
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Analog mux with active low enable.I/P and O/P state when enable is High

I am using this mux (74LV4051D,118)from Nxperia for one of my applications.The functional table is given below. When the Enable is High S0, S1, S2 are don't care, and the switch is off. May I know ...
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What is the simplest possible (as in fewest logic gates) 4-bit by 4-bit binary multiplier?

I am working on a science fair project, where I am 3d printing a calculator, using water as bits. I have hit a roadblock with my multiplier, however, as my current design uses an absurd amount of ...
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1answer
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Are the following boolean expressions correct according to De Morgan's laws?

Are the below boolean expressions correct according to De Morgan's laws? I am trying to realise a three input NOR gate using a four input NOR gate, but I suspect I did a wrong transform. \$\:\:\:y=\...
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Realize function to only NAND/NOT circuit [duplicate]

I tried to implement the function y=x4!x5 using only NAND and NOT gates, but I got one NAND and NOR gate. How to transform the above function to obtain the gates ...
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Does anyone knows what a 8421 adder circuit and what its used for?

We are learning different types of logic gates then we come across an application of it which are full adder and half adder. After constructing it using logic gates we are tasked to construct an 8421 ...
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NAND circuit from boolean expression

What is the best way to convert following boolean expression to circuit based only on NOT, NAND gates? I already done OR, AND circuit. But what is the method to receive that?
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Why are NAND gates used in a digital decoder instead of AND gates? [duplicate]

Why are NAND gates used to build a 2 to 4 decoder? Why not AND? What are all the reasons for it? How is it more economical? How it is not possible to construct it with AND gates. Why would I want ...
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105 views

Is it possible to make a XNOR gate only with diodes without using a transistor?

I created almost all logic gates with diodes and resistors NOT, OR, NOR, AND, NAND, XOR but i have problems with XNOR and i doubt if it is even possible. I found one but this using a transistor, so my ...
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2answers
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Why are the resistors compulsory in this circuit? [duplicate]

When I use resistors, my circuit is working fine but if I remove them, then the LEDs in my circuit don't work anymore. As seen here the switch just sends high (red) voltage ahead Can you please ...
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1answer
96 views

What does this circuit do? (flip flop) [closed]

I am trying to understand a circuit which does two arithmetic operations of 5-bit words in 2 cycles: Q = 2*Q - A (one cycle) Q = 11*Q (two cycles) What does this part do? This is the whole circuit:
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Tying open-collector outputs to TTL inputs

I know that open collector outputs are effectively either 0 V or high-Z. I also know that TTL chips tend to read a disconnected output as high, but that really you should have something like a 1 kΩ ...
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3answers
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Why does the TTL NAND gate use a 4 transistor design instead of 2?

Why does the TTL NAND gate use 4 BJTs to make the gate when it could be done using only 2? I assume that the design with the 4 transistors amplifies the current so multiple levels of gates can be ...
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2answers
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Counter using only basic logic gates

I'm trying to make a counter (0 > 9) using only basic logic gates , I used the master slave jk flip flop and it work fine except that I don't know how to make it reset to 0 again after 9.
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1answer
403 views

Do I need to add buffers when creating a 3-input NAND gate from 2-input NANDS because of propagation delays?

I'm seeing that a 3-input NAND gate is made up of 3 2-input NANDS. However, the first 2 input has to go through 3 levels of gates, while the third input only need to go through 1-level of gate In ...
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6answers
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My Professor and I are debating about absorption law

So the question is \$(w+y)(wz+wz')wy+y\$ and this is my answer by absorption law where \$A+AB=A\$: $$ (w+y)(wz+wz!)w y + y\\ B A + A $$ So the answer is \$A=y\$. My professor said I ...
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How to calculate RC values according to threshold points of a Schmitt trigger inverting oscillator [updated]

I'm trying to make a high-period, low duty cycle signal to trigger a regulator (EN pin) for lower power consumption. I tried to simulate this simple circuit in various simulation software, using "...
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3answers
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Intuition for building OR gate from NAND gates

The problem was to build an OR gate from NAND gates. I managed to do this in a kind of brute-force way just trying different variations, and finally got it but am feeling unsatisfied since I don't ...
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1answer
89 views

Working out which logic gates need to go where

I have something as below featuring XOR, AND, OR, XNOR, NAND and NOR gates. I have to get the bottom 3 outputs set to 1. As you can see, I've managed to do it as below but was wondering out of the 720 ...
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What is the mistake in this combinational logic circuit diagram?

I am trying to represent the combinational logic circuit to perform 5x3 multiplier operation using 1-bit full adder using CSEDAR Simulator, the label is based on this operations: My answer is as ...
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1answer
60 views

Where do Logic Gates Get the First 0 or 1?

I've been thinking about playing around with some logic gates on breadboards... But where do I get the first 0 or 1? I could use a regulator,but is there a better solution? or would a logic gate just ...
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1answer
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Alternatives to FSM in VHDL?

I want to design a UART using logic gates but I don't know if is there any alternatives to Finite State Machine. Coding a UART in VHDL using FSM is really easy and abstract, the programmer doesn't ...
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Minimize the switching function from Karnaugh map

I need to minimize the switching function y=f(x1,...,x5) represented by the Karnaugh map. I wonder if I did it in the right way. Can anyone check this?
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2answers
72 views

How do you make a three two-input and gates function as four-input and gate

I'm having a hard time trying to recreate this logic. I used the output of my two and gates connected to another AND gate will that work? or is there any better solution to this problem?
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1answer
68 views

Frequency of a sequential circuit

I'm reading the book Digital Design and Computer Architecture. I came across this exercise: From what I've learned so far, the frequency of a circuit is the reciprocal of the clock period. Since we ...
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Confused about positive edge-triggered D flip-flop

I'm reading the book Digital Design and Computer Architecture. I don't understand this passage: This is a D flip-flop with active low asynchronous set and reset inputs. If S' and R' are both 1, the ...
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1answer
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How do i make a circuit with 3 different counters that count 3 different things? [closed]

The system requires 3 counters -one for the number of pills per bottle -the number of bottles filled -the total number of pills in the final bottles.
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4answers
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Does this combinational lock circuit contain any memory?

Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
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2answers
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Is a combinational logic circuit a Finite State Machine? [closed]

Is a combinational logic circuit a Finite State Machine? In other words, is the class of combinational circuits a subset of the class of Finite state machines?
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3answers
108 views

We want numbers that lie between 1 and 10 inclusive, why should I use OR gate instead of AND?

I know the answer, I need to use an OR gate because that is how the code works. I want to learn the problem solving part of this. The code that works is: ...
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Understanding SAR ADC Control Logic

I am trying to understand how SAR control logic works before I use it in a design. I have read a few papers that design SAR ADCs but they don't go into detail on the control logic; they only show the ...
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How to compensate noise at the output of logic gates?

I am simulating 74HC logic family on LTSpice. The output of inverters and D-Flip-Flop are normal, but the output of NAND and AND are noisy . How can I compensate or filter that noise? What kind of ...
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3answers
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What size does my resistor have to be for the IC input?

I am testing some logic gate ICs to include in future projects. However, even when both of my switches are off, my logic IC is still sending a logical HIGH to my LED. I think my problem is the same as ...
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1answer
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Uses of IC Logic Gates in Microelectronics [closed]

My question concerns the following ICs: AND, OR, NAND, NOR, XOR, XNOR Voltage Translating Gates Buffers Drivers Translators I understand what (1)s do, but what are simple uses for them? I have no ...
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What is the invisible layer between Boolean algebra and the physical circuit of a computer, and how to understand it?

How is Boolean algebra implemented through a circuit ? Is it just a way of thinking about a circuit? You don't need Boolean algebra to think about a circuit since it is made of physical components, ...
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1answer
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How can I multiplex the outputs of an XBEE and a MAX485's?

I have a microcontroller that gets fed with 8-bit commands that either come through wires (using the RS-485 standard) or by the RX pin of an XBEE (without using actual switches) I want to multiplex ...
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1answer
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Minimizing delay of Full Adder

It is said that by exploiting the inverting property we can "reduce one inverter delay in each full adder". Why is that? Clearly, we can reduce one for the input of the first adder, but we ...
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2answers
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truth table from logic circuit [closed]

How should a truth table look for the logic circuit below if there is one output that is determined by just one of the inputs?
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2answers
141 views

Will this register drawing work?

I have just learned about how logic gates work and I am trying to simulate a 1-bit register without using a clock signal. My design looks like this: The logic should work something like this (...
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Unsure whether or not the following logic circuits I have created are correct

I have recently began studying logic gates and boolean expressions and have been told to label the 2 following logic circuits, as well as derive the full boolean expression for them. I have come up ...
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1answer
105 views

How many logic gates are there in this circuit? [closed]

How many logic gates are there in the following circuit? When counting how many logic gates this circuit contains, should each 3 input gate be counted as two 2 input gates? It is something extremely ...
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Standart Retiming circuit with two D type Flip Flops

I am trying to build a button(for adjusting the clock) syncroniser circuit for a seven segment clock. The button signals are of course async inputs so there needs to be retiming to make sure it goes ...
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3answers
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Why is the term 'Voltage' used instead of electric potential in "output voltage" within logic gate implementations?

This is a drawing of a MOSFET implementation of a NOT Gate. V_OUT is the voltage that will be output. However, I find the term "voltage" strange, because a point of a circuit shall be "...
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2answers
142 views

How to implement a full adder using only AND, XOR gates

The question is that I have 3 inputs (X,Y,Z) and two outputs (S,C). I have to implement a full adder circuit using only AND-XOR gates. I did a little bit of research but I couldn't figure out a way to ...
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Finding Elmore delay if S/D are shared, between two unequal transistors?

If W=3, and Cload = 10, How can we find output pull down delay? If there is no sharing of S/D then the problem is simple C_n=(2+W)C delay = (R/W)(C_n) + (R/W + R/2)(C_load) but when we are sharing S/D ...
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4answers
123 views

For an AND Gate to work, do the two inputs need to arrive at the same time?

I understand that AND gates require the two inputs to be present for the output to be produced. However, if one input arrives faster than the other input does the output get produced? Additionally, is ...

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