Questions tagged [logic-gates]
Symbolic representation of ideal devices implementing boolean functions
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Why are NAND gates used to make AND gates in computers?
Why is this a standard for AND gates
when it could be made with two FETs and a resistor instead?
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Different inverter (logic gate) symbols
The symbol for an inverter (logic gate) is usually the one shown below left. But I have sometimes seen the symbol shown below right. (See, for example, the last image in this answer.) What does ...
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Building a full adder with NPN BJT transistors
So I'm trying to wire up a full adder just with NPN BJT transistors (I know there is a 74XX283 4-bit binary full adder, but I want to do it just with transistors if possible for my own learning).
The ...
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K-maps for forming 8bit binary to 8bit BCD digital circuit
I have been trying to convert 8bit binary to 8bit BCD. The circuit I have been working on is below:
I built a 4bit binary to 5bit BCD converter using a similar truth table like the one here:
Do I ...
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Why is the + sign commonly used as logic OR operator?
A few days ago I was asked, why it is pretty common to use the + instead of the v symbol as the boolean OR operator in digital ...
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Multiplexing UART
I'd like to interface my main microcontroller's hardware serial port to more than one device at the same time. My understanding is that UART on my microcontrollers is based on an active-low 5V TTL.
(...
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Pull down resistor on logic gate input
I would like to use a pull-down resistor on the input of a NOT logic gate. I am using a 5V microcontroller, and I want to ensure that the input of the gate will never be floating (eg. microcontroller ...
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What is meant by logic high or low
In a circuit involving integrated circuits, the documentation for the ic often states that if a pin is in logic 1 or high the circuit will behave in one way, and if the circuit is in logic 0 or low ...
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What is the purpose of a buffer gate?
As I understand a buffer gate is the opposite of a NOT gate and does not change the input:
However I sometimes see buffer gate ICs used in circuits and to an inexperienced eye they seem to do nothing ...
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OR gate vs. connecting two wires?
I am not much of an electrical person but I'm trying to get an idea about it, so keep in mind I have very little background outside of college level electrical physics with calculus, and a strong ...
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Making a logic circuit with only NAND GATES?
I am trying to create a logic circuit using only NAND Gates for this expression:
(NOT Q AND P) OR R
This question has really gotten me stuck! Can somebody please help?
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Why is D flip-flop positive edge triggered instead of level triggered?
I'm trying to understand this D type positive edge flip-flop:
simulate this circuit – Schematic created using CircuitLab
I'm having problem understanding why it is positive edge triggered and ...
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Is this NPN transistor AND logic gate practical?
Most places on the internet that I see give a schematic for an AND gate that is something like this:
simulate this circuit – Schematic created using CircuitLab
The only thing about this is ...
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AND gate output when inputs are open
My problem is about AND-gate when its inputs are open. I want to know: What is the output when inputs are open? The output is Z (open) or 0?
What is your idea about this AND-gate transistor ...
user194071
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Why is base resistor of a transistor important?
I know that this is a very basic question but I really do not know the answer.
I was making simple logic gates using transistors and I used PNP transistor as NOT gate.
I made the following circuit: ...
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Why would an AND gate need six transistors?
I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense ...
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What will happen if the output from a NOT-gate injected- BACK to its OWN input?
Not-gate, if get a 0(Off) input, it gives an 1 (On) output. And if get a 1 (On) input, gives-back a 0(Off) output.
Now, if-I could bring the output back to the input of the not-gate, then what will ...
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Why are NAND flash and NOR flash named using the terms NAND and NOR?
Is the naming of the two flash architectures related to differences between the two types of logic gates? If so, how?
Why does or doesn't this difference also apply to different DRAM or SRAM ...
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How do I make a double dabble circuit with logic gates
Im attempting to make a 8 bit binary calculator that displays on multiple seven segment displays. Can double dabble be done with logic gates. If so, how?
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How to ensure an off-before-on transition for an H-bridge?
I want to control a H-bridge using an ATMega2560. The goal is to produce output with +-18V for driving a Merklin H0 digital train set.
Given the voltage and current needed for the trains it is ...
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Which of the following methods should I use to actuate a solenoid from a microcontroller?
I've been studying the PICAXE microcontroller as a driver for a set of three 12VDC solenoid valves (though I may choose the 24V models). For reference, the controller will use a temperature sensor to ...
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Which gate is better in building the Full Adder ? XOR or OR
So this is a question that was asked in one of the exams. As you know, there are 2 ways to get the boolean expression for the sum of the full adder.
Given X and Y are inputs, C0 is the carry from ...
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Boolean expression to NOR-gates
I'm having some trouble understanding how I can convert a boolean expression to a NOR-gate only expression. What I'm working with looks like this:
$$T = BD + \overline{A}B\overline{C} + \overline{A}...
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Why is the output (in the truth table) inverted in a ic 74154 used as a demux?
I am studying Digital Principles and Applications from Malvino and Leach. I have a doubt in the demultiplexer section. This is the image of a 1 to 16 demux. I understand how it works.
So, if ABCD = ...
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CMOS (wrong) OR gate with 4 transistors
I'm currently reading through Introduction to Computing Systems: From Bits & Gates to C & Beyond and I'm a bit confused about the outputs of this OR gate (which is not an OR gate):
And here ...
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NAND gate problem
As a practice question for our exam, we were given this circuit. The question was to find out which transistors have current flowing between the collector and the emitter and which do not. The problem ...
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Emulating Logic-AND gate
The following is an image of the AND logic gate from electronics-tutorials and my representation of that in EveryCircuit, where I've used the "Logic input" as the A/B inputs on the left (equivalent to ...
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D-Flip-Flop Hold and Setup Timing
I am solving some question to prepare for my exam but got stuck on this one and need your help.
Giving the following circuit:
Where input x gets updated 10ns after ...
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Having trouble with determining why my XNOR transistor circuit is not behaving
this is my first post. I've been working on creating logic gates from 2N2222 transistors. I've build a basic switch, NOT Gate, OR, NOR, AND, NAND, and XOR (from a combination of the others). However, ...
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Monostable out of NAND gates
For the diagram below, I can see that it functions as a monostable (I have built and tested it), but I can't really see why it works, I mean, I can see that there is an RC network, which a monostable ...
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Rewriting a boolean expression only using NAND
So I had a truth table and using a Karnaugh map I simplified a function. I obtained.
\$ f = \overline{A_3}A_2\overline{A_1} + \overline{A_2}\overline{A_0} + A_3\overline{A_0} \$
Then using the ...
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How can I design a 4-to-16 decoder using two 3-to-8 decoders and 16 two-input AND gates?
I have an idea of how to get started, but not sure where to go from there.
Since I am using two 3-8 decoders to develop a 4-to-16 decoder, I want to use 4 inputs out of the two 3-8 decoders. So I'll ...
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Finding frequency of a series of pulses (3 - 60 Hz) without using a microcontroller or frequency-to-voltage converter
I came across an interesting yet challenging problem of finding the frequency of a series of pulses. The pulses can have a frequency anywhere from 1 to more than 100 Hz. The goal is to detect if the ...
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Noise immunity and noise margin
Why is noise margin in logic gates a quantitative measure of noise immunity?
Can anyone provide an instantiation to demonstrate how noise margin is a measure of noise immunity
user212907
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CMOS OR gate using 4 Transistors
Can an OR gate be implemented using 4 CMOS transistors? The circuit would have two n-type transistors in parallel in the pull-up network, and two p-type transistors in series for the pull-down network....
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Replacing a diode-OR gate by a circuit that behaves the same way (also in the presence of feedback loops) without accumulating voltage loss
Consider the following circuit with two OR gates:
simulate this circuit – Schematic created using CircuitLab
and the Time Simulation:
The OR gates with both inputs 0 generate 0, and after ...
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Diodes in parallel circuit analysis
Could some please help me understand why D2 is on and not D1 on a) and why is D1 is on and not D2 for b). This is for ideal diodes
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H-bridge MOSFET NAND gate driver suffered from logic voltage drop
I've tried to reproduce the NAND Schmitt triggers circuit to drive my H-bridge MOSFET as per following source:
http://axotron.se/index_en.php?page=34&chapter=0
All my design files are at this ...
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NOR Gate is Working Correctly with Vcc Pin Disconnected
I modified my Sega Master System to have a pause button on the actual controller. To process the signal, I soldered a quad NOR gate to the I/O and CPU circuits in the console. The idea is that the ...
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What is wrong with my Dmux8way? How can I fix it?
The problem is something with the sel spliter and the leftmost
DMUX4WAY, the automatic check returned - "have different bit width and cannot be connected". But I don’t know how can I fix it.
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How does a 0 as a binary input work if it is given by off?
In electronic circuits, for binary operations we use on as 1 and off as 0. Like in the data transmitted through fiber optic cables is sent using light going on and off. How can an output be generated ...
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Counter using only basic logic gates
I'm trying to make a counter (0 > 9) using only basic logic gates , I used the master slave jk flip flop and it work fine except that I don't know how to make it reset to 0 again after 9.
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Fan-In/Fan-Out - Circuit - Explain why this circuit does not work
Problem: Explain why this circuit does not work for Fan-In=1 and Fan-Out=3 for all logic gates(including the complex logic gate).
Firstly, I would say the Inverter Gate is fine because it does not ...
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Three legged NOT gate? What is this symbol?
I've come across the above schematic in a datasheet for a 4x2:1 bus switch. What exactly does that triangular symbol on S mean? It looks a lot like a NOT gate, but ...
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Diode Logic Gates
For some reason, I understand transistor logic gates, and I am able to solve problems, but for some reason I do not understand the and / or logic gates constructed by diodes. If someone can explain it ...
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How does electricty flow in a flip-flop circuit? I can't understand how memory bits work with NAND gates
Consider:
simulate this circuit – Schematic created using CircuitLab
The i bit is what we want to store, and the s bit is ...
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How do you implement the following function using nothing but 2:1 MUX?
I am having difficulties understanding how to implement boolean functions, particularly given that I may only use 2:1 muxes and the variable D as a residual variable.
The function is as follows:
$$
...
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Why is this a Moore and not a Mealy FSM?
Can someone please explain how I can tell which FSM type I have? In my textbook I read that output in a Mealy FSM is based on both the input and the present state, but in a Moore FSM it is based only ...
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Why does the TTL NAND gate use a 4 transistor design instead of 2?
Why does the TTL NAND gate use 4 BJTs to make the gate when it could be done using only 2?
I assume that the design with the 4 transistors amplifies the current so multiple levels of gates can be ...
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CMOS and gate implementation
As far as I am aware, this is an incorrect implementation of an AND gate, as when out is logic high, the two N-type FET transistors will go to an open state, leaving it floating. I am doubting my ...
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