Questions tagged [logic-gates]
Symbolic representation of ideal devices implementing boolean functions
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"Double-pumped" flip-flop?
As of this moment, does anybody make a single-chip flip-flop that latches its state on BOTH the falling AND rising edges of a clock? In other words, instead of latching an input's state and setting ...
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Why does NOR need one more output to the multiplexor but NAND not in ALU?
Recently, I was learning "Computer Organization and Design: The Hardware/ Software Interface" riscv 2nd Edition by "David A. Patterson"
In appendix A, A-37 shows the question in &...
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Chaser circuit with a chain of 4017's
I have a problem with this chaser circuit.
It should work like this:
When I switch on the power, no outputs should be activated.
When I press the reset button, the clock signal will be started and ...
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Diodes needed (parts) for OR gate automotive relay circuit
I need to power up a make-or-break simple automotive relay (4pin, 40A 12V) via an OR gate.
OR gate as follows:
Source 1 is the cable that provides +12V to activate car dome light which I will tap ...
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Logic gate biasing a BJT (again)
The following schematic shows a PNP BJT driven by the output of a logic gate. When the logic gate output is high the transistor must be off, and only be activated when the logic goes low.
The problem ...
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What is the internal schematic for a 74HC series gate (NAND gate as an example)?
It's rather easy to find the schematics for a CMOS NAND gate on the net -- two series NMOS transistors as the pull-down network, two parallel PMOS transistors as the pull-up network.
What would an ...
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If two Boolean functions \$f_1\$ and \$f_2\$ have same truth table, does that means they have exactly same characteristic? can one f1 numerate to f2?
if \$f_1(x,y,z)=\neg xz+x\neg y+\neg xy\neg z+xy\neg z\$ determine if \$f_1\$ is symmetric and whether it is unate.
What I thought is:
\$f_1\$=¬xz+x¬y+y¬z, the truth table of \$f_1\$ has the same ...
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How to understand this combinational cyclic circuit made of interconnected SR latches?
I'm trying to understand the following circuit, or better said, what must be the approach to analyze other similar ones:
What I'm doing for now is forget about the clock signal and the ...
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Multi-level circuit simple NAND conversion: Why keep non-NAND symbols?
I am working on understanding the NAND conversion. I have just got the basics of two-level NAND conversion, and when I went to the book example for a multi-level NAND conversion it used solved an ...
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Full adder 2D addressing
I try to implement a full adder circuit using square arrays.
I've used Digital software to design it. Also I've tested it. It works fine.
But my implementation is quite different from the circuit ...
user211748
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Minterms from Logic Circuit
I have the following logic circuit:
And I'm asked to identify the minterms in F's truth table.
The expression for F is
F = C + A'B'
and the truth table isn't too difficult to construct (X=F):
I ...
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Low Current Consuption on a Voltage Inverter
I'm working with a uC and a Bluetooth Module. I need the lowest current consumption in this project because it is intended to be a mobile device. Thus, I'm using sleep modes on the uC. Now, I've ...
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Master-Slave JK Flip Flop Truth Table
In my computer logic and design class, we have gone over the different types of flip flops and their representations. I understand what the goal of the master-slave configuration is but I am having ...
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How to turn an LED on in an inverter circuit
I am currently trying to build an inverter circuit which turns on an LED (on a simulation before building it physically). I am using an 2N3904 NPN transistor, 5V voltage sources, a 220k and a 47k ...
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How do I implement a synchronous reset switch to my D-Flip Flop
This is my master slave D Flip Flop and I was wondering where do I put the reset switch to make it into a D Flip Flop positive edge with a synchronous switch. I know that for synchronous, you can ...
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How do I create a 8-bit binary digit out of the combination two 7-bit ASCII values?
I am implementing a circuit that takes two ASCII values that are in the range 0x30 - 0x39[0 - 9] for the tens digit and ones digit, and then combine them, and output a proper 8-bit binary value ...
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How to simulate a button press on DFPlayer Mini?
I have a DFPlayer Mini with an SD card with one song on it. I want to make a circuit to power it on, and after a couple seconds, simulate a button press through a 33k resistor on pin 12 to trigger the ...
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Circuit help required - press two buttons to trigger third input using common ground fightstick board
I have a gaming fightstick which I don't want to install any additional buttons into. I need help with connection or a circuit so when I press two buttons (eg select & start), it triggers a third ...
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Unexpected voltages on home-made OR gate
I've created some home-made gates using discreet components onto strip board.
So far I have an OR gates, an AND gate and 4 NOR gates.
Logically they all work as expected but on only one of my 4 NOR ...
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Did I create this Karnaugh map correctly?
I'm tasked with making a 4-7 decoder for a 7-segment LED (common anode).
I am an extreme layman (1st year EEE student)
I have 4 inputs (A,B,C,D)
...
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What's the problem with this four-transistors XOR gate?
I aimed to design a XOR gate using as few transistors as possible. Eventually, I came up with this:
Designed and simulated here. The two terminals on the left are inputs, where the "low" ...
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NEC asic information from around 1990
I'm looking for datasheets with specification for the NEC ASIC/Gate Arrays from around 1990.
More preciselly, any information with specifications of their ASIC/Gate Array lines.
I would like to known ...
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How to determine if a gate/inverter can drive a fanout of 4 gates?
I have a circuit in which a driving inverter output (Fanout of 4) with equal Wn Wp sizing (m=4) is driving 4 other gates having same equal Wn Wp sizing (m=1). How to calculate if the inverter fanout ...
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NAND circuit from boolean expression
What is the best way to convert following boolean expression to circuit based only on NOT, NAND gates?
I already done OR, AND circuit.
But what is the method to receive that?
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Frequency of a sequential circuit
I'm reading the book Digital Design and Computer Architecture. I came across this exercise:
From what I've learned so far, the frequency of a circuit is the reciprocal of the clock period. Since we ...
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We want numbers that lie between 1 and 10 inclusive, why should I use OR gate instead of AND?
I know the answer, I need to use an OR gate because that is how the code works. I want to learn the problem solving part of this.
The code that works is:
...
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CMOS Logic Gate Interpretation
So I came across this interesting question while researching CMOS logic gates:
As is says, a logic function \$Y\$ is given and you are required to create a logic network that implements it. I am ...
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How to know whether addition has been done in a parallel binary adder?
I am little new to electronics and getting some high level overview of digital electronics. The question is that how to know whether addition has been performed in a logic circuit.
For example I have ...
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creating symbol for Transmission gate switch in ltspice
I need to create a symbol of transmission gate to use but when putting its symbol I get a message "unknown subcircuit called in xx1_nc01_nc02_nc03_nc04
how may I fix it?
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Time (Propagation delay) taken for adding 3 n-bit binary numbers using Carry Propagate Adders (Ripple carry adders)
While being introduced to carry save addition technique, I was told that the time taken for adding 3 n-bit binary numbers using ripple carry adders will be (2n+1)t_FA (Assuming we neglect the minor ...
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Verilog project - Binary to BCD - 0-49 2 digit display
I have an end of the year project where I must create an 4 operation ALU that outputs its result onto 7 segment displays in Verilog.
2 of those operations are multiplication and addition. Considering ...
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Does this circuit include two level logic circuits?
I made the circuit below from the logic expression below.
A'B' + A'C' + A'D + ABC
But, I was told to consider adding two level AND-OR and NAND-NAND logic circuits. I think the circuit below has them,...
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Use battery to drive main circuit or load battery and cut-off main circuit depending on power source
Please excuse my beginner's question. Having read about electronics and logics basics and specific power-related questions, I've not found anything that would explain to me how to realize the ...
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Logical Effort (G) and Effort (H) in Parallel
I am struggling with this question in which I need to understand what is the route with the least effort (H).
Usually, I'm given a route but it's very simple to calculate, because all the other inputs ...
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Can I implement addition and subtraction in different operations using a MUX?
I'm building a 16-bit ALU that needs to be able to perform logical AND, OR, add, subtract and rotate one bit to the left.
I need to have addition and subtraction operate with different op codes ...
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Not getting output from a subcircuit
I just started to working with Proteus and I want to implement and test some simple circuits.
I made a subcircuit and tested it with logic state and logic probes.
The first picture is my main sheet ...
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Why simple digital multiplexer uses OR gate to combine chip parts outs?
Why not just wire together outputs of the internal AND gates. For instance, consider the following Mux scheme:
Here outputs of the internal AND gates are combined using out OR gate to produce output, ...
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Build a T flip-flop with enable and reset using only a JK flip-flop (without enable or reset) and some necessary logic gates
Can someone help me to check whether my answer is correct or wrong, because I am confused with some of the condition of enable and reset. I am confused if the enable is low and the reset is high, ...
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Why does my synchronous up counter count enable not function properly?
I have designed a simple 4-bit synchronous up-counter, using master/slave JK flip flops in Logisim.
Here is my JK design:
And my counter design:
It works perfectly as intended, however if the INC (...
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How do I implement a Barrel Shifter?
I'm using Multimedia logic for this particular assignment, I am to implement an ALU that performs Bitwise Rotation on the input from "A" by the amount defined by "B". Not quite sure how to approach ...
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Design this memory with D flip-flops
Design the following memory with D flip-flops (you can use other gates or decoders if needed).
The following memory has 4 one-bit locations and can access 2 locations at each moment and read from ...
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Estimating gate or transistor count for an IC
I'm messing around with calculating predicted failure rates using MIL-HDBK-217F. For microcircuits (depending on linear or digital) you need to come up with a gate count or a transistor count for the ...
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Can an OR gate be made using 2 XOR and 1 and gate?
Hello i was wondering if an OR gate can be made using 2 XOR gates and 1 AND gate.
as i got this question in one of my exams a few days ago.
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Jellybean Radio Button logic Chip
Below is an LTSpice simulation of a 'radio button' circuilt.
Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons.
The idea is that the button you push, ...
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How can I implement this function with JK flip-flop + NAND gates?
I need to design a mod-5 up/down counter with control input x. When x = 0 it will count down, and when x = 1 it will count up. I'm allowed to use only a JK flip-flop and NAND gates. Complement of x is ...
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Tail Light Control State Diagram
I am attempting to implement this tail light design first by using a state diagram. The car has 4 tail lights on each side, making a total of 8. They behave accordingly when the following inputs are ...
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Finding the SOP expression for the XOR gate and the circuit for it
Would the sum of products expression look like so:
\$\overline{A}\cdot B+A\cdot\overline{B}=Z\$ ? And the corresponding circuit should look like so?
Sorry for the bad drawing. I'm just wondering if ...
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I need help with designing a specific circuit
Design an arithmetic unit. Let A and B be two 4-bit 2’s complement numbers. Design a circuit to compute:
Z = A + B if k1k0=00
A + B + 1 if k1k0=01
A if k1k0=10
A - B ...
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Intrinsic glitch of the XOR PORT
Good evening, I'm dealing with the glitch of the xor gate. I read on the book 'Code Design for Dependable Systems: Theory and Practical Applications' that a glitch is generated when more than one ...
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2^n - 1 modulo parallel prefix adder
So I have to do a simple 4-bit modulo 2^n -1 parrallel prefix adder. I've actually made a working one, but not modulo. Now I have a trouble with transforming it to modulo one. This looks like this:
...
