Questions tagged [logic-gates]
Symbolic representation of ideal devices implementing boolean functions
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Why are NAND gates used to make AND gates in computers?
Why is this a standard for AND gates
when it could be made with two FETs and a resistor instead?
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What is the purpose of a buffer gate?
As I understand a buffer gate is the opposite of a NOT gate and does not change the input:
However I sometimes see buffer gate ICs used in circuits and to an inexperienced eye they seem to do nothing ...
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What is the process of going from machine code to electrically controlling individual transistors? [closed]
For someone who writes software but doesn't have a computer engineering background, the dozens of abstraction layers have always bewildered me.
I know all source code in their most fundamental level ...
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Why does a single AND gate need 60 transistors?
Looking at the datasheet for the MC74VHC1G08, under the features section, it states Chip Complexity: FETs = 62.
Why does this IC need 62 transistors, while an AND ...
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Why would an AND gate need six transistors?
I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense ...
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Three legged NOT gate? What is this symbol?
I've come across the above schematic in a datasheet for a 4x2:1 bus switch. What exactly does that triangular symbol on S mean? It looks a lot like a NOT gate, but ...
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What will happen if the output from a NOT-gate injected- BACK to its OWN input?
Not-gate, if get a 0(Off) input, it gives an 1 (On) output. And if get a 1 (On) input, gives-back a 0(Off) output.
Now, if-I could bring the output back to the input of the not-gate, then what will ...
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Why is the + sign commonly used as logic OR operator?
A few days ago I was asked, why it is pretty common to use the + instead of the v symbol as the boolean OR operator in digital ...
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OR gate vs. connecting two wires?
I am not much of an electrical person but I'm trying to get an idea about it, so keep in mind I have very little background outside of college level electrical physics with calculus, and a strong ...
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Why am I Seeing A Weird "Notch" on the Data Line For Some Logical 1s?
I'm attempting to build a Z80 homebrew computer for some retrocomputing fun and to teach myself the basis of electronic design. For proof-of-concept, I've already assembled a basic system on ...
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Diode Logic Gates
For some reason, I understand transistor logic gates, and I am able to solve problems, but for some reason I do not understand the and / or logic gates constructed by diodes. If someone can explain it ...
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Why do two reverse diodes represent the logic gate AND?
Consider:
I can make no sense in my head how this can work. How is it possible to have a current flow through normal diodes from cathode to anode and represent an AND if both are 1?
user165500
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What is the purpose of an AND gate with the same signal on both inputs?
If this is a buffer, why use an AND gate, aside from better availability of that gate in a single package? This is on an Analog Devices SHARC eval board.
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Digital Logic circuit - exam question
I have a question from exam that I failed to solve:
I need to build a digital logic circuit that is receiving 4 bit number and return true if the number is ...
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Why do CMOS NOT gate designs differ from BJT NOT gate designs?
If you look for an inverter circuit on Google Images, you'll find something that looks like this:
This inverter design has a single NPN transistor. However, on Wikipedia's article about transistor ...
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What is the purpose of chaining series of NOT gates?
I have seen these a few times, but I don't know what the purpose is. Clearly the purpose is something else than just to invert the signal. Otherwise just one or two would be enough for that. Also, ...
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Why do we need to use transistors when building an OR gate?
Why do we need to use transistors when building an OR gate? Wouldn't we be able to achieve the same result without transistors at all, just by joining the two ...
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Why does the race hazard theorem work?
So for those who don't know, the race hazard theorem (RHT) states that:
A x B + A' x C = A x B + A' x C + B x C
I understand the other part of the RHT, about time delays and such, but I don't ...
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Why are there no single logic gates in through-hole packages?
If I'm not mistaken, single logic gates (i.e. a single NOT, OR, NOR, AND, NAND, XOR, etc.) do not exist (anymore?) in through-hole packages.
At least, on Digikey, when searching for active in-stock ...
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My Professor and I are debating about absorption law
So the question is \$(w+y)(wz+wz')wy+y\$ and this is my answer by absorption law where \$A+AB=A\$:
$$
(w+y)(wz+wz!)w y + y\\
B A + A
$$
So the answer is \$A=y\$.
My professor said I ...
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With this AND gate made of transistors, why does the LED need a resistor in parallel instead of in series?
I'm building an AND gate out of transistors. Knowing how the basics work, I built my own (naive) circuit using the following design.
In testing, it didn't work like an AND gate.
A
B
LED
0
0
Off
1
...
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Do MOSFET logic gates necessarily need an N channel MOSFET?
I've been studying CMOS logic gate design, such as an inverter here:
Why do we need the N-channel MOSFET at the bottom at all? Couldn't it be replaced with a simple resistor into ground like this?
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Why do logic gates need multiple MOSFETs?
I've just started learning about physics and electronics, and right now I'm learning about creating logic gates with CMOSFETs (Complementary MOSFETs). I'm interested in this because I'm a "high-...
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Discrete logic design
I have been tasked with building a simple alarm device. It just needs to measure a few inputs and the outputs will respond accordingly (to put it very simply!). To me, it seemed that using a few ...
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How to compensate noise at the output of logic gates?
I am simulating 74HC logic family on LTSpice.
The output of inverters and D-Flip-Flop are normal, but the output of NAND and AND are noisy
.
How can I compensate or filter that noise?
What kind of ...
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AND / OR gates implementation (real or educational)
Frank Vahid's "Digital Design" book presents AND and OR gates at the transistor level like this:
Disregarding how it hurts the eyes to see them upside-down like this, is this purely ...
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How does electricty flow in a flip-flop circuit? I can't understand how memory bits work with NAND gates
Consider:
simulate this circuit – Schematic created using CircuitLab
The i bit is what we want to store, and the s bit is ...
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Different inverter (logic gate) symbols
The symbol for an inverter (logic gate) is usually the one shown below left. But I have sometimes seen the symbol shown below right. (See, for example, the last image in this answer.) What does ...
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Why do we need NMOS transistors for NAND gate?
I have a hard time understanding how gates are built from CMOS transistors. For example, I don't understand why do we need the NMOS transistors if the PMOS transistors will already produce the desired ...
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Of what use can a logic gate be to a circuit that contains a micro-controller
I am wondering if a logic gate would be of use to a circuit that contains a micro-controller.Are there cases when an analog logic gate is preferred over a micro-controller and what are some of the ...
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Why are OR gates using transistors different from OR gates using diodes?
There are two ways to make an OR gate:
and:
But with diodes it looks easier to make than with transistors, isn't it? What are the advantages of the transistors version and drawbacks of the diodes ...
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What does a chip's propagation delay vary on?
When looking up datasheets on logic gates, propagation delay is usually shown as a range. Sometimes there's a "typical" value in the middle, but there's a min and max listed. On what does ...
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Determining how much load capacitance a 40-series logic IC can safely drive
In designing a circuit, meant to delay only the rising edge of a square wave, I've got some doubts on determining the maximum value for C1 that can safely be driven by the CD40106 CMOS logic IC.
The ...
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Multiplexing UART
I'd like to interface my main microcontroller's hardware serial port to more than one device at the same time. My understanding is that UART on my microcontrollers is based on an active-low 5V TTL.
(...
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Using HC/HCT, AHC/AHCT series logic
I am builing a circuit, and i need to connect a few different IC's (obiosly). My circuit is based on 5V TTL logic and i found a part that is made only in AHC/AHCT variant.
So let's take it from the ...
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Does the 74LVC1GU04 actually have "Schmitt-trigger action" on its input?
The 74LVC1GU04 is an unbuffered inverter, which (according to the datasheet) is intended to be used in linear mode in applications, such as crystal oscillators and linear amplifiers with negative ...
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What is this trapezoidal logic gate?
What is this thing called? how does it work?
I've tried googling so much, even pasted the image in the google search box haha
Its used here on the MSP430:
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Determining minimum number of NAND/NOR gates required to realize a Boolean expression
Is there any algorithm to determine the minimum number of NAND or NOR gates with
given number of inputs
availability / unavailability of complemented input
required for realizing a Boolean ...
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Why aren't many classical logic gates reversible?
It's mentioned in a textbook for quantum information that many classical logic gates such as the NAND gate are inherently irreversible. I'm confused why this is true. What does it mean by reversible? ...
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What is meant by 'On-chip 2-cycle Multiplier' for AVR microcontroller?
While checking the datasheet of ATMEGA 32 I have found a feature called 'On-chip 2-cycle Multiplier'.
Can anyone explain to me what's that and what's the advantage of it?
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Is is possible to create modular logic gates from transistors for teaching purposes?
I'd like to work through some basic logic circuits with some youngsters and wanted to build them up from scratch (transistors), not logic gates if possible.
We've done the basics: buffer, NOT, AND, OR,...
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Why do TTL integrated circuits have such complicated schematics for logic gates with so many transistors as opposed to RTL?
I'm in the process of building a 4 bit computer out of discrete NPN BJTs and resistors. I'm using RTL, and I've made flip flops, full adders, and demultiplexers, and everything is working fine so far. ...
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Is the NAND logic gate perfectly symmetrical?
In other words: if we swap A and B, will Q behave exactly the same in DC and transient analysis?
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check if an unsigned binary number is divisible by 15
I'm a computer science student and I got stuck on this question for hours.
We have a binary unsigned number X, represented by 12 bits.
We would like to build a system with 1 bit output - Y, that will ...
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What is the advantage of using Logic Shifter ICs over just building it with NMOS Transistors?
I was browsing the internet for SD card module schematics for a board I am developing that should read and write data to an SD card. I realized that these modules use specific ICs to convert 5V logic ...
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Connecting unused logic gates
Logic gates like AND, OR, NOT etc. often come packed as arrays in ICs.
Sometimes not all gates are used in a project. I would like to know how the remaining unused gates should be connected to ...
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How do you implement the following function using nothing but 2:1 MUX?
I am having difficulties understanding how to implement boolean functions, particularly given that I may only use 2:1 muxes and the variable D as a residual variable.
The function is as follows:
$$
...
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74HC being labelled as 74LS?
Bought several tubes of 74LS00. We test the datasheet spec for VIH by sweeping one input from 0 V to 5 V while holding the other input at 5 V, and checking the output. Usually we expect to see a ...
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How to map a truth table to ternary logical functions?
Please be kind. I have a thorny and important question from a different field of engineering whose answer may be fairly well-known in electrical engineering. I asked a similar question on ...
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How do I design a clocked synchronous state machine for a combinational lock?
I need help in completing a task, I’m stuck on quite a few things. Since I’m very new to this topic on finite machines.
I’ve attempted the state diagram, state table, transition table, K-map values ...
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