Questions tagged [logic-gates]
Symbolic representation of ideal devices implementing boolean functions
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Why do we use an inverter at the end in CMOS AND and OR gates?
I know it is a very basic question but I couldn't really find an answer on the internet. Our lecturer told us it is used to reduce the number of transistors used in the design.
Our first case without ...
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CD4098 as an astable multivibrator
I have a bunch of unused CD4098 ICs available and I was hoping to use them in DIY-project to drive a counter (therefore duty cycle % does not matter) in astable multivibrator mode with adjustable ...
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Circuit help required - press two buttons to trigger third input using common ground fightstick board
I have a gaming fightstick which I don't want to install any additional buttons into. I need help with connection or a circuit so when I press two buttons (eg select & start), it triggers a third ...
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Unexpected voltages on home-made OR gate
I've created some home-made gates using discreet components onto strip board.
So far I have an OR gates, an AND gate and 4 NOR gates.
Logically they all work as expected but on only one of my 4 NOR ...
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(Logisim) D-flip-flop asynchronous reset not behaving as intended
I made the following 1-minute clock circuit in logisim that's supposed to count up to 59 seconds and then loop back to zero:
It works mostly fine, but the problem happens when it reaches 59 and loops ...
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Information leakage due to fault propagation in XOR gates
From the paper Fault Template Attacks on Block Ciphers Exploiting Fault Propagation, in the concept of Automatic Test Pattern Generation (ATPG), two events are required to perform in sequence: Fault ...
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How can I set time for this circuit the easiest way?
Can I do it in lab like Proteus and can I change the resistor and capacitor for the timer 555 to equal 1.023, like:
r1 = 10 kΩ
r2 = 10 kΩ
c1 = 47 μf
Is there a way without a resistor for AND gate or 7-...
user328849
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Does the 74LVC1GU04 actually have "Schmitt-trigger action" on its input?
The 74LVC1GU04 is an unbuffered inverter, which (according to the datasheet) is intended to be used in linear mode in applications, such as crystal oscillators and linear amplifiers with negative ...
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Did I create this Karnaugh map correctly?
I'm tasked with making a 4-7 decoder for a 7-segment LED (common anode).
I am an extreme layman (1st year EEE student)
I have 4 inputs (A,B,C,D)
...
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What are the considerations of using a common anode 7-segment display over a common cathode?
Common anode:
Do I need resistors here? Where would I connect them?
Common cathode:
Common anode seems simpler circuit wise - but I like the idea that "1" represents "ON" that ...
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What's the meaning of this yellow color in Proteus?
What's the meaning of this yellow color in proteus?
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Can I construct a logic AND on a "power" line
I have two 12W LED bulbs which are wired in parallel. I control them both with a MOSFET (M1.) Now I want to be able to dim one of the bulbs, but it should still only light up when the "original&...
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NOT gate output question
Newbie here with a very basic circuit question. I believe I understand how the transistor portion of the NOT gate depicted below works. What I am unclear about is why the output voltage Y changes from ...
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Is the invalid state of an SR latch also undefined?
I understand that if both the Set and Reset inputs of an SR latch are high, the output of both Q and Not-Q is low and this is considered an invalid state.
But in this situation is the output also ...
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How do I change an input from active high to a positive edge trigger? [duplicate]
know that flip flops are edge-triggered, but I'm not knowledgeable enough to know how to replicate that for my own circuits.
On a gate level, how does a pos-edge happen?
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How do I find resistors values for a TTL to ECL interface?
This is the photo of the ttl to ecl interface
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How to use the output pin of OR gate as one of its inputs?
I am trying to make a circuit using transistors that consist of an OR gate, but the output of the OR gate is used as B input.
As expected the LED should remain on as soon as an input is 1, and the ...
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Floating ttl input and ground short without pulldown
A pulldown resistor seems to always be used for configurations where when the switch is open the normal state is low.
For example
The reasons always given are to avoid a short between voltage and ...
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Solar panel as light sensor to switch a battery and LED circuit
I have a project powered by a solar panel which is supposed to charge a battery and then light up an LED only when it's dark outside. I made the initial circuit using an LDR and a potentiometer and ...
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D flip-flop circuit to show nine hex numbers alternately on one seven-segment display
I tried to make a circuit with a D flip-flop to show a hex number of F1D021301 alternately on a single seven-segment display, but it can only do F1D02130 or F1D0213 and return back to 0 and repeat to ...
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CD4018 divide by 11
I am making a circuit that creates various subdivisions of input frequency by integer values from f/2 down to f/12. Division by 2, 4, 8 are straightforward using JK flip flops. Divisions by 6, 9, 12 ...
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Which of the following input binary conditions will produce an ambiguous state in the flip flop?
For ambiguous state, both outputs x and y must be zero(for active low) to be considered invalid i.e. of both PRESET and CLR are logic "0". Now, analysing the circuit, $$ x=a \oplus D_0 $$
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How to find the Signal Probability equation of XOR gate with N inputs
2-input XOR gate truth table
The signal probability for a XOR gate with 2 inputs is: \$sp=(1-p_A)p_B + p_A(1-p_B)\$
3-input XOR gate truth table
The signal probability for a XOR gate with 3 inputs ...
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Implementing three-state logic
Can we build a three-state logic gate using only transistors (or basic logic gates)? If so, how is it built?
I'm trying to build a model for an 8-bit computer in LogiSim, and I'm trying to find out if ...
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For the 4x1 MUX shown below the Boolean Expression F(x,y,z) is [closed]
The output to a 4x1 MUX is : \$Y=S_1'S_0'I_0+S_1'S_0I_1+S_1S_0'I_2+S_1S_0I_3\$
My answer was : \$F=A_{1}'A_{2}'x+A_{1}'A_{2}x+A_{1}A_{2}'y+A_{1}A_{2}y' \Rightarrow xyz'+xyz+y'z\$
The correct answer is ...
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CMOS output Voh and Vol
I'm using this IC.
This is its Hardware Checklist.
I'm using DVDDH as 1.8V (which is VDDIO)
My question is, on page 55 of the datasheet, Table 6-4, for the LED1 and LED2 pins,
it is mentioned as "...
user220456
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A three-input NAND gate is to be used as an inverter. Which one of the following measures will achieve better results?
The two inputs not used are kept open
The two inputs not used are connected to ground (0 level)
The two inputs not used are connected to logic supply (1 level)
None of the above
I get that we can ...
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Determining how much load capacitance a 40-series logic IC can safely drive
In designing a circuit, meant to delay only the rising edge of a square wave, I've got some doubts on determining the maximum value for C1 that can safely be driven by the CD40106 CMOS logic IC.
The ...
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Small response in digital logic simulation
I am a student and new to digital logic simulations. Just curious as to why there is a very short response in OUT_02 at about 1.75 s.
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SR flip-flop with Preset and Clear should not work as described
In the presented flip-flop, suppose the Enable signal is high, the S is low, and R is high. Now we set the Preset low (0) and the Clear high (1). In this condition, we expect Q=1 and Q'=0.
But ...
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Is there a logical gate called grantr?
Is there a logical gate called grantr?
I do not remember where I have seen that name and I can't shake my mind from the thought that there exists a logical gate ( not function) with that name. Is ...
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Why can logic gate connect together with each logic gate behave the same way when it's by itself?
Why can logic gates connected together behave the same as single logic gates?
For example:
When inputs A and B are high, the AND gate output is high when it's by itself.
But when it is connected to ...
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Logical output of CMOS circuit
What would be the output of the following CMOS circuit?
My answer is coming out to be R(P+Q).
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Express state of overflow as function?
Making an ALU I want a signal that signals whenever an addition or subtraction changes the binary number from - to +. Each number u and v is 4-bits and therefore is marked by 0, 1, 2, 3 where 3 is the ...
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Why do we even need an OR gate? [duplicate]
Question
This might be a naive question but hear me out, can't we just connect the two wires in parallel to build an OR gate? Like this:
simulate this circuit – Schematic created using ...
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Circuit using a D flip-flop and logic gates
How do I create a circuit with two inputs A and B and one output Q using only one D flip-flop and logic gates? The circuit should perform the following when the clock ticks:
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Why is this NAND gate not turning on with both inputs off?
Problem
I am trying to simulate a circuit that acts like a memory bit in Logisim Evolution but for some reason the NAND gates don't turn on with both outputs set to 0. I suspect that the problem ...
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Why 1-bit multiplier is not expandable like 1-bit full adder does?
1-bit full adder is intended for add two binary operand (with size 1-bit). It has 3 inputs, that is first operand, second operand, and carry-in. Also it has 2 outputs, that is sum and carry-out.
1-bit ...
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What does "limit of 1 TTL LS load" mean?
If I read that a line has a limit of 1 TTL LS load, does it mean that I can attach only a TTL gate? I know that other options exist, for example, the HC, however, in the case I have only LS gates, how ...
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Output of SN74LS08N AND gate when inputs are connected to nothing
I am using a voltmeter to test the output voltage of the SN74LS08N AND gate. The inputs are simply jumper wires that I can conveniently plug into a voltage source (5V), GND, or otherwise leave it ...
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Circuit to share a pin
I ran out of pins on my MCU, and for that reason I want to share one pin, so it act as an input (data from a sensor) in certain part of my program, and as an output (chip select for SPI) in another ...
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Is it possible to create an A.B' logic using classical switches?
I'm new to electronics and I've been trying to make a device that reminds my father to charge his scooter when he comes into the garage. Here is the circuit diagram:
Switch S2 is a footpedal / ...
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Can the 74LVC06A input be connected to an open-drain output?
The picture above is the SN74LS06 schematic from Texas Instruments. It appears that the input of the SN74LS06 can be connected to an open-drain output.
I purchased the 74LVC06APW from Nexperia. But I ...
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AND / OR gates implementation (real or educational)
Frank Vahid's "Digital Design" book presents AND and OR gates at the transistor level like this:
Disregarding how it hurts the eyes to see them upside-down like this, is this purely ...
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Why doesn't my discrete gate SR flip-flop work? [closed]
When I make a SR flip-flop using NAND gates and configured it as in the above circuit. Why does it simulate differently and is useless?
Here is the circuit I made:
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What is this chip called? [closed]
I need a TTL chip 74 series, that takes in some amount of inputs and one enable bit. When the enable bit is high, the output is the same as the input. When the enable bit is low, the output is all low....
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Converting 2-line gate driver PWM to 1-line 3-state
I'm a software engineer, not really experienced in the hardware design, looking to confirm if I correctly designing the following piece:
I have a FOC motor controller chip (TMC4671) that is only able ...
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Frequency counter schematic
I was wondering what's wrong with my Proteus schematic.
This schematic is supposed to show the frequency in Hertz on the display but instead only three zeroes are displayed.
Is there any component ...
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A high-voltage logic part in PSpice
I'm trying to build the following part of a circuit:
I'm wondering what the part is that has "HI" written on it; I couldn't find it in any PSpice guide.
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Create a logic circuit only using AND & OR gates
yesterday I had an exam, in which I still don't know how to resolve the problem.
The question of the exam was: Create a logic circuit with 4 inputs (A,B,C,D) using ONLY AND & OR with 2 INPUTS ...
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