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Electrical Engineering

Questions tagged [lvds]

LVDS stands for Low Voltage Differential Signalling. It is a popular high-speed (>100 Mb/s) way to connect chips.

106 questions
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19 views

sub-LVDS to CSI-2

I am going to make two prototype boards with the same functionality but using different components. For the first prototype board, my question is related to this topic. The imaging sensors I'll use ...
2
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2answers
63 views

Can CML differential signal lines be flipped to act as a NOT gate?

If I want to invert a CML differential D-Flip Flop (Ex: hmc747lc3c) output before entering into a CML Counter(Ex: MC10EP016), is it as simple as flipping the signal lines before entering the counter? ...
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50 views

connecting 6 bit 1 channel LVDS LCD to 6 bit 2 channel or 8 bit 1 channel LCD Universal Driver

I had an old laptop LCD screen with part number N154I2-L05 . It has 6 bit 1 channel LVDS connector input slot. so I have decided to use it instead of letting covered in dust, and I ordered an ...
3
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1answer
115 views

Maximum length of high-speed LVDS cable in automotive environment versus using SerDes

I would like to connect a small TFT display that uses LVDS, 4 channels for data and 1 channel for clock. Data rate is maximum 200 Mbps per lane. Very strict EMC requirements are applicable, namely ...
2
votes
1answer
50 views

Debugging dual LVDS display panel color issue

I'm on TI's AM5708 platform (custom board) trying to drive this Full HD panel via TI's DS90C387 Dual-Pixel Display Interface. The SoC outputs 24bit RGB into ...
0
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0answers
62 views

Connecting BLVDS or M-LVDS to LVDS receivers

I want to distribute 8 LVDS signals via a multiDROP bus hierarchy on a backplane board with the signal source in the center and 6 ports for slave boards to the right and another 6 ports to the left. ...
0
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0answers
25 views

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer Hello there, First of all I'm a beginner in FPGA programming and i don't know if my whole approach to this is wrong. I'm currently trying to ...
0
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1answer
186 views

Differential Pair Reference Plane Coupling

I am routing LVDS pair on a flex board. The signal is 264MHz. I used Saturn PCB design to calculate width and spacing between conductors. The targeted impedance for diff pair is 100 ohms, which is ...
0
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0answers
107 views

LVDS driver signals measurement

This is background: I have a self-made PCB, which is used to connect the camera via the CameraLink interface. When I connected everything together, it turns out that the camera is signalling me via ...
0
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1answer
132 views

LVDS display troubleshooting

I am currently working on a prototype connecting a SOC-board (Samsung ARTIK530) to a LVDS LCD display (DT070BTFT-PTS1). The display shows a very (!) distorted picture. I have tried fixing it using ...
0
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1answer
238 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
1
vote
1answer
241 views

Does LVDS always need 100 ohm differential impedance?

LVDS pairs need 100 ohms differential impedance. However, I am having trouble achieving that in my design. My design requires that the pairs travel over very thin flexible PCB, about 50mm total ...
1
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1answer
140 views

Locating pairs on an LVDS cable

For a 2-row connector intended to interface a cable to a PCB, which method is preferable for twisted pair LVDS signals? Horizontal Pairs: LVDS1-    LVDS1+    ...
0
votes
1answer
81 views

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V?

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V? Is there an easy way to shift the common mode voltage to 0V?
3
votes
1answer
203 views

How to “Pull Down” LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
0
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1answer
91 views

How to use 0.1 inch header footprint for high speed signals?

I have a board which has a dual 0.1 inch header footprint (the totally standard kind you see everywhere). Trouble is, this carries a fast 300-500 Mbit DDR LVDS signal (!!) to another board. Okay, so ...
0
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1answer
287 views

What lvds connector do I have

Can someone help me find out what type of LVDS cable I have and point me in the direction of an adaptor to HDMI. Thanks. Backstory: I recently had to throw out an old Sony Vaio All in one PC and ...
2
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1answer
285 views

SPI with differential signaling

Standard SPI uses single-ended signals. Is it possible that a communication uses SPI protocol but the signals are physically LVDS?
2
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1answer
169 views

Non-coaxial 50 ohm cable for LVDS

I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram. In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and ...
0
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2answers
103 views

LVDS Flex Cables - Optimizing Trace Layout for 10 GbE

I want to run a 10 Gigabit Ethernet (GbE) signal over a 15 pin LVDS flex cable like this one: My PCB will accept an RJ45 connector, and those traces will run over the PCB to the flex jumper, then ...
0
votes
1answer
243 views

Setting DC-bias on LVDS receiver with internal 100ohm differential termination

Here is the setup : simulate this circuit – Schematic created using CircuitLab RX channel is routed as 100ohm controlled impedance. FPGA input pins are LVDS IOs. I want to apply a DC bias of +...
0
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0answers
177 views

Alternatives to RJ45 ethernet connections?

I have a system where two boards need to communicate through a serial bus with several lines --- rates are in the order of up to 3MHz. The boards will be several meters away (say, 3 to 5 meters / 10 ...
1
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0answers
69 views

LVDS CLK Input Appropriate Here?

I'm working with an MCP37231/21-200 that requires a differential input for the clock. I need to know if I can use an LVDS input to drive my clock. The output clock is specified to have LVDS ...
0
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1answer
240 views

does the orientation of a choke in an LVDS application matter?

I found the diagram below online while looking for information on the orientation of a choke I intend to use in an LVDS application. Does the orientation of the choke matter? The part I intend to use ...
1
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0answers
459 views

Interfacing LVDS to 1.2V IO Bank (e.g. POD12 or SSTL12)

I am currently working with an Arria 10 device (specifically a ReflexCES A10 SoM Indus module). The GPIO pins of the device are split into IO banks with specific VCCIO voltages controlling the banks. ...
1
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2answers
436 views

Using old laptop LCD as external VGA screen [closed]

I have a few old laptops with good LCD panels that I wish to salvage and use as external VGA screen on other computers. I'am no expert in electronics but I work with computers and know the basics of ...
0
votes
1answer
70 views

FMC connector AC701

I am using the AC701 I need to use the pins of the FMC connector to connect the outputs of 8 ADC to the inputs of the FPGA ( 41 pairs of LVDS signals) I need to use the pins of the FMC connector to ...
-1
votes
1answer
85 views

LVDS inputs and TTL outputs in design

I have a design and most of the entry ports are the outputs of an ADC these outputs are LVDS. My question is how do i declare the inputs of my FPGA as LVDS signals? And how to declare the outputs has ...
1
vote
1answer
102 views

Which is better, less crosstalk or less skew?

I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other ...
1
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2answers
132 views

Difference between LVDS and “Low Power LVDS”

It sounds like a double emphasis but indeed, pin 25 of the LTC2323 (http://www.linear.com/product/LTC2323-16) I lets me choose between: CMOS (GND) LVDS (IOVDD) Low-Power LVDS (leave floating) As ...
8
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3answers
1k views

Via in between differential traces - how bad is it?

I'm working on a board that has some LVDS 2.5 signals. All the guides I've read about board layout say not to put vias in between the differential traces, eg this guide In a few cases it would be a ...
0
votes
1answer
784 views

LVDS signal to FPGA [closed]

I need to receive 42 pairs of LVDS signals to a FPGA. All i want is that the FPGA converts the differential pairs in normal std_logic signals. And i need to choose a xilinx FPGA with enough pins that ...
1
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1answer
165 views

How to send logic low to LVDS?

I have a chip that takes LVDS inputs. It has a very large number of inputs and I'd like to set most of them to zero (or one) while prototyping. They can't be left open/floating. What is a good way ...
1
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1answer
1k views

What should the single-ended impedance be for LVDS?

For LVDS, it seems like the traces are usually specified as 100 ohm differential impedance. What should the single end impedance be from each trace to ground? I'm looking at PCB impedance ...
0
votes
1answer
329 views

LVDS clock signal EMI

I am working on a project in which we have an an i.MX53 to driving an LCD through the LVDS connector and we fail the required EMC criteria. There are multiple peaks at 40 MHz intervals (starting at ...
0
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1answer
909 views

17" screen panel and 2 channel 8 bit 40 pins LVDS connector on motherboard

I was looking for 17" screen panel for my motherboard. And after tones of datasheets I couldn't find any that may fit my 2ch 8bit 40pin LVDS connector. Most panels have 2ch 6bit 30/40pin or I found ...
3
votes
2answers
418 views

How to measure/show MIPI-DSI 4 lane signals on DSO/oscilloscope?

I want to measure/show the MIPI-DSI 4 lane signals on an oscilloscope. There is MIPI type display has been connected with LVDS-to-MIPI converter. I want to measure the signals at the output side of ...
2
votes
2answers
135 views

VHDL many .ucf files or not

I have a very basic question about VHDL. Do we need a separate .ucf file for each .vhd file or not? The reason I am having many .vhd files because each of the entity specifies a different interface. ...
2
votes
1answer
536 views

Balun single-ended 50 Ohm to LVDS 100 ohm conversion

I have an LVDS differential 100OHM signal which I want to convert to a single-ended 50 OHM signal. I want to use a BALUN for this conversion. What kind of BALUN should I use here? Some BALUNs have 1:...
1
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2answers
998 views

Effect of swapping positive and negative traces in a LVDS differential pair, for both clock lines and data lines?

For an LVDS signal, I am trying to understand what will happen if the transmitter's positive and negative sides of the differential pair get swapped on their way to the receiver. In other words you ...
0
votes
1answer
141 views

Poor man's clock MUX with an LVDS input

I want to send two different 10MHz clock signals to a device. My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC. The first source have ...
3
votes
1answer
417 views

Convert single-ended (analog) signal to LVDS

I am looking for recommendation of a converter/cable to convert a digital pulse to LVDS. Attachment is the schematic of the whole design. Basically, my task is to measure the photon arrival time, ...
1
vote
1answer
265 views

How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
1
vote
1answer
715 views

What type of cable/connector is this 30 PIN LCD display cable?

I need help identifying the type of cable this is. It is used to connect an LCD display panel to a processor board. The width of each connector is about 15 mm and each end attaches to a 30 PIN ...
0
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0answers
58 views

24-30pin connector for digital picture frame

Hey all I have 3 27" lcd panels that I will be making digital picture frames out of and I am looking for advice on what i can use in order to use only 1 cable going to the digital picture frame since ...
2
votes
1answer
303 views

LVDS-SPI bridge, asic or FPGA, and what FPGA

I'm going to develop a camera utilizing the NanEye 2D image sensor. This has LVDS interface. I'm using a MCU for data processing that does not have LVDS interface, but it has SPI and I2C. Therefore I ...
0
votes
1answer
65 views

How can I connect this LCD panel to my Raspberry Pi?

I want connect my Raspberry Pi to this LCD. How I can do this? I have read about lvds controller. Is this the solution to my problem? Could someone help me in my research? I'm Italian and I'm ...
0
votes
1answer
500 views

LVDS cable between a camera and a FPGA

I'm using a development kit which is made a camera board and a FPGA board. So far, in this kit, the camera board is directly plugged onto the FPGA board. I have tested a new code for my FPGA. ...
1
vote
1answer
147 views

Cables for LVDS RS-644

To use SPI over a 5m long cable we plan to use LVDS RS-644 which calls for a twisted-pair cable with 100ohm characteristic impedance. Evaluating our cable options we looked into Cat5 cable (...
0
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2answers
162 views

Interfacing an LVDS driver with an LVPECL receiver

I'm trying to understand how the below circuit allows interfacing LVDS levels with LVPECL levels. Assuming: Driver: Voh = 1.4V, Vol = 1V, Vcm = 1.2V Receiver: VBB = 2V After the transmission ...

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