Questions tagged [lvds]

LVDS stands for Low Voltage Differential Signalling. It is a popular high-speed (>100 Mb/s) way to connect chips.

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Difference between LVDS SerDes and FPD-Link III SerDes?

I'm new to the world of video interfaces and am working on a project in which parallelized video stream data is transmitted and subsequently received by processing components on the other end of an ...
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36 views

How would you connect a LVDS display to a laptop motherboard supporting natively a different display?

I'm planning a project of building a 4:3 laptop based on existing (modern) components. As 4:3 displays are not manufactured anymore the idea is to take one from a old laptop, like a thinkpad T60. Then ...
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LVDS connections for V29 LCD driver board

I am trying use LP154W02 B1K7 LCD (from Acer 5670 laptop) with V29 LCD driver board. As per datasheet, LP154W02 B1K7 LCD is 2 channel 6 bit, 3.3v, 1680x1050 resultion. Original LVDS connections from ...
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72 views

Could I use a 2Ch 6bit LVDS cable on an LCD that uses 1Ch 6 bit LVDS?

this is my first question here so I'll try to make it as clear as possible. I've bought a T.V53.03 control board to use with an old laptop display I have at my home. After searching for the display ...
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What is the expected output of an LVDS IO cell of an FPGA (or just simulation) when the P and N pad inputs are both the same logical value?

I am curious what, in general, the output would be of an LVDS signal when both inputs are the same voltage level. So if the truth table is: ...
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39 views

What is the purpose of having two type of output interfaces on this ADC?

The ADS4126 comes with a Double Data Rate (DDR) LVDS output interface and a I have following questions: What criteria is used to decide which one of the two to use? Can both be used to read the ADC ...
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Detecting activity on LVDS line

For some test equipment I have an LVDS line running at 100 Mbps. I would like to make an Arduino Due (because I use this for other monitoring in the test) detect activity on the LVDS line. Using a (...
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44 views

LVDS25 LVDS33 and LVDS18

I am a little confused about the definition of LVDS_18, LVDS_25 and LVDS_33. I thought LVDS simply had a VCM of 1.2V. If a clock calls for LVDS25, can I run an LVDS clock from a part that is being ...
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50 views

9-pin micro-d connector for LVDS signals

Has anyone utilized 9-pin micro-d connectors for driving and receiving LVDS signals? I am running the LVDS at 100 Mbps for 20-30 inches. I am using a vertical pcb mounted connector 380-009-213 from ...
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70 views

Using DB9 connectors for LVDS signals

Has anyone utilized 9-pin DB9 connectors for driving and receiving LVDS signals? I wanted to use Micro-D connectors on a board I am developing but they take too long to get. Since DB9 connectors are ...
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507 views

How do I configure the wires in the LVDS 30 pin cable?

I explain: I have a screen that I want to use as a monitor. I have purchased an LCD controller board and a LVDS cable I need someone to help me to rewire the LVDS cable. I have the input terminal pin ...
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LVDS (from PTN3460) driven display shows fringed lines

I am developing a board which converts DisplayPort to LVDS. The LVDS is put through a PCIe switch and then fed to an APIX transmitter, which connects to the display. There's a second video path going ...
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51 views

Connecting CMOS sensor to (far away) PCB: understanding cable length

The problem is a bit complex due to the number of unknown parameters and my inexperience. I need a way to determine how far I can put the PCB from the sensor without problems in the transmission of ...
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107 views

ADC with parallel DDR LVDS interface and also a parallel CMOS interface

The ADS4126 is a 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC). Its data rate is too high for it to be read out using something like SPI or I2C. It does use SPI for control purpose though. The ...
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71 views

Signal 'bounces' back to high

I transmit a signal using LVDS over a CAT6 ethernet cable. However, instead of coming through clean, it always 'bounces' back to the high state: (Pink is the input and yellow is the output) (Sorry ...
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82 views

Impedance Mismatch of LVDS Differential Pairs

A mistake was made when designing a set of mother and daughter PCBs, resulting the daughter board to have its LVDS pairs at ~100Ω differential impedance, while the motherboard ~90Ω. The receiver, ...
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62 views

How to generate positive and negative power supplies from a single supply with high current driving capability?

I am trying to build a 1553 military standard bus transceiver (analog front end) and I am required to use a single power supply of 3.3 V. To be able to receive, my comparators need supplies of +/- 3.3-...
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51 views

LVDS length pair matching (HSD connectors)

For a high speed interconnect (3 - 6GBit/sec over a single lvds pair) I attempted to length match the LVDS data pair as accurate as possible. Something I have failed to get information on is the ...
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79 views

Understanding Common mode voltage

I am trying to understand common mode voltage a little bit fundamentally (only with electronic devices and no math). I watched this Youtube Video to understand common mode and differential mode ...
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117 views

Universal LVDS controller board

I am trying to salvage a Chimei Innolux V236BJ1 LE1 panel from an old LG TV. Planning to use T.RD8503.03 but I can't find the datasheet. I need it to see if the pinout are compatible, or if not, to ...
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132 views

LVDS data rate to TFT

I have a two LVDS Ports (A & B) coming from deserializers connected to a 10.25" TFT display. lvdsaclkp, lvdsaclkn, lvdsa[0:3]p/n lvdsbclkp, lvdsbclkn, lvdsb[0:3]p/n VESA: JEITA: What is the ...
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Circuit not working: Differential impedance, or skew, or a different problem responsible?

For a hobby project, I am designing a circuit that converts displayport to APIX2, which is a serializer protocol used in cars' infotainment systems, mostly BMW. This is done by an INAP375T IC, APIX is ...
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79 views

Interfacing LVDS into LVPECL with DC coupling

We are using TI ADC ADC12DJ3200 in our design. Now this ADC has input pins for timestamping the ADC data. This timestamp input supports LVPECL standard but the allowed common mode voltage is only 0....
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Why a potential divider at high speed LVDS clock outputs?

I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below. Will this ...
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From where does the Common Mode 1.2V of LVDS comes from?

I am trying to understand the LVDS signalling. But from where do we get the 1.2V common mode voltage? Please help. Thanks
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Can I use a deserializer without a matching serializer?

I am trying to connect an LVDS output to an 18-bit parallel input. Ser/des ICs like this all state on their datasheets (like on page 12 of the linked datasheet) that before they are able to function ...
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65 views

Signal conversion LVDS, RS422 and LVTTL

What are all the parameters required to LVDS to lvttl, RS422 to LVTTL and LVTTL to LVDS and RS422 signal conversion?
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DS90UB948-Q1 internal pattern generator

Does anyone have prior experience with DS90UB948-Q1 FPD-Link III Deserializer deserialiser from Texas Instruments ? I am trying to configure the internal pattern generator block sending I2C commands. ...
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2k views

Connecting 21" screen to LVDS connector on motherboard

I'm working in an "All-in-One pc" project. For that, I have an old Dell laptop (which only works with DC adapter) and a 21" LG monitor. My question is: How can I connect the LCD panel directly on the ...
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100 views

Can CML differential signal lines be flipped to act as a NOT gate?

If I want to invert a CML differential D-Flip Flop (Ex: hmc747lc3c) output before entering into a CML Counter(Ex: MC10EP016), is it as simple as flipping the signal lines before entering the counter? ...
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698 views

Maximum length of high-speed LVDS cable in automotive environment versus using SerDes

I would like to connect a small TFT display that uses LVDS, 4 channels for data and 1 channel for clock. Data rate is maximum 200 Mbps per lane. Very strict EMC requirements are applicable, namely ...
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179 views

Debugging dual LVDS display panel color issue

I'm on TI's AM5708 platform (custom board) trying to drive this Full HD panel via TI's DS90C387 Dual-Pixel Display Interface. The SoC outputs 24bit RGB into ...
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418 views

Differential Pair Reference Plane Coupling

I am routing LVDS pair on a flex board. The signal is 264MHz. I used Saturn PCB design to calculate width and spacing between conductors. The targeted impedance for diff pair is 100 ohms, which is ...
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234 views

LVDS driver signals measurement

This is background: I have a self-made PCB, which is used to connect the camera via the CameraLink interface. When I connected everything together, it turns out that the camera is signalling me via ...
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411 views

LVDS display troubleshooting

I am currently working on a prototype connecting a SOC-board (Samsung ARTIK530) to a LVDS LCD display (DT070BTFT-PTS1). The display shows a very (!) distorted picture. I have tried fixing it using ...
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719 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
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626 views

Does LVDS always need 100 ohm differential impedance?

LVDS pairs need 100 ohms differential impedance. However, I am having trouble achieving that in my design. My design requires that the pairs travel over very thin flexible PCB, about 50mm total ...
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245 views

Locating pairs on an LVDS cable

For a 2-row connector intended to interface a cable to a PCB, which method is preferable for twisted pair LVDS signals? Horizontal Pairs: LVDS1-    LVDS1+    ...
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142 views

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V?

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V? Is there an easy way to shift the common mode voltage to 0V?
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385 views

How to “Pull Down” LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
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220 views

How to use 0.1 inch header footprint for high speed signals?

I have a board which has a dual 0.1 inch header footprint (the totally standard kind you see everywhere). Trouble is, this carries a fast 300-500 Mbit DDR LVDS signal (!!) to another board. Okay, so ...
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554 views

What lvds connector do I have

Can someone help me find out what type of LVDS cable I have and point me in the direction of an adaptor to HDMI. Thanks. Backstory: I recently had to throw out an old Sony Vaio All in one PC and ...
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1k views

SPI with differential signaling

Standard SPI uses single-ended signals. Is it possible that a communication uses SPI protocol but the signals are physically LVDS?
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547 views

Non-coaxial 50 ohm cable for LVDS

I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram. In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and ...
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250 views

LVDS Flex Cables - Optimizing Trace Layout for 10 GbE

I want to run a 10 Gigabit Ethernet (GbE) signal over a 15 pin LVDS flex cable like this one: My PCB will accept an RJ45 connector, and those traces will run over the PCB to the flex jumper, then ...
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426 views

Setting DC-bias on LVDS receiver with internal 100ohm differential termination

Here is the setup : simulate this circuit – Schematic created using CircuitLab RX channel is routed as 100ohm controlled impedance. FPGA input pins are LVDS IOs. I want to apply a DC bias of +...
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394 views

Alternatives to RJ45 ethernet connections?

I have a system where two boards need to communicate through a serial bus with several lines --- rates are in the order of up to 3MHz. The boards will be several meters away (say, 3 to 5 meters / 10 ...
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110 views

LVDS CLK Input Appropriate Here?

I'm working with an MCP37231/21-200 that requires a differential input for the clock. I need to know if I can use an LVDS input to drive my clock. The output clock is specified to have LVDS ...
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508 views

does the orientation of a choke in an LVDS application matter?

I found the diagram below online while looking for information on the orientation of a choke I intend to use in an LVDS application. Does the orientation of the choke matter? The part I intend to use ...
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Interfacing LVDS to 1.2V IO Bank (e.g. POD12 or SSTL12)

I am currently working with an Arria 10 device (specifically a ReflexCES A10 SoM Indus module). The GPIO pins of the device are split into IO banks with specific VCCIO voltages controlling the banks. ...