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Questions tagged [lvds]

LVDS stands for Low Voltage Differential Signalling. It is a popular high-speed (>100 Mb/s) way to connect chips.

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36 views

LVDS data rate to TFT

I have a two LVDS Ports (A & B) coming from deserializers connected to a 10.25" TFT display. lvdsaclkp, lvdsaclkn, lvdsa[0:3]p/n lvdsbclkp, lvdsbclkn, lvdsb[0:3]p/n VESA: JEITA: What is the ...
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Circuit not working: Differential impedance, or skew, or a different problem responsible?

For a hobby project, I am designing a circuit that converts displayport to APIX2, which is a serializer protocol used in cars' infotainment systems, mostly BMW. This is done by an INAP375T IC, APIX is ...
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39 views

Interfacing LVDS into LVPECL with DC coupling

We are using TI ADC ADC12DJ3200 in our design. Now this ADC has input pins for timestamping the ADC data. This timestamp input supports LVPECL standard but the allowed common mode voltage is only 0....
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58 views

Why a potential divider at high speed LVDS clock outputs?

I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below. Will this ...
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From where does the Common Mode 1.2V of LVDS comes from?

I am trying to understand the LVDS signalling. But from where do we get the 1.2V common mode voltage? Please help. Thanks
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Can I use a deserializer without a matching serializer?

I am trying to connect an LVDS output to an 18-bit parallel input. Ser/des ICs like this all state on their datasheets (like on page 12 of the linked datasheet) that before they are able to function ...
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34 views

Signal conversion LVDS, RS422 and LVTTL

What are all the parameters required to LVDS to lvttl, RS422 to LVTTL and LVTTL to LVDS and RS422 signal conversion?
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DS90UB948-Q1 internal pattern generator

Does anyone have prior experience with DS90UB948-Q1 FPD-Link III Deserializer deserialiser from Texas Instruments ? I am trying to configure the internal pattern generator block sending I2C commands. ...
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102 views

LVDS single channel to LVDS dual channel conversion

I have an embedded linux board with a Nvidia Tegra K1 chip (Toradex TK1) with a single channel LVDS output up to 1920×1200 @ 24bpp. I would like to use the board with a dual channel LVDS display ...
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155 views

Connecting 21" screen to LVDS connector on motherboard

I'm working in an "All-in-One pc" project. For that, I have an old Dell laptop (which only works with DC adapter) and a 21" LG monitor. My question is: How can I connect the LCD panel directly on the ...
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66 views

Test LVDS signals

I am wondering how I could test LVDS signals on a PCB using a scope. The most straight forward answer would be to measure on the termination resistor points, although this isn't possible, since the ...
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44 views

sub-LVDS to CSI-2

I am going to make two prototype boards with the same functionality but using different components. For the first prototype board, my question is related to this topic. The imaging sensors I'll use ...
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2answers
69 views

Can CML differential signal lines be flipped to act as a NOT gate?

If I want to invert a CML differential D-Flip Flop (Ex: hmc747lc3c) output before entering into a CML Counter(Ex: MC10EP016), is it as simple as flipping the signal lines before entering the counter? ...
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238 views

connecting 6 bit 1 channel LVDS LCD to 6 bit 2 channel or 8 bit 1 channel LCD Universal Driver

I had an old laptop LCD screen with part number N154I2-L05 . It has 6 bit 1 channel LVDS connector input slot. so I have decided to use it instead of letting covered in dust, and I ordered an ...
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1answer
285 views

Maximum length of high-speed LVDS cable in automotive environment versus using SerDes

I would like to connect a small TFT display that uses LVDS, 4 channels for data and 1 channel for clock. Data rate is maximum 200 Mbps per lane. Very strict EMC requirements are applicable, namely ...
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1answer
120 views

Debugging dual LVDS display panel color issue

I'm on TI's AM5708 platform (custom board) trying to drive this Full HD panel via TI's DS90C387 Dual-Pixel Display Interface. The SoC outputs 24bit RGB into ...
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115 views

Connecting BLVDS or M-LVDS to LVDS receivers

I want to distribute 8 LVDS signals via a multiDROP bus hierarchy on a backplane board with the signal source in the center and 6 ports for slave boards to the right and another 6 ports to the left. ...
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Using ALTLVDS_TX megafunction with a DS90CR485 Serializer

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer Hello there, First of all I'm a beginner in FPGA programming and i don't know if my whole approach to this is wrong. I'm currently trying to ...
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286 views

Differential Pair Reference Plane Coupling

I am routing LVDS pair on a flex board. The signal is 264MHz. I used Saturn PCB design to calculate width and spacing between conductors. The targeted impedance for diff pair is 100 ohms, which is ...
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153 views

LVDS driver signals measurement

This is background: I have a self-made PCB, which is used to connect the camera via the CameraLink interface. When I connected everything together, it turns out that the camera is signalling me via ...
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1answer
208 views

LVDS display troubleshooting

I am currently working on a prototype connecting a SOC-board (Samsung ARTIK530) to a LVDS LCD display (DT070BTFT-PTS1). The display shows a very (!) distorted picture. I have tried fixing it using ...
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410 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
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395 views

Does LVDS always need 100 ohm differential impedance?

LVDS pairs need 100 ohms differential impedance. However, I am having trouble achieving that in my design. My design requires that the pairs travel over very thin flexible PCB, about 50mm total ...
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171 views

Locating pairs on an LVDS cable

For a 2-row connector intended to interface a cable to a PCB, which method is preferable for twisted pair LVDS signals? Horizontal Pairs: LVDS1-    LVDS1+    ...
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108 views

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V?

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V? Is there an easy way to shift the common mode voltage to 0V?
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283 views

How to “Pull Down” LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
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113 views

How to use 0.1 inch header footprint for high speed signals?

I have a board which has a dual 0.1 inch header footprint (the totally standard kind you see everywhere). Trouble is, this carries a fast 300-500 Mbit DDR LVDS signal (!!) to another board. Okay, so ...
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423 views

What lvds connector do I have

Can someone help me find out what type of LVDS cable I have and point me in the direction of an adaptor to HDMI. Thanks. Backstory: I recently had to throw out an old Sony Vaio All in one PC and ...
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1answer
526 views

SPI with differential signaling

Standard SPI uses single-ended signals. Is it possible that a communication uses SPI protocol but the signals are physically LVDS?
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1answer
260 views

Non-coaxial 50 ohm cable for LVDS

I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram. In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and ...
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2answers
147 views

LVDS Flex Cables - Optimizing Trace Layout for 10 GbE

I want to run a 10 Gigabit Ethernet (GbE) signal over a 15 pin LVDS flex cable like this one: My PCB will accept an RJ45 connector, and those traces will run over the PCB to the flex jumper, then ...
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1answer
332 views

Setting DC-bias on LVDS receiver with internal 100ohm differential termination

Here is the setup : simulate this circuit – Schematic created using CircuitLab RX channel is routed as 100ohm controlled impedance. FPGA input pins are LVDS IOs. I want to apply a DC bias of +...
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246 views

Alternatives to RJ45 ethernet connections?

I have a system where two boards need to communicate through a serial bus with several lines --- rates are in the order of up to 3MHz. The boards will be several meters away (say, 3 to 5 meters / 10 ...
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91 views

LVDS CLK Input Appropriate Here?

I'm working with an MCP37231/21-200 that requires a differential input for the clock. I need to know if I can use an LVDS input to drive my clock. The output clock is specified to have LVDS ...
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326 views

does the orientation of a choke in an LVDS application matter?

I found the diagram below online while looking for information on the orientation of a choke I intend to use in an LVDS application. Does the orientation of the choke matter? The part I intend to use ...
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705 views

Interfacing LVDS to 1.2V IO Bank (e.g. POD12 or SSTL12)

I am currently working with an Arria 10 device (specifically a ReflexCES A10 SoM Indus module). The GPIO pins of the device are split into IO banks with specific VCCIO voltages controlling the banks. ...
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2answers
636 views

Using old laptop LCD as external VGA screen [closed]

I have a few old laptops with good LCD panels that I wish to salvage and use as external VGA screen on other computers. I'am no expert in electronics but I work with computers and know the basics of ...
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1answer
86 views

FMC connector AC701

I am using the AC701 I need to use the pins of the FMC connector to connect the outputs of 8 ADC to the inputs of the FPGA ( 41 pairs of LVDS signals) I need to use the pins of the FMC connector to ...
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1answer
98 views

LVDS inputs and TTL outputs in design

I have a design and most of the entry ports are the outputs of an ADC these outputs are LVDS. My question is how do i declare the inputs of my FPGA as LVDS signals? And how to declare the outputs has ...
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1answer
111 views

Which is better, less crosstalk or less skew?

I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other ...
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2answers
162 views

Difference between LVDS and “Low Power LVDS”

It sounds like a double emphasis but indeed, pin 25 of the LTC2323 (http://www.linear.com/product/LTC2323-16) I lets me choose between: CMOS (GND) LVDS (IOVDD) Low-Power LVDS (leave floating) As ...
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Via in between differential traces - how bad is it?

I'm working on a board that has some LVDS 2.5 signals. All the guides I've read about board layout say not to put vias in between the differential traces, eg this guide In a few cases it would be a ...
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1k views

LVDS signal to FPGA [closed]

I need to receive 42 pairs of LVDS signals to a FPGA. All i want is that the FPGA converts the differential pairs in normal std_logic signals. And i need to choose a xilinx FPGA with enough pins that ...
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1answer
199 views

How to send logic low to LVDS?

I have a chip that takes LVDS inputs. It has a very large number of inputs and I'd like to set most of them to zero (or one) while prototyping. They can't be left open/floating. What is a good way ...
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1answer
1k views

What should the single-ended impedance be for LVDS?

For LVDS, it seems like the traces are usually specified as 100 ohm differential impedance. What should the single end impedance be from each trace to ground? I'm looking at PCB impedance ...
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401 views

LVDS clock signal EMI

I am working on a project in which we have an an i.MX53 to driving an LCD through the LVDS connector and we fail the required EMC criteria. There are multiple peaks at 40 MHz intervals (starting at ...
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1k views

17" screen panel and 2 channel 8 bit 40 pins LVDS connector on motherboard

I was looking for 17" screen panel for my motherboard. And after tones of datasheets I couldn't find any that may fit my 2ch 8bit 40pin LVDS connector. Most panels have 2ch 6bit 30/40pin or I found ...
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2answers
523 views

How to measure/show MIPI-DSI 4 lane signals on DSO/oscilloscope?

I want to measure/show the MIPI-DSI 4 lane signals on an oscilloscope. There is MIPI type display has been connected with LVDS-to-MIPI converter. I want to measure the signals at the output side of ...
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2answers
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VHDL many .ucf files or not

I have a very basic question about VHDL. Do we need a separate .ucf file for each .vhd file or not? The reason I am having many .vhd files because each of the entity specifies a different interface. ...
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1answer
688 views

Balun single-ended 50 Ohm to LVDS 100 ohm conversion

I have an LVDS differential 100OHM signal which I want to convert to a single-ended 50 OHM signal. I want to use a BALUN for this conversion. What kind of BALUN should I use here? Some BALUNs have 1:...