Questions tagged [lvds]

LVDS stands for Low Voltage Differential Signalling. It is a popular high-speed (>100 Mb/s) way to connect chips.

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295 views

How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
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735 views

Balun single-ended 50 Ohm to LVDS 100 ohm conversion

I have an LVDS differential 100OHM signal which I want to convert to a single-ended 50 OHM signal. I want to use a BALUN for this conversion. What kind of BALUN should I use here? Some BALUNs have 1:...
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48 views

How to generate positive and negative power supplies from a single supply with high current driving capability?

I am trying to build a 1553 military standard bus transceiver (analog front end) and I am required to use a single power supply of 3.3 V. To be able to receive, my comparators need supplies of +/- 3.3-...
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240 views

LVDS display troubleshooting

I am currently working on a prototype connecting a SOC-board (Samsung ARTIK530) to a LVDS LCD display (DT070BTFT-PTS1). The display shows a very (!) distorted picture. I have tried fixing it using ...
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33 views

LVDS length pair matching (HSD connectors)

For a high speed interconnect (3 - 6GBit/sec over a single lvds pair) I attempted to length match the LVDS data pair as accurate as possible. Something I have failed to get information on is the ...
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43 views

Understanding Common mode voltage

I am trying to understand common mode voltage a little bit fundamentally (only with electronic devices and no math). I watched this Youtube Video to understand common mode and differential mode ...
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30 views

Universal LVDS controller board

I am trying to salvage a Chimei Innolux V236BJ1 LE1 panel from an old LG TV. Planning to use T.RD8503.03 but I can't find the datasheet. I need it to see if the pinout are compatible, or if not, to ...
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44 views

LVDS data rate to TFT

I have a two LVDS Ports (A & B) coming from deserializers connected to a 10.25" TFT display. lvdsaclkp, lvdsaclkn, lvdsa[0:3]p/n lvdsbclkp, lvdsbclkn, lvdsb[0:3]p/n VESA: JEITA: What is the ...
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23 views

Circuit not working: Differential impedance, or skew, or a different problem responsible?

For a hobby project, I am designing a circuit that converts displayport to APIX2, which is a serializer protocol used in cars' infotainment systems, mostly BMW. This is done by an INAP375T IC, APIX is ...
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473 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
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221 views

Poor man's clock MUX with an LVDS input

I want to send two different 10MHz clock signals to a device. My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC. The first source have ...
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48 views

Interfacing LVDS into LVPECL with DC coupling

We are using TI ADC ADC12DJ3200 in our design. Now this ADC has input pins for timestamping the ADC data. This timestamp input supports LVPECL standard but the allowed common mode voltage is only 0....
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347 views

Setting DC-bias on LVDS receiver with internal 100ohm differential termination

Here is the setup : simulate this circuit – Schematic created using CircuitLab RX channel is routed as 100ohm controlled impedance. FPGA input pins are LVDS IOs. I want to apply a DC bias of +...
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1answer
641 views

SPI with differential signaling

Standard SPI uses single-ended signals. Is it possible that a communication uses SPI protocol but the signals are physically LVDS?
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62 views

Why a potential divider at high speed LVDS clock outputs?

I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below. Will this ...
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72 views

From where does the Common Mode 1.2V of LVDS comes from?

I am trying to understand the LVDS signalling. But from where do we get the 1.2V common mode voltage? Please help. Thanks
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Can I use a deserializer without a matching serializer?

I am trying to connect an LVDS output to an 18-bit parallel input. Ser/des ICs like this all state on their datasheets (like on page 12 of the linked datasheet) that before they are able to function ...
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1answer
342 views

Maximum length of high-speed LVDS cable in automotive environment versus using SerDes

I would like to connect a small TFT display that uses LVDS, 4 channels for data and 1 channel for clock. Data rate is maximum 200 Mbps per lane. Very strict EMC requirements are applicable, namely ...
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1k views

STM32 FSMC/FMC and DS90CR285

I don't want to use an FPGA. I need to quickly put together a prototype that will relay DCMI data (small resolution camera sensor) to DS90CR285. Here performance doesn't matter that much – later it ...
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40 views

Signal conversion LVDS, RS422 and LVTTL

What are all the parameters required to LVDS to lvttl, RS422 to LVTTL and LVTTL to LVDS and RS422 signal conversion?
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DS90UB948-Q1 internal pattern generator

Does anyone have prior experience with DS90UB948-Q1 FPD-Link III Deserializer deserialiser from Texas Instruments ? I am trying to configure the internal pattern generator block sending I2C commands. ...
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170 views

LVDS single channel to LVDS dual channel conversion

I have an embedded linux board with a Nvidia Tegra K1 chip (Toradex TK1) with a single channel LVDS output up to 1920×1200 @ 24bpp. I would like to use the board with a dual channel LVDS display ...
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1answer
131 views

Debugging dual LVDS display panel color issue

I'm on TI's AM5708 platform (custom board) trying to drive this Full HD panel via TI's DS90C387 Dual-Pixel Display Interface. The SoC outputs 24bit RGB into ...
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312 views

Connecting 21" screen to LVDS connector on motherboard

I'm working in an "All-in-One pc" project. For that, I have an old Dell laptop (which only works with DC adapter) and a 21" LG monitor. My question is: How can I connect the LCD panel directly on the ...
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1answer
304 views

Differential Pair Reference Plane Coupling

I am routing LVDS pair on a flex board. The signal is 264MHz. I used Saturn PCB design to calculate width and spacing between conductors. The targeted impedance for diff pair is 100 ohms, which is ...
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79 views

Test LVDS signals

I am wondering how I could test LVDS signals on a PCB using a scope. The most straight forward answer would be to measure on the termination resistor points, although this isn't possible, since the ...
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1k views

17" screen panel and 2 channel 8 bit 40 pins LVDS connector on motherboard

I was looking for 17" screen panel for my motherboard. And after tones of datasheets I couldn't find any that may fit my 2ch 8bit 40pin LVDS connector. Most panels have 2ch 6bit 30/40pin or I found ...
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288 views

connecting 6 bit 1 channel LVDS LCD to 6 bit 2 channel or 8 bit 1 channel LCD Universal Driver

I had an old laptop LCD screen with part number N154I2-L05 . It has 6 bit 1 channel LVDS connector input slot. so I have decided to use it instead of letting covered in dust, and I ordered an ...
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51 views

sub-LVDS to CSI-2

I am going to make two prototype boards with the same functionality but using different components. For the first prototype board, my question is related to this topic. The imaging sensors I'll use ...
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1answer
596 views

LVDS cable between a camera and a FPGA

I'm using a development kit which is made a camera board and a FPGA board. So far, in this kit, the camera board is directly plugged onto the FPGA board. I have tested a new code for my FPGA. ...
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1answer
1k views

LVDS_25 voltage range

I understand that thee voltage level for LVDS standard has a typical offset voltage of 1.25V and voltage swing of 350mV. However, when I am doing some pin mapping on Xilinx FPGA, I encountered some ...
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73 views

Can CML differential signal lines be flipped to act as a NOT gate?

If I want to invert a CML differential D-Flip Flop (Ex: hmc747lc3c) output before entering into a CML Counter(Ex: MC10EP016), is it as simple as flipping the signal lines before entering the counter? ...
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438 views

Does LVDS always need 100 ohm differential impedance?

LVDS pairs need 100 ohms differential impedance. However, I am having trouble achieving that in my design. My design requires that the pairs travel over very thin flexible PCB, about 50mm total ...
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2answers
33k views

Connecting old webcam via USB

I have removed the webcam (Chicony CNF-9157) from an old laptop with the intention of connecting it up to a computer via USB. The webcam and the LCD were connected to the motherboard by LVDS. ...
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139 views

Connecting BLVDS or M-LVDS to LVDS receivers

I want to distribute 8 LVDS signals via a multiDROP bus hierarchy on a backplane board with the signal source in the center and 6 ports for slave boards to the right and another 6 ports to the left. ...
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38 views

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer Hello there, First of all I'm a beginner in FPGA programming and i don't know if my whole approach to this is wrong. I'm currently trying to ...
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162 views

LVDS driver signals measurement

This is background: I have a self-made PCB, which is used to connect the camera via the CameraLink interface. When I connected everything together, it turns out that the camera is signalling me via ...
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2answers
3k views

HDMI to LVDS converter [closed]

I am a software developer and now working on a touch screen based project of which I have no or little knowledge. Attached is the schematic of the circuit we obtained from chalkboard electronics. It ...
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1answer
2k views

How can I determine the the Wiring Configuration of an LVDT sensor?

I have an LVDT Sensor for measuring linear displacement similar to the one on the picture. The problem is that I don't have the manufacturer's wiring diagram and they don't provide it, because ...
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1answer
181 views

Locating pairs on an LVDS cable

For a 2-row connector intended to interface a cable to a PCB, which method is preferable for twisted pair LVDS signals? Horizontal Pairs: LVDS1-    LVDS1+    ...
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112 views

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V?

Why does LVDS (or any differential signaling for that matter) use a common mode voltage of 1.2V instead of 0V? Is there an easy way to shift the common mode voltage to 0V?
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314 views

How to “Pull Down” LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
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134 views

How to use 0.1 inch header footprint for high speed signals?

I have a board which has a dual 0.1 inch header footprint (the totally standard kind you see everywhere). Trouble is, this carries a fast 300-500 Mbit DDR LVDS signal (!!) to another board. Okay, so ...
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445 views

What lvds connector do I have

Can someone help me find out what type of LVDS cable I have and point me in the direction of an adaptor to HDMI. Thanks. Backstory: I recently had to throw out an old Sony Vaio All in one PC and ...
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1answer
310 views

Non-coaxial 50 ohm cable for LVDS

I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram. In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and ...
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2answers
160 views

LVDS Flex Cables - Optimizing Trace Layout for 10 GbE

I want to run a 10 Gigabit Ethernet (GbE) signal over a 15 pin LVDS flex cable like this one: My PCB will accept an RJ45 connector, and those traces will run over the PCB to the flex jumper, then ...
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Transmitting HDMI/DVI over an FPGA with no support for TMDS

I'm hoping to be able to output HDMI/DVI-D for my next FGPA project but my FPGA doesn't have native support for TMDS outputs. The FPGA is a Spartan 3E and I believe it only has support for LVDS ...
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1answer
662 views

LVDS signals having different ground reference with coupling capacitor

I'm simulating a LVDS driver connected to a LVDS receiver with a 100nF series coupling capacitor in between the +ve and -ve signal lines using the respective IBIS model of the same buffer. (DS25BR100 ...
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271 views

Alternatives to RJ45 ethernet connections?

I have a system where two boards need to communicate through a serial bus with several lines --- rates are in the order of up to 3MHz. The boards will be several meters away (say, 3 to 5 meters / 10 ...
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1answer
549 views

Convert single-ended (analog) signal to LVDS

I am looking for recommendation of a converter/cable to convert a digital pulse to LVDS. Attachment is the schematic of the whole design. Basically, my task is to measure the photon arrival time, ...