Questions tagged [lvds]

LVDS stands for Low Voltage Differential Signalling. It is a popular high-speed (>100 Mb/s) way to connect chips.

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31
votes
3answers
4k views

Correct place to attach shields for twisted pairs

I have two PCBs connected by a cable containing 5 sub-cables: 6v power through a custom made coaxial cable (similar to that found on laptop power supplies). 2x 100mbps LVDS through 100ohm impedance ...
11
votes
3answers
1k views

Measuring impedance

I am designing and building circuits which use 100Mb/s on a Low Voltage Differential Signaling (LVDS) bus. Some of these signals need to travel between PCBs on hand made cables. The problem is that I ...
10
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2answers
4k views

EMI Filtering on LVDS lines

This question is slightly related to: What's radiating on my PCB? These are Beckhoff's EtherCAT industrial IO modules. Each module is connected to its neighbours by 100mbps LVDS. Each module contains ...
10
votes
1answer
3k views

Homebrew differential 'scope probe

I may be able to get my hands on an old 600MHz LeCroy oscilloscope. However, it doesn't have any probes. Is it feasible to make an active differential probe for it using a high-speed op-amp, like the ...
8
votes
3answers
1k views

Via in between differential traces - how bad is it?

I'm working on a board that has some LVDS 2.5 signals. All the guides I've read about board layout say not to put vias in between the differential traces, eg this guide In a few cases it would be a ...
7
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2answers
7k views

Transmitting HDMI/DVI over an FPGA with no support for TMDS

I'm hoping to be able to output HDMI/DVI-D for my next FGPA project but my FPGA doesn't have native support for TMDS outputs. The FPGA is a Spartan 3E and I believe it only has support for LVDS ...
7
votes
1answer
820 views

Microstrip over power plane

I am designing a 4-layer PCB with 16 channels of LVDS (differential signalling, 480MHz). My layer stackup is Signal-GND-Power-Signal. A microstrip design for the LVDS channels is usually traces over a ...
6
votes
2answers
3k views

GND plane close to LVDS differential pair?

I have two LVDS differential pairs on my PCB, running from a connector. On the connector, I have the following sequence of nets: GND LVDS+ LVDS- GND LVDS+ LVDS- GND This is as I have seen suggested: ...
6
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2answers
464 views

Issue with TI comparator

I'm having trouble with a comparator from TI (LMH7322). I use it in the circuit shown in the attached image "Comparator_1". Outputs go to an FPGA. The circuit is supposed to take a single ended input ...
5
votes
1answer
342 views

LVDS signal distortion w.r.t switching power supply

We are using DC-DC switching regulators on board (switching freq. of regulators are ~540KHz). There is periodic noise in power/gnd at 540Khz. If we change the switching freq. of regulator, the ...
5
votes
2answers
582 views

Inner layer routing of LVDS traces in between ground vias

I have ground vias underneath an ADC on a multi-layer board for thermal relief. I am using inner layers to route the LVDS signals for the ADC. The image shows diff pairs on layer 4, which is in ...
4
votes
1answer
587 views

High-Speed PCB Design - Routing on Power Plane Layer?

I am working on designing my first high-speed PCB with 4 layers (in order): Top Layer: Single-ended/TTL signals Internal Layer 1: Power Plane (3.3V) Internal Layer 2: Ground Plane Bottom Layer: ...
4
votes
1answer
1k views

LVDS_25 voltage range

I understand that thee voltage level for LVDS standard has a typical offset voltage of 1.25V and voltage swing of 350mV. However, when I am doing some pin mapping on Xilinx FPGA, I encountered some ...
3
votes
1answer
2k views

How to connect LVDS signals to oscilloscope?

I have a bunch of LVDS signals on a PCB I want to look at with a scope (without wanting to tear my hair out). They range in speed from hundreds of Hz to ~200 MHz. How can I do this in a way that will ...
3
votes
2answers
20k views

How to route a LVDS clock from FPGA input to output?

Using VHDL, How is it possible to receive a pair of LVDS signals (say external clock) on the FPGA and route them to another pairs of pins to go out, without any modification? I have tried IBUFDS and ...
3
votes
2answers
551 views

How to measure/show MIPI-DSI 4 lane signals on DSO/oscilloscope?

I want to measure/show the MIPI-DSI 4 lane signals on an oscilloscope. There is MIPI type display has been connected with LVDS-to-MIPI converter. I want to measure the signals at the output side of ...
3
votes
1answer
1k views

Can I use an ethernet jack to send LVDS signals?

I would like to use an Ethernet jack for the form factor and CAT5e+ cable properties (shielded/twisted, characteristic impedance, etc) to send LVDS signals over a long length of cable (100+ ft). When ...
3
votes
1answer
523 views

networking platform to meet the IEC61850 sampled value requirements

I've developed a linux based simulator of the IEC 61850 sampled value publisher, even with RT linux I still can't meet the requirement to publish a message with MTU =-1500, every 1uS on a PC platform. ...
3
votes
1answer
130 views

Debugging dual LVDS display panel color issue

I'm on TI's AM5708 platform (custom board) trying to drive this Full HD panel via TI's DS90C387 Dual-Pixel Display Interface. The SoC outputs 24bit RGB into ...
3
votes
1answer
312 views

How to “Pull Down” LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
3
votes
1answer
630 views

SPI with differential signaling

Standard SPI uses single-ended signals. Is it possible that a communication uses SPI protocol but the signals are physically LVDS?
3
votes
1answer
547 views

Convert single-ended (analog) signal to LVDS

I am looking for recommendation of a converter/cable to convert a digital pulse to LVDS. Attachment is the schematic of the whole design. Basically, my task is to measure the photon arrival time, ...
3
votes
1answer
693 views

Corrupt LVDS Display

We are using an Advantech PCM-3363 PC104 board to drive a NLT Technologies NL10276BC13-01C LVDS Display in an embedded device. While everything works fine usually, the display sometimes is corrupt. ...
3
votes
1answer
338 views

Maximum length of high-speed LVDS cable in automotive environment versus using SerDes

I would like to connect a small TFT display that uses LVDS, 4 channels for data and 1 channel for clock. Data rate is maximum 200 Mbps per lane. Very strict EMC requirements are applicable, namely ...
2
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2answers
33k views

Connecting old webcam via USB

I have removed the webcam (Chicony CNF-9157) from an old laptop with the intention of connecting it up to a computer via USB. The webcam and the LCD were connected to the motherboard by LVDS. ...
2
votes
2answers
72 views

Can CML differential signal lines be flipped to act as a NOT gate?

If I want to invert a CML differential D-Flip Flop (Ex: hmc747lc3c) output before entering into a CML Counter(Ex: MC10EP016), is it as simple as flipping the signal lines before entering the counter? ...
2
votes
2answers
155 views

VHDL many .ucf files or not

I have a very basic question about VHDL. Do we need a separate .ucf file for each .vhd file or not? The reason I am having many .vhd files because each of the entity specifies a different interface. ...
2
votes
1answer
150 views

what is the voltage direction and current direction of LVDS signal at particular time?

What is the voltage and current direction LVDS signal (how it is related) ? i.e at a time (t1) there is only one current direction and one voltage ( D+ or D-)
2
votes
1answer
870 views

Signal reflections at the driver?

This question is related to How do I use directional couplers on a differential signal? I understand that if I have an impedance mismatch at the end of a signal cable, E.G. from a terminator which ...
2
votes
1answer
304 views

Non-coaxial 50 ohm cable for LVDS

I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram. In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and ...
2
votes
1answer
330 views

LVDS-SPI bridge, asic or FPGA, and what FPGA

I'm going to develop a camera utilizing the NanEye 2D image sensor. This has LVDS interface. I'm using a MCU for data processing that does not have LVDS interface, but it has SPI and I2C. Therefore I ...
2
votes
2answers
860 views

How do I use directional couplers on a differential signal?

I understand how a directional coupler can be used to measure signals travelling in one direction on a wire. What I don't understand is exactly how this would work on a differential signal, E.G. LVDS (...
2
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0answers
32 views

LVDS length pair matching (HSD connectors)

For a high speed interconnect (3 - 6GBit/sec over a single lvds pair) I attempted to length match the LVDS data pair as accurate as possible. Something I have failed to get information on is the ...
2
votes
1answer
733 views

Balun single-ended 50 Ohm to LVDS 100 ohm conversion

I have an LVDS differential 100OHM signal which I want to convert to a single-ended 50 OHM signal. I want to use a BALUN for this conversion. What kind of BALUN should I use here? Some BALUNs have 1:...
1
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2answers
1k views

Effect of swapping positive and negative traces in a LVDS differential pair, for both clock lines and data lines?

For an LVDS signal, I am trying to understand what will happen if the transmitter's positive and negative sides of the differential pair get swapped on their way to the receiver. In other words you ...
1
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2answers
1k views

How to Send Video from a Raspberry Pi (HDMI) to 20 pin LVDS

Through shenanigans, I have come to possess 4 small LCD screens. I've found the pin-out for video data on page 12 of this datasheet. I think it's LVDS. I'd like to know what I need to learn to be able ...
1
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3answers
651 views

CML/LVDS driver for several GHz, parasitic RC filter formed by terminating resistance and load capacitance

Update: Based on useful comments of The Photon, Andy aka and PlasmaHH. As I got, there is indeed the parasitic low-pass. There is no magic bullet that will mitigate it. Large receiver capacitance is ...
1
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2answers
320 views

Can series capacitors (DC block) be used to clean up LVDS signals over long distance

I have a system driving LVDS over ~ 140 ft of CAT6 cable. I am using the SN65LVDS series devices from TI to accomplish this. I'm aware that there will be low-frequency distortion in the signal at ...
1
vote
3answers
398 views

Profiling for FPGA requirements for a high-performance camera

I would like to know how to do the profiling of an image acquisition and storing pipeline on an FPGA based system, capturing images from a CMOS image sensor through LVDS interface, do some basic image ...
1
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1answer
646 views

Differential Signals (LVDS)

Talking about diff signals, we hear that they carry equal & opposite voltage. How will I conclude that referring the figure below :- What is the significance of common mode voltage in diff ...
1
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2answers
719 views

Using old laptop LCD as external VGA screen [closed]

I have a few old laptops with good LCD panels that I wish to salvage and use as external VGA screen on other computers. I'am no expert in electronics but I work with computers and know the basics of ...
1
vote
1answer
176 views

Cables for LVDS RS-644

To use SPI over a 5m long cable we plan to use LVDS RS-644 which calls for a twisted-pair cable with 100ohm characteristic impedance. Evaluating our cable options we looked into Cat5 cable (...
1
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2answers
133 views

Input clock of a Direct Digital Synthesizer

I need to create a circuit based around one of Analog Digital DDSs (AD9102) to create a sinusoidal signal at 150kHz. For this purpose I think that a clock line at around 10MHz would be sufficient. I ...
1
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1answer
50k views

LVDS 30 pin cable confusion [closed]

I'm trying to salvage a Samsung LTN154AT07 LCD from a laptop. I've ordered an MT6820-B rev.3 universal LVDS driver and a 5A step-down module (XL4005), and I think I have a decent grasp of how ...
1
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1answer
61 views

Why a potential divider at high speed LVDS clock outputs?

I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below. Will this ...
1
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1answer
300 views

Differential Pair Reference Plane Coupling

I am routing LVDS pair on a flex board. The signal is 264MHz. I used Saturn PCB design to calculate width and spacing between conductors. The targeted impedance for diff pair is 100 ohms, which is ...
1
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1answer
432 views

Does LVDS always need 100 ohm differential impedance?

LVDS pairs need 100 ohms differential impedance. However, I am having trouble achieving that in my design. My design requires that the pairs travel over very thin flexible PCB, about 50mm total ...
1
vote
1answer
180 views

Locating pairs on an LVDS cable

For a 2-row connector intended to interface a cable to a PCB, which method is preferable for twisted pair LVDS signals? Horizontal Pairs: LVDS1-    LVDS1+    ...
1
vote
1answer
347 views

Setting DC-bias on LVDS receiver with internal 100ohm differential termination

Here is the setup : simulate this circuit – Schematic created using CircuitLab RX channel is routed as 100ohm controlled impedance. FPGA input pins are LVDS IOs. I want to apply a DC bias of +...
1
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1answer
113 views

Which is better, less crosstalk or less skew?

I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other ...