Questions tagged [max10]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
1
vote
1answer
67 views

How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
1
vote
2answers
75 views

dual purpose pins on max 10 fpga

I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. ...
1
vote
1answer
376 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
0
votes
1answer
60 views

Is it possible to power down all the PLLs and VCO of a MAX 10 Device?

We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled ...
0
votes
1answer
153 views

Intel max 10 dimensions - datasheet & BSDL mismatch

TL;DR: The BSD file from Intel doesn't match the datasheet. What are the right dimensions? BSD: https://www.intel.com/content/dam/altera-www/global/en_US/others/support/devices/bsdl/10M02SCM153.bsd ...
0
votes
1answer
164 views

Intel Altera MAX 10 DEV KIT Interface - Can a RS232 6 pin PMOD module by Digilent be used seamlessly with MAX 10 for PC-FPGA UART communication?

I am planning to either purchase a MAX 10 or a DE2-115 dev kit to implement communication via both ethernet and RS-232. DE2-115 has both ports soldered onto the board, but MAX-10 has 2 ethernet ports ...
1
vote
1answer
673 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
0
votes
1answer
377 views

Altera Max10 altPLL slack

Regarding a MAX10 board. The whole design inside the MAX10 is clocked from a single clock using verilog's always@(posedge clockin). If connect directly a 80mhz clock to a Max10 input pin and define ...
2
votes
2answers
384 views

FPGA Jtag Hooking to User Logic

After some primer reading on jtag it looks to be a nifty means to test a FPGA logic design in a consistent and sustainable way. Let's use altera max 10 as an example. I've read this MAX 10 JTAG ...
2
votes
2answers
338 views

FPGA Bank Power On-Off Separately

Specifically the MAX 10 FPGAs are being looked at. The IO banks are powered through their own power pins. I've already know that the bank 1 and 8 need to be powered up with the core so that the ...
0
votes
1answer
215 views

Can I learn VHDL on a CPLD device?

I need to learn and practice VHDL, so I wouldlike to buy a small FPGA dev board. I've found a board based on a MAX10 circuit with the exact form factor I need, but I've read this chip is a CPLD, not a ...
2
votes
1answer
121 views

Altera MAX10 Clock primitives without synchronization?

Irrespective of the relative evil of gating clocks in FPGAs my understanding was that one should synchronize the enable signal to the clock being gated by means of a flip-flop chain. However, while ...
2
votes
1answer
448 views

Altera's MAX10 remote update

I am going to implement a MAX10 remote update. Unfortunately, in Altera's documents i only see a NIOS implementation and everything looks very big and too complex. Also i already have a reliable ...
1
vote
2answers
1k views

Altera Max10 3.3V interface

Regarding Altera's MAX10 Cpld, I got some questions regarding the interface of this CPLD with 3.3V devices. I have set pins to 3.3V LVCMOS and I got this warning message in quartus: "Warning (...
0
votes
2answers
670 views

Altera MAX10 CPLD initialization IO state

I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip). All the memory chip are on same bus so only ...
2
votes
1answer
998 views

Why don't my programs stay in the FPGA MAX 10 after a power cycle? [closed]

I program my FPGA (MAX 10) with a .sof file and works, but when I turn off my device everything erases from my FPGA. After exploration on the internet I found the EPCS IC, and I find out my board ...
2
votes
1answer
334 views

Why some MAX 10 chips don't support ADC while the datasheet says they do?

I'm using an Altera MAX 10 chip 10M50SCE144C8G. I want to use its ADC. In datasheet, it says that this chip has a "Single ADC that supports 1 dedicated analog input pin and 8 dual-function pins". ...
3
votes
2answers
3k views

Configure (upload bitstream) to MAX10 without Altera tools using Linux

I am currently using the flash-based Altera MAX10 in designed attached to main processor which runs Linux on a custom board (the FPGA itself just implements a few peripherals; the processor running ...
3
votes
1answer
1k views

Best utillization of M9K memory in max10 or other altera fpga's

I've got a max10 with a nios processor built in my memory utillization on the part is: 414,198 / 562,176 ( 74 % ) but I've used up every M9K block on the FPGA. Here is a table for the utillization As ...