Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
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How do memory seats keep track of their position?
I was wondering how do memory seats keep track of their position. Since this kind of equipment existed in 1990's cars, it must be simple yet ingenious. I have been thinking about this for quite a time ...
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1answer
60 views
Can a computer increase its memory in machine cycle? [on hold]
For my college assignment, one of the question asks to explain how a computer increases its memory in machine cycle. I have searched and so far I have found that a computer can't increase it's own ...
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53 views
32bit system with RAM larger than 4GB [closed]
Is there any advantage on installing more than 4GB of RAM on a 32bit system? It can only address 2^32=4GB of RAM, so anything extra to that can not be even addressed, less alone fill with code/data. ...
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1answer
47 views
What is address allocation of memory register? [on hold]
What is ment by address allocation of memory register in microprocessor and memory topic or in computer architecture?
Memory chips are have no processing elements(passive elements). How memory chips ...
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2answers
57 views
Does pin A15 on a Z80 tell if the CPU is addressing ROM or RAM?
I am designing a simple, hobbyist single board computer similar to an Arduino using a Z80 CPU. The trouble I am running into is how the CPU addresses memory. I know that the Z80 uses pins A0-A15 to ...
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1answer
25 views
Using narrower DDR RAM than controller
I have some ARM processor that have 72-bit width (8 for ECC) RAM controller.
Can I buy eg. two 32bit chips and combine them? If yes then how?
Can I buy just one 32bit and pull down rest of data pins ...
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2answers
89 views
Memory choices for lack of arduino speed [closed]
I'm designing a system which reads values from a microphone and feeds it to the Arduino to calculate a few sound parameters. The measuring happens during a couple of milliseconds. The problem is that ...
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0answers
27 views
PMOS as a pass gate in SRAM
Can anyone explain why replacing the NMOS pass gate in SRAMs with PMOS would be a bad idea from a circuit perspective?
Fast responses would be appreciated. Thank you!
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How to address each memory type in the design
Below is a problem I know how to list the hexadecimal address range for the whole memory but I got not idea how how to address each memory type in hexadecimal?
////////////////////////////////////////...
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1answer
54 views
Memory Addressing How To? [closed]
I have read some about computer memory and the article said DRAM is mainly made from a transistor to direct the electricity and a capacitor to store them. I don't understand how it fills certain ...
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0answers
50 views
Improving a SRAM-based memory cell by reducing number of transistors
I'm working on Emulated version of a memory cell. It is a volatile single-bit memory.
It uses 4 NAND gates to store one bit. I want to connect several of those memory cells together to create one ...
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2answers
131 views
STM32H7 with 512MB SDRAM
I'm considering to design an audio processor based on the STM32H7. I want to experiment with MCU-based DSP instead of using a dedicated DSP. I chose this high-end ARM MCU to have ample headroom for ...
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2answers
59 views
Why is there a need for an eNVM and an eSRAM in the same SoC FPGA
SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
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2answers
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Parallel RAM without large number of pins?
Back in the 1970s, Texas Instruments had a now-discontinued range of products that they called GRAM (and read only equivalent GROM) which was basically a standard memory chip with address and data all ...
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1answer
55 views
Asynchronous SRAM routing crosstalk concerns
I'm routing a large BGA SRAM that is connected to a BGA FPGA, and there's about 40 signals altogether connecting the two. I'm using Henry Ott's recommended 8-layer stackup:
1 ________________Mounting ...
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2answers
78 views
Are memory-mapped registers actually implemented as real registers?
I am currently trying to better understand microcontroller-architectures and I am particularly studying the ARM cortex-m3 right now. What I have always wondered is, if memory mapped registers are ...
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1answer
71 views
How memory is stored in memories like SD Card, USB flash drive, etc. that the data stays even if removed to the device?
This latches ( Gated Latch, SR Latch, and Flip Flops) can only store memory IF there is electric current flowing, but everything will go OFF if no current.
I wonder how memory is stored in memories ...
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4answers
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Does computer memory record the zero binary state?
It's been two years since I started reading about electronics and computer circuits. I fell in love with the homemade computers and the possibility of building one by myself.
You will see: When ...
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0answers
36 views
Power consumption of RFID vs SD card
I am working on enhancing security of data on electronic passports using homomorphic cryptography. Obstacles I am facing in application of the solution I have came up with relate directly to available ...
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3answers
2k views
Size of program counter
Can we say anything about the program counter by looking at the size of a memory chip?
I think the program counter is part of the microprocessor and memory is external. How can we comment about the ...
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1answer
32 views
Interfacing multiple SPI data input into EBI memory for access in verilog
I have several SPI peripherals that collect data into the FPGA and I have an EBI memory module to communicate data from FPGA to micro controller. I am having a hard time understanding the best way to ...
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0answers
41 views
Writing data to external Flash Memory chip
I develop a microcontroller project that requires writing big chunks of data in a Micron 4Gb SPI NAND Flash memory and I am a little confused regarding manipulation of the Flash memory blocks.
...
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0answers
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DRAM write operation
In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
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1answer
49 views
DRAM memory organisation
I've been trying to understand the working of DRAM chips but apparently in a lot of confusion.
Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
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1answer
478 views
What determines the ground state of a computers dram?
I have read a paper about the cold-boot attack led by J. Alex Halderman.
Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf
The paper shows the decay of a data in memory without power. They ...
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1answer
37 views
Cache memory on hit, no data stored
So, I have a question about the cache memory, i know that if the tag matches the data will be retrieved, but what happens if the current address has the same tag with others but in that place, in my ...
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2answers
106 views
How to secure an EMMC
My department of the company I am working at is in charge of developing a circuit for production, and security in the embedded system is a crucial requirement. The current prototype of our embedded ...
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2answers
134 views
Altera DE2-115 - Lack of on-chip memory resources for storing audio samples (?)
I have currently successfully stored some 16-bit, 48kHz audio samples using M9K blocks. Everything is perfectly functional, including their playback. My only problem is that, from my understanding (...
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1answer
61 views
Why address bus bit and data bus bit different [closed]
Recently I read address bus is 16 and 4 bit data/address in ROM.
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1answer
62 views
Memory access at microprocessors
I just learned about memory segmentation that is used in microprocessors and I was told that old microprocessors like Intel 8086 had 20 lines of address bus which means that it could access 2^20 ...
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0answers
27 views
Need to realize Mealy machine on embedded memory (VHDL)
Need Help to realize Mealy machine on emb. Now i have working code to Moore machine.How to get Miles to work it, according to control signals
...
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1answer
175 views
How does a memory map of a 1K EEPROM look like? [closed]
I am using a 1Kbit: The device is organized as one block of 128 x 8-bit memory. I want to understand how to it's organized and how addresses are structured?
Example: I want to store the world "Hello" ...
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0answers
46 views
Accessing encoder buffer from a task
The LPC1768 has a quadrature encoder interface (QEI), which stores the encoder count in a fixed memory location.
Can this be accessed in the typical way, through a FreeRTOS task (I think header files ...
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3answers
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Is “new” acceptable when using C++ objects in a FreeRTOS application?
I've read that malloc() should be avoided when designing FreeRTOS applications. Does the same apply when using "new"?
E.g.:
TestObject* test = new TestObject();
...
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1answer
78 views
Content addressable memory chip
I have searched a lot for a content addressable memory chip, but I couldn't find any part numbers. Why aren't there any chips for this kind of memory?!
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1answer
122 views
What's the need of translating the virtual address to physical address?
These are the points I read in the Memory Management Unit of ARM architecture:
Virtual addresses (or logical addresses) are addresses provided by the OS to processes.
One virtual address space per ...
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1answer
1k views
How is a DRAM volatile with capacitors?
There are a few things I understand:
DRAM stores each bit of data to a tiny capacitor with some potential difference.
Unless the capacitor is connected to low voltage end, the potential difference ...
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1answer
398 views
Replacing Pseudo-SRAM with SRAM
This week I am repairing an old Game Gear, suffering from bad video memory. The original IC is a HM65256BLFP-10T: an asynchronous Pseudo-Static 8-bit 32k-word RAM with an access time of 100ns.
I ...
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2answers
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Where is the location of display buffer on a computer board? [closed]
On an OS development text by Nick Blundel, at chapter 4.1 titled Adapting to Life Without BIOS, it is explained that while graphics
hardware is in text-mode, we can write ASCII characters on screen by ...
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2answers
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If I need to access memory cell by cell, should I shift or index?
I have a piece of memory which I need to access cell by cell:
parameter RAM_LENGTH = 1024;
reg [7:0] mem [RAM_LENGTH - 1:0];
I need to iterate cells sequentially....
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1answer
89 views
Memories' structure
One of the most recent memory architectures is the 3D-Xpoint which has a structure of the type:
So, you see that as usual in a memory device we have wordlines and bitlines.
Now suposse I want to ...
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1answer
122 views
Why does this RAM component have unpredictable behavior in Multisim?
Multisim has a 2k8 RAM component that I was playing around with. Here is how it works. Here is what happens when I simulate this. Let's say I save the value 00000011 to address 00000000. Then, I make ...
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3answers
351 views
How can I implement a very simple asynchronous DRAM controller?
I'd like to know how to build a bare bones asynchronous DRAM controller.
I have some 30-pin 1MB SIMM 70ns DRAM (1Mx9 with parity) modules that I'd like to use in a homebrew retro computer project. ...
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3answers
140 views
Structure of Larger Memory Modules by using different Size Blocks
I want to design a memory module that includes 2 types of memory cells. I know how to design the memory by using 1 type of memory cells like shown in the picture.
But how about designing a memory ...
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Can memory timings be adjusted on SoC instead of having to match DDR trace lengths?
I made a little board with a AM3358 and some ram but i didn't pay attention that all traces had to be around the same length and i now have memory errors because of this.
Would it be possible to ...
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0answers
221 views
Bus Pirate Flashrom OTP chip issue (Winbond W25Q128FV SPI flash)
So I have an embedded device with a Winbond W25Q128FV SPI flash chip on it and I am trying to extract the firmware by dumping the flash memory.
So far I have used a Bus Pirate with Flashrom to do so. ...
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1answer
225 views
using generate statement in verilog
I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog
this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
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9answers
1k views
EEPROM with high endurance
I am currently working on one embedded project in which I have one counter which will be active all the time.
If the power goes down then also I have to store last counter status and load it back in ...
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0answers
120 views
What is write/read leveling(each DQ relative to DQS)
DDR3 supports write and read leveling on DQ.
I know we need them because of Fly-by topology.
But I want to know more detailed reason why we need them for DDR3.
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In 1T1C DRAM cell, which takes longer, Read 0 or Read 1 and why?
I've been trying to simulate a 1T1C DRAM cell. My technology node is 20nm and cap values are 25fF and 182fF for storage and bitline respectively. I observed that the read and write times for 0 and 1 ...
