Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
0
votes
2answers
40 views
Why is there a need for an eNVM and an eSRAM in the same SoC FPGA
SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
15
votes
2answers
1k views
Parallel RAM without large number of pins?
Back in the 1970s, Texas Instruments had a now-discontinued range of products that they called GRAM (and read only equivalent GROM) which was basically a standard memory chip with address and data all ...
0
votes
1answer
41 views
Asynchronous SRAM routing crosstalk concerns
I'm routing a large BGA SRAM that is connected to a BGA FPGA, and there's about 40 signals altogether connecting the two. I'm using Henry Ott's recommended 8-layer stackup:
1 ________________Mounting ...
0
votes
2answers
75 views
Are memory-mapped registers actually implemented as real registers?
I am currently trying to better understand microcontroller-architectures and I am particularly studying the ARM cortex-m3 right now. What I have always wondered is, if memory mapped registers are ...
0
votes
1answer
70 views
How memory is stored in memories like SD Card, USB flash drive, etc. that the data stays even if removed to the device?
This latches ( Gated Latch, SR Latch, and Flip Flops) can only store memory IF there is electric current flowing, but everything will go OFF if no current.
I wonder how memory is stored in memories ...
1
vote
4answers
138 views
Does computer memory record the zero binary state?
It's been two years since I started reading about electronics and computer circuits. I fell in love with the homemade computers and the possibility of building one by myself.
You will see: When ...
0
votes
0answers
35 views
Power consumption of RFID vs SD card
I am working on enhancing security of data on electronic passports using homomorphic cryptography. Obstacles I am facing in application of the solution I have came up with relate directly to available ...
6
votes
3answers
2k views
Size of program counter
Can we say anything about the program counter by looking at the size of a memory chip?
I think the program counter is part of the microprocessor and memory is external. How can we comment about the ...
0
votes
1answer
23 views
interfacing multiple SPI data input into EBI memory for access in verilog
I have several SPI peripherals that collect data into the FPGA and I have an EBI memory module to communicate data from FPGA to micro controller. I am having a hard time understanding the best way to ...
0
votes
0answers
36 views
Writing data to external Flash Memory chip
I develop a microcontroller project that requires writing big chunks of data in a Micron 4Gb SPI NAND Flash memory and I am a little confused regarding manipulation of the Flash memory blocks.
...
0
votes
0answers
27 views
DRAM write operation
In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
1
vote
1answer
44 views
DRAM memory organisation
I've been trying to understand the working of DRAM chips but apparently in a lot of confusion.
Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
7
votes
1answer
477 views
What determines the ground state of a computers dram?
I have read a paper about the cold-boot attack led by J. Alex Halderman.
Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf
The paper shows the decay of a data in memory without power. They ...
-1
votes
1answer
36 views
Cache memory on hit, no data stored
So, I have a question about the cache memory, i know that if the tag matches the data will be retrieved, but what happens if the current address has the same tag with others but in that place, in my ...
1
vote
2answers
85 views
How to secure an EMMC
My department of the company I am working at is in charge of developing a circuit for production, and security in the embedded system is a crucial requirement. The current prototype of our embedded ...
0
votes
2answers
101 views
Altera DE2-115 - Lack of on-chip memory resources for storing audio samples (?)
I have currently successfully stored some 16-bit, 48kHz audio samples using M9K blocks. Everything is perfectly functional, including their playback. My only problem is that, from my understanding (...
-1
votes
1answer
52 views
Why address bus bit and data bus bit different [closed]
Recently I read address bus is 16 and 4 bit data/address in ROM.
0
votes
1answer
61 views
Memory access at microprocessors
I just learned about memory segmentation that is used in microprocessors and I was told that old microprocessors like Intel 8086 had 20 lines of address bus which means that it could access 2^20 ...
0
votes
0answers
25 views
Need to realize Mealy machine on embedded memory (VHDL)
Need Help to realize Mealy machine on emb. Now i have working code to Moore machine.How to get Miles to work it, according to control signals
...
1
vote
1answer
129 views
How does a memory map of a 1K EEPROM look like? [closed]
I am using a 1Kbit: The device is organized as one block of 128 x 8-bit memory. I want to understand how to it's organized and how addresses are structured?
Example: I want to store the world "Hello" ...
0
votes
0answers
15 views
Accessing encoder buffer from a task
The LPC1768 has a quadrature encoder interface (QEI), which stores the encoder count in a fixed memory location.
Can this be accessed in the typical way, through a FreeRTOS task (I think header files ...
1
vote
3answers
109 views
Is “new” acceptable when using C++ objects in a FreeRTOS application?
I've read that malloc() should be avoided when designing FreeRTOS applications. Does the same apply when using "new"?
E.g.:
TestObject* test = new TestObject();
...
0
votes
1answer
66 views
Content addressable memory chip
I have searched a lot for a content addressable memory chip, but I couldn't find any part numbers. Why aren't there any chips for this kind of memory?!
0
votes
1answer
102 views
What's the need of translating the virtual address to physical address?
These are the points I read in the Memory Management Unit of ARM architecture:
Virtual addresses (or logical addresses) are addresses provided by the OS to processes.
One virtual address space per ...
9
votes
1answer
1k views
How is a DRAM volatile with capacitors?
There are a few things I understand:
DRAM stores each bit of data to a tiny capacitor with some potential difference.
Unless the capacitor is connected to low voltage end, the potential difference ...
4
votes
1answer
285 views
Replacing Pseudo-SRAM with SRAM
This week I am repairing an old Game Gear, suffering from bad video memory. The original IC is a HM65256BLFP-10T: an asynchronous Pseudo-Static 8-bit 32k-word RAM with an access time of 100ns.
I ...
1
vote
2answers
117 views
Where is the location of display buffer on a computer board? [closed]
On an OS development text by Nick Blundel, at chapter 4.1 titled Adapting to Life Without BIOS, it is explained that while graphics
hardware is in text-mode, we can write ASCII characters on screen by ...
1
vote
2answers
54 views
If I need to access memory cell by cell, should I shift or index?
I have a piece of memory which I need to access cell by cell:
parameter RAM_LENGTH = 1024;
reg [7:0] mem [RAM_LENGTH - 1:0];
I need to iterate cells sequentially....
0
votes
1answer
89 views
Memories' structure
One of the most recent memory architectures is the 3D-Xpoint which has a structure of the type:
So, you see that as usual in a memory device we have wordlines and bitlines.
Now suposse I want to ...
1
vote
1answer
102 views
Why does this RAM component have unpredictable behavior in Multisim?
Multisim has a 2k8 RAM component that I was playing around with. Here is how it works. Here is what happens when I simulate this. Let's say I save the value 00000011 to address 00000000. Then, I make ...
8
votes
3answers
302 views
How can I implement a very simple asynchronous DRAM controller?
I'd like to know how to build a bare bones asynchronous DRAM controller.
I have some 30-pin 1MB SIMM 70ns DRAM (1Mx9 with parity) modules that I'd like to use in a homebrew retro computer project. ...
0
votes
3answers
87 views
Structure of Larger Memory Modules by using different Size Blocks
I want to design a memory module that includes 2 types of memory cells. I know how to design the memory by using 1 type of memory cells like shown in the picture.
But how about designing a memory ...
0
votes
0answers
41 views
Can memory timings be adjusted on SoC instead of having to match DDR trace lengths?
I made a little board with a AM3358 and some ram but i didn't pay attention that all traces had to be around the same length and i now have memory errors because of this.
Would it be possible to ...
0
votes
0answers
192 views
Bus Pirate Flashrom OTP chip issue (Winbond W25Q128FV SPI flash)
So I have an embedded device with a Winbond W25Q128FV SPI flash chip on it and I am trying to extract the firmware by dumping the flash memory.
So far I have used a Bus Pirate with Flashrom to do so. ...
0
votes
1answer
104 views
using generate statement in verilog
I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog
this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
8
votes
9answers
1k views
EEPROM with high endurance
I am currently working on one embedded project in which I have one counter which will be active all the time.
If the power goes down then also I have to store last counter status and load it back in ...
1
vote
0answers
107 views
What is write/read leveling(each DQ relative to DQS)
DDR3 supports write and read leveling on DQ.
I know we need them because of Fly-by topology.
But I want to know more detailed reason why we need them for DDR3.
0
votes
0answers
36 views
In 1T1C DRAM cell, which takes longer, Read 0 or Read 1 and why?
I've been trying to simulate a 1T1C DRAM cell. My technology node is 20nm and cap values are 25fF and 182fF for storage and bitline respectively. I observed that the read and write times for 0 and 1 ...
0
votes
1answer
80 views
multiprocessor programming and memory management [closed]
I'm working for a project (an embedded storage system) that requires to increase a memory access speed using a multiprocessors programming, so that we can execute a memory access program (storing data)...
1
vote
0answers
38 views
In a DRAM 1T1C cell, what are the typical values observed for caps?
So, I want to simulate a 1T1C DRAM cell. I have come across a wide variety of numbers for the storage cell capacitance in literature, ranging from as low as 13.8fF to as high as 150ff. but I haven't ...
0
votes
0answers
23 views
Finding number of lines in Cache [duplicate]
So the task I have in front of me states :
We have a 1 MB RAM with word size of 16 bytes and a
4-Way Set Associative Cache 32 Kbytes capacity
What I need to find is the address length and how the ...
0
votes
2answers
474 views
What does Burst-size of a SDRAM means? [closed]
I am currently working with real-time image processing in FGPA. I have some timing problems about the classical FFT algorithm. i.e : FFT of one images spends more time than one frame period time. I ...
2
votes
2answers
266 views
SDRAM structure for Cortex-M7
I'm looking into designing a custom board based on a Microchip / ATMEL SAM S70 or STM32F7 / STM32H7. The SAMS S70 appears to be the cheapest option and offers roughly the same as the ST competitors.
...
1
vote
1answer
147 views
Is it possible to read the memory from a Holtek HT46R064B OTP(!) chip?
I am trying to get data from a Holtek HT46R064B. I know that the Chip is an OTP (One-Time Programmable) Chip. I ask myself if it is possible to read some parts of its memory.
In my case the chip is ...
-1
votes
3answers
139 views
How is the memory allocated in an AVR?
I'm writing a program for the AVR microcontroller, and my code experiments has led me to both confusion and discovery. Here is first code:
...
2
votes
2answers
63 views
microproccessor 8085
What is the need of enabling 8 bit register in memory using address bus to read data from it?Enabling is required to write data into register and after that to read can't we just provide read signal ...
-5
votes
1answer
142 views
Design logic circuit to address 2 x 512 kB RAM and 2x1024 MB RAM with 36 address lines? [closed]
How do you address 2 x 512 kB RAM and 2 x 1024 MB RAM with 40 address lines?
Memory is byte addressable, problem is to find out enough address lines to address all 4RAM and designing appropriate ...
4
votes
1answer
84 views
Character mask VGA display
Im building a VGA (640x480@60Hz) adapter for my homebrew project but i dont have enought memory to store a framebuffer. Since im using 8 bit memory i plan to do 8 bit color, but 8 colors would be ...
0
votes
0answers
74 views
PIC memory problem
I write program for PIC16F73 and XC8 compiler. If I add additional variables and Data Memory increased to 50% or more microcontroller will be not working in real life. If
microcontroller use more ...
1
vote
2answers
269 views
What is SNM(Static Noise Margin) in SRAM?
I have read multiple papers and articles about it but still, I am not able to understand fully. If you can explain me in layman terms I would be much happy. Thanks.
