Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
660
questions
0
votes
1answer
69 views
How does a CRC check work between a microcontroller and EEPROM?
I have communication between an EEPROM and a microprocessor over SPI and I want to take care of data integrity.
Could you please confirm my below understanding?
I have a data which I want to write in ...
0
votes
1answer
34 views
0
votes
0answers
25 views
What are odd-even memory addresses in 8086 and how do they work? [duplicate]
I have recently started to look more into microprocessors at the hardware level, and i am a bit confused on what are the odd-even memory locations that 8086 uses.
As far as i understand, it has ...
0
votes
1answer
64 views
How do modern CPUs treat memory operations? [closed]
How does a modern CPU treat memory reads and writes on the hardware level?
With old 8-bit architectures all memory locations are read and written to one byte at a time, but how do modern CPUs that ...
0
votes
1answer
32 views
Understanding addressing and size in memory map
TM4C123 has 256 kiBytes of flash ROM as shown in the memory map. The range of memory addresses for the ROM is 0x0000.0000 to 0x0003.FFFF (a 32bit address), totaled to 3x16x16x16x16 = 196,608 number of ...
0
votes
0answers
17 views
PROGMEM problem with my project - dynamic allocation error
My project is and RTISR (Real Time Instant Signal Recognizer).
I'm sampling a signal from PIN A0 in the Arduino, and I have 6 types of Signals which I compare with (using squared cross correlation to ...
2
votes
1answer
81 views
MicroSD to USB adapter
My goal is to make a MicroSD to USB adapter myself.
With this question, I saw that I can use a USB2240 controller chip to connect my µSD card to my computer.
In ...
5
votes
4answers
518 views
The memory regions I can write and cannot write to, ARM Cortex-M architecture
I hope my title is correct terminologicaly. I am working(learning) with STM32F4 discovery board, which has an STM32F407VGTx microcontroller on it. I really try to find the answers in the reference ...
11
votes
8answers
4k views
EEPROM being both “programmable” and “read-only”
Since it is called programmable, I tend to think that it should also be named with the write option. What is the deal here?
1
vote
1answer
86 views
Understanding PIC MCU memory from datasheet
Being new to PIC, I have been struggling to understand the information in the datasheet.
Q.1. : What does "256 bytes Linear Data Memory Addressing Memory" mean? I am looking at the ...
0
votes
0answers
19 views
41256 / 81256 - dram power and ground confusion
I'm trying to design a memory board for an Emu Emax sampler to enhance the amount of memory.
Now, when I read the Emax service manual and look at schematics over memory chip connections (in this case ...
2
votes
1answer
77 views
Manual EEPROM Programming Problem
I have a 28c256-25 EEPROM that I have created a breadboard circuit to program. The datasheet says after the address is set and the data is put on the I/O pins, a low pulse on /WE while /OE and /CE are ...
0
votes
0answers
36 views
Why it is required to write each byte with 0 before erase in NOR flash?
It is written in some sites that for NOR flash, each byte has to be written with 0 before erase. Why it is required to write with 0 before erasing? Erasing the sector change each byte to 1.
0
votes
1answer
53 views
Is an even number of DRAM chips required?
I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...
0
votes
0answers
32 views
Use MicroSD to SD adapter for read Memory Stick Micro M2
While searching in my personal affairs I found a Memory Stick Micro M2 (Sony) which I believe I was using in a phone. Unfortunately I no longer have the adapter ...
0
votes
1answer
33 views
Built in Self Test - In Embedded memories
I am reading this thing called -BIST (Built in Self Test).
I understand that, before a module enters its intended functionality, this BIST is made to run within the module. Once, this BIST is passed, ...
0
votes
2answers
68 views
Why do block RAMs have synchronous reading instead of async reading?
I'm programming FPGA boards (Artix 7 to be exact) and I recently noticed that, in order to be synthesized into block RAM, an array of storage must have synchronous reading, otherwise it will only be ...
2
votes
1answer
64 views
Beginner trying to learn how to read start and end addresses for memory chips in hexadecimal
I'm new to electrical (construction management student) and am trying to learn how to read start and end addresses. The practice problem I have been given is in the picture, and I was wondering how I ...
2
votes
2answers
62 views
Last address of program in STM32 HAL?
Is there a way to find the last address or last page of the program which is stored in an STM32(F1) using a HAL (or LL?) function?
Background: I'm using EEPROM emulation in Flash and this works great....
0
votes
2answers
54 views
What is the relevance of a !Q in the D Flip-Flop when using for a memory module?
If the purpose of this circuit is to store the value of D in Q, why should I need a !Q? Why don't use a circuit like this instead?:
2
votes
2answers
86 views
What is the probability of a bit error occurring in modern computers?
What is the probability of a bit error occuring when reading/writing from/to the latest memory technologies (ssd, hdd, ram) in modern computers? If the same terminology is used in this context as in ...
1
vote
2answers
66 views
How do I implement authentication on an embedded device? [closed]
I have been reading a lot about encryption lately but most sources just care about making sure that the connection between two parties is secure. I want to know how I can be sure that the party I am ...
1
vote
2answers
149 views
Why does dynamic ram need to be 'refreshed'?
I read this question, but it didn't really answer my question. I also want to preface this question by saying that I'm asking this from the perspective of being a computer science student that took ...
1
vote
0answers
26 views
In Directed-mapped cache, a problem in exercise!
5.2 Caches are important to providing a high-performance memory hierarchy
to processors. Below is a list of 32-bit memory address references, given as word
addresses.
3, 180, 43, 2, 191, 88, ...
0
votes
3answers
80 views
Sequential circuits and memory
I read some books to understand why we need to memorise bits in electric circuits and found the sequential logic circuits are designed to achieve that goal.
The basic element is the SR Latch which ...
0
votes
5answers
199 views
Why are bytes 8 bits? (and more)
An 8 bit value can range anything from 0 to 255 in decimal, or 00 to FF in hexadecimal. But why did they choose 8 bits for the byte, out of all of the powers of 2 they could have chosen? Even still, a ...
0
votes
1answer
103 views
Where the ICM20948 DMP memory is stored?
In Invensense ICM20948 motion sensor
they mention
The DMP in ICM-20948, therefore, has higher memory for code storage
Hence, the AP/MCU must accommodate higher memory required to hold the DMP image
...
-2
votes
1answer
48 views
EEPROM converted to DRAM?
Can we use a EEPROM cell for DRAM ?
simulate this circuit – Schematic created using CircuitLab
This is an EEPROM cell. Can we use multiple cells of this type to create a DRAM?
0
votes
1answer
24 views
DDR4 column width v/s burst size
I'm trying to understand how data is going to fill up a 64bit cacheline with x4 DDR4 DIMM.
x4 DDR4 has 16 Banks, 4 Banks each in 4 Bank Groups and each bank is having 4 memory arrays. Burst size is 8....
0
votes
2answers
81 views
The CPU has registers, but doesn't the RAM have registers too?
At low-level, registers are the same as a bunch of flip-flops connected by the same clock, so I would think RAM is made of registers.
I've been reading, though, that registers are only in the cpu, ...
3
votes
1answer
38 views
Is there some kind of standard of modbus input register?
As the title said,
based on your experience, is there a such thing?
If no, which are the most commonly used?
for example in a sensor, the input registers as follows:
...
0
votes
1answer
31 views
3-terminals magnetic tunnel junction
I was wondering if a 3 terminals magnetic tunnel junction can be implemented, as in the Figure.
On the bottom I have a normal metal (NM), on the top a magnetic junction (FM = ferromagnet) and I can ...
1
vote
0answers
40 views
Devices storing volatile memory
I've hit a bit of a rut in a question on my homework for my computer architecture class (MIPS architecture):
what are digital logic devices that can implement 1 bit and 32 bit volatile memory, and ...
1
vote
1answer
63 views
How x86-64 Intel CPU understands how many bytes load into a register
I have the following byte code one the left and and its byte representation on the right:
...
0
votes
1answer
45 views
Decoder inputs needed given 32 registers
I have a couple of questions about decoders. My first is this:
If I have a register bank with 32 registers, how many inputs are needed for the decoder and why? I think that you need 5 inputs for this ...
0
votes
1answer
52 views
74ls279 SR latch not working
I am trying to get an 74ls279 SR latch to hold a state, but it's not working. I am using a full-size solderless breadboard, a 3V power supply, and an LED to view its state. The LED flickers and loses ...
0
votes
1answer
38 views
Timer IC that doesn't reset count because of power down and remembers last state [closed]
I'm looking for a timer/RTC that will count how long the system power was up in total and will toggle a pin after a specific time that will be configured in advance.
Does a timer that "remembers" ...
0
votes
1answer
113 views
Why cant clock be directly used instead of DQS in DDR during read and write
I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write ...
0
votes
1answer
23 views
Where can I Find the Memory map and register table for the S70FL01GS
I am currently working with this device:
https://www.mouser.com/datasheet/2/100/001-98295_S70FL01GS_1_Gbit_128_Mbyte_3.0V_SPI_Flas-1102682.pdf
The datasheet provides some high-level details about ...
0
votes
4answers
218 views
Memory Mapped IO and IO Mapped IO
I am revisiting Microcontrollers and Microprocessor concepts.
Yes. I know this question has been asked many times like here and here. I have also visited many sites regarding this concept but still I ...
0
votes
1answer
41 views
Bit Lines at SRAM
I would like to know the specific purpose for SRAM having a bit line and a negated bit line? I might think that is due to stability reasons, but I would like to know more details about its specific ...
0
votes
1answer
92 views
Why do we need interleaved memory?
I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says:
Interleaved memory results in contiguous reads (which are common both
in ...
0
votes
2answers
136 views
SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?
What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits?
Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
0
votes
1answer
40 views
Read-only for some masters but read-write for other?
Is it possible that a memory/memory region be read-only for some masters/chip components but read-write for others?
It is kind of vague question, but from a conceptual point view would this be ...
2
votes
0answers
119 views
eMMC Jedec Backward Compatibility
I'm working on a new design based on a Xilinx FPGA.
I'd like to use some eMMC devices but the FPGA controller supports JEDEC up to 4.51.
Nowadays, some eMMC devices are JEDEC 5.0 or 5.1 compliant ...
1
vote
1answer
128 views
PCB sound memory for toys [closed]
I want to build a toy. The initial build will be a prototype but if the idea 'sells,' I want to build en-masse.
For the prototype, as I do not have (beyond what I learnt at Uni) industry experience, ...
1
vote
1answer
139 views
Amplifier memory distortion application
I've found an article about memory distortion issues in audio analog amplifiers. Available for free here.
The author uses in the last configuration a CFP differential input with a cascode of FET ...
1
vote
1answer
83 views
Cortex-M3, Code region vs SRAM/RAM
In the ARM Cortex-M3 processor core, the memory map contains: a Code region, SRAM and a RAM. What makes the use of the code region different than the other memories? In addition, what is the nature of ...
0
votes
0answers
49 views
eMMC selection problem due to lifecycle
As you know while considering eMMC's lifecycle there are 3 technologies called SLC, MLC, and TLC.
But I could not understand exact speed of these. i.e. MLC's lifecycle.
Some say 3k like this one.
...
0
votes
0answers
85 views
Problems with Memory Initialization in Quartus
I have the following code snippet in my VHDL code to initialize a ROM block:
...
