Questions tagged [memory]

Consider instead more specific tags, e.g., dram, sram, flash

Filter by
Sorted by
Tagged with
1 vote
2 answers
81 views

Problem in executing the memory stage that can perform call, ret, pop, etc

I am trying to implement a Y86 processor for my college assignment. This is my MemoryStage: ...
Chiranjeevi K's user avatar
1 vote
2 answers
48 views

How is the structure of a matrix addressable memory block realized?

Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
mxpici's user avatar
  • 13
-1 votes
0 answers
63 views

Help identifying chip - Y1294 4PV01 A7 [closed]

I am trying to find out what this chip is I believe it is perhaps a microprocessor or microcontoller. Perhaps a PIC or clone. I think it serially communicates with the camera relaying a fixed piece ...
onepound's user avatar
  • 183
-1 votes
0 answers
56 views

ESP32 strlen in ROM error

The free(buf) in the below function throws the strlen in ROM error. I can't figure out what I'm doing wrong: ...
kovac's user avatar
  • 473
0 votes
1 answer
42 views

Can't write to status register of SST25VF010A flash memory

I'm having trouble writing to the status register of a SST25VF010A-33-4I-SAE 1Mbit SPI flash memory on a board I recently made. I'm using an STM32F401CBU6 to communicate with the memory. I can read ...
Swiss Gnome's user avatar
1 vote
0 answers
67 views

Picking the best memory technology for our needs

This is my first post here, but bear with me. I have come here after searching the internet for a while (like most of us do) We are in the process of figuring out which memory option would be the best ...
Abhishek Tyagi's user avatar
0 votes
0 answers
55 views

What do NRAM cells look like?

Note: I don't have any electrical engineering experience, so I'd like to apologize for my bad vocabulary about this subject. I'm currently exploring the memory world and stumbled across NRAM which got ...
TornaxO7's user avatar
  • 101
0 votes
2 answers
86 views

Why memory cell basis is typically "paired inverters" and not "paired forwarders", revisited

I asked over a year ago (link) about why memory cells typically use paired inverters instead of paired buffers. The answer mentioned gain, "this is basically because it's hard to make non-...
BipedalJoe's user avatar
1 vote
2 answers
173 views

Why do AVR microprocessors have two ways (paths) to access I/O ports?

I've an ATmega328P. Register Summary Page 275 ATmega328P datasheet. The first address is the I/O address, and the second is the data memory address. I'm going to set all (D ports) Data Direction ...
Amr Elkamash's user avatar
7 votes
2 answers
2k views

What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?

I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
Nadax's user avatar
  • 73
9 votes
2 answers
585 views

What is the theoretical maximum capacity of 72-pin RAM modules?

I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect. This is my current understanding: A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
polemon's user avatar
  • 1,097
0 votes
1 answer
67 views

STM32H7 QuadSPI CMSIS Read

So, I am trying to access an APS6404 IC (PSRAM) with QSPI on STM32H7 (currently in single-line mode). When I am writing to it, everything seems fine, but as soon as I read - the FIFO is empty and the ...
sx107's user avatar
  • 1,077
1 vote
2 answers
387 views

Why does this little program occupy 80% storage in my ESP32? any solutions?

...
Venkat Yalamati's user avatar
3 votes
1 answer
77 views

Memory Capacity and Memory Addresses

According to this site, in Table2, HBM(HBM2e) has a capacity of 8Gb = 2^33 bits per channel. Here, it has a 24-bit address consisting of 4 bits from the Bank address BA[3:0], 15 bits from the Row ...
cashew_nuts's user avatar
2 votes
2 answers
473 views

Is it wrong to use Thévenin's theorem on this memory circuit?

In my electricals beginner class I was given a paper about memory circuits. There was a small section about how writing data to a single memory cell worked. Here is the sketch of the memory cell: The ...
volticus's user avatar
  • 173
1 vote
0 answers
87 views

How to handle flash write/read operations on STM32L552 with ICACHE enabled without disabling it?

I am currently working with an STM32L552 microcontroller and encountering some peculiar behavior when writing and reading double words to and from the flash memory. After writing data to a specific ...
tronhawk's user avatar
0 votes
0 answers
76 views

How I can store data code for LONG time 100-200y - ESP32, Arduino, Data Retention, Reliability, Lifetime, Flash

I'm working on a research project in winch we want embedded sensors and logic, an ESP32, inside building's pillar surrounded by concrete. The ESP32 collects data through sensors, process them and send ...
user avatar
0 votes
1 answer
66 views

Why is memory addressed using 2 address decoders only and not more? [duplicate]

I am currently taking a university course about computer architecture in which we learned basic DRAM architecture and addressing. As far as I know, each latch is selected using decoder outputs to ...
Yousef Irshaid's user avatar
-1 votes
1 answer
55 views

Synchronising data input and filter coefficient so that both reach at same time and give filter output in semi parallel/parallel filter in Verilog

I have designed an 8-tap filter using 8 coefficients in a semi-parallel fashion. I want to get the correct output for a FIR filter design by using 8 DSPs and one SRLC32E register. Here I pass my input ...
superb ranjeet's user avatar
1 vote
0 answers
64 views

6502 Extra Cycles on Page Cross

On the 6502 processor, when using the Absolute,X, Absolute,Y or (Indirect),Y addressing ...
Macmade's user avatar
  • 291
0 votes
1 answer
146 views

MUX in a 4 bit by 3 bit memory

Here is a 3-bit adressable memory with an adress space of 4. My question is why is the book calling the 3 rightmost highlighted circuits MUXes? And what type of MUXes are they? 4:1 MUX? And if it is ...
oabdullae's user avatar
2 votes
2 answers
104 views

Finding correct memory IC [closed]

I have a project where I need to store data (~16Mo) on a memory IC and be able to fetch the data fast (<36000bits/s) (with DMA in the idea). My µcontroller is an Arduino DUE. So far I've tried a ...
Vlad's user avatar
  • 21
1 vote
1 answer
97 views

Reflashing firmware for preventive purposes

This is a relatively common malfunction for the installed firmware in some old electrical devices to become corrupted. I often see this in repair videos, and there's often an easy fix - reflash the ...
NSp's user avatar
  • 11
0 votes
0 answers
58 views

Finding memories power dissipation

Can someone tell me how to calculate the power dissipation of digital ICs like NAND Flash, QSPI NOR Flash and microcontrollers?
sushmi Ram's user avatar
0 votes
1 answer
71 views

eMMC interfacing with EC200U SDIO Power domain

I need to interface my eMMC(THGBMJG6C1LBAU7) memory with EC200U from Quectel. The Quectel E200U has two SDIO ports one is working at 3.3V power domain and other one is working at 1.8V power domain. ...
Hari's user avatar
  • 2,010
0 votes
0 answers
58 views

SDRAM and I2S on STM32

I am using an STM32F429 discovery board to develop a DSP platform for making some sound effects. I have I2S streaming and passing through, and I have SDRAM configured where I can talk to it and even ...
Adam's user avatar
  • 75
0 votes
2 answers
102 views

DRAM Memory : How is data stored from the HDD to DRAM? [closed]

When storing data from HDD to DRAM, is one large data block (e.g., 8 bytes) stored in one chip? Or is it distributed among multiple chips in a DIMM? If it is distributed, how many bytes of consecutive ...
C.Ky's user avatar
  • 3
0 votes
1 answer
450 views

DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?

While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock. The characteristic of DDR is that it transfers 2 sets of data every cycle. Therefore, for older versions of ...
ALPHA's user avatar
  • 1
1 vote
0 answers
44 views

Does "field electron emission" used in EEPROM work better than "hot-carrier injection" in NOR Flash?

After deeping research based on my another question, I continued comparing Flash and EEPROM based on wikipedia comparison table. From wikipedia about the Flash memory: Programming the source-drain ...
zg c's user avatar
  • 83
1 vote
1 answer
48 views

Is it possible to use a MOS 6502 with a AE29F2008?

I wanted to buy a MOS 6502, but before that, wanted to know if it is possible to interface it with an AE29F2008 memory (recovered from a PC). The problem is that the AE29F2008 has three address pins ...
jack07Code's user avatar
0 votes
1 answer
59 views

Tsi107 PowerPC Host Bridge Vs Processor

I a confused regarding the difference between a powerPc host bridge and a processor. According to the host bridge datasheet, it can be programmed, and it has interrupt generation and handling, and ...
kam1212's user avatar
  • 593
0 votes
1 answer
137 views

What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?

I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
Ankit Kumar's user avatar
0 votes
0 answers
21 views

Entering memory adresses into a direct mapping cache

I have been given the following problem: A computer CPU generates the following adresses in 8 bit binary form: 91, B3, 70 etc. The computer has direct mapping cache that can store 64 words and 8 words ...
bill kladis's user avatar
0 votes
0 answers
41 views

Direct Mapping of 8GByte memory with 64-bit addressable word size

The question: A computer has 8 GByte of memory with 64-bit addressable word sizes. Each block of memory stores 16 words. The computer has a direct-mapping cache of 128 blocks Calculate the tag bits, ...
AMunim's user avatar
  • 103
11 votes
8 answers
5k views

What mechanism does CPU use to know if a write to RAM was completed?

How does CPU know that a write to RAM was successful, like how does a faster CPU know that data was successfully written to a slower RAM? You're free to mention any system architecture because I'm not ...
John greg's user avatar
  • 189
0 votes
0 answers
199 views

Can a PCI bus master access a device mapped in cpu memory space

If a PCI bus master can access memory space just as cpu can, can it put an address on the memory bus of the cpu that actually triggers a memory mapped I/O device to respond to that address. (As if the ...
John greg's user avatar
  • 189
1 vote
1 answer
117 views

Using SRAM Macro for simulation and synthesis

I got my hands on this ARM Artisan memory compiler for generating SRAMs. I generated .v and .lib files from it to carry out RTL ...
Abhishek Tyagi's user avatar
0 votes
1 answer
96 views

How does data reach peripherals in STM32H7xx?

I'm trying to understand bus interconnection matrix in stm32h7xx. Here is a capture of the H753's one: In particular, I'm wondering how a data buffer located in DTCM would reach the SPI1's tx ...
Martel's user avatar
  • 1,229
0 votes
1 answer
62 views

How to debug modbus rtu address space problems? [closed]

I have an "Ewon Flexy server" and an "IMO SD1 Inverter" connected via Modbus RTU RS485. I can change some of the parameters with Flexy interface and observe the change in the ...
Juha's user avatar
  • 188
0 votes
1 answer
807 views

RISC-V byte load and store

I have the confusion in the following RISC V programming statements. Can someone explain that why does the contents of s0 in the last comment shown. shouldn't it be 0x00000180 the same as we are not ...
kam1212's user avatar
  • 593
4 votes
1 answer
258 views

What are the possible implementations of LUT on silicon?

I'm looking for the possible ways to implement a LUT. The only way I know is to use Flip Flops to store the outputs and a MUX to select the output using the input as a select signal. Is there any ...
Hmdee's user avatar
  • 51
0 votes
2 answers
64 views

Faulty address line [closed]

how to find address line fault in microcontroller if microcontroller connected to external memory through address line? if given one line in address is faulty how to pinpoint the particular line ...
Mentee's user avatar
  • 1
0 votes
0 answers
42 views

Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?

Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
Sai Gautham's user avatar
0 votes
0 answers
159 views

what is the definition of one nCK in ddr?

If ddr4 runs at 1600Mhz, then what is the value of nCk? is it 625ps? if so, then does nCk simply means speed of one of clock cycle at which ddr4 runs?
Jen Parker's user avatar
0 votes
0 answers
104 views

SDHC card is read as SD by READ_OCR

I'm trying to use 32 GiB SDHC card in SPI mode but I have problem with initialization. I send SD_SEND_OP which finally returned 0x00 but it doesn't have CCS bit set: ...
Maciej Piechotka's user avatar
1 vote
1 answer
120 views

How does DDR SDRAM increase the bandwidth without increasing the frequency at which a memory array operates?

I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. ...
Diogo Landau's user avatar
0 votes
0 answers
60 views

Type of memory used to design Arbitrary Waveform Generators (AWGs)

i am interested in understanding how the design decision is taken while choosing the type of memory to be used in AWGs. My understanding is that in most AWGs, waveforms are stored in a Digital memory ...
Abhishek Tyagi's user avatar
3 votes
1 answer
222 views

How can I improve this RAM implementation in VHDL?

I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL. Exam question Write the VHDL code for ...
iknotum's user avatar
  • 33
0 votes
2 answers
839 views

Can I use flash memory to store application data?

Context: I am using STM32CubeIDE 1.11.0 on Linux to program (via ST-Link V2) my STM32f103c8t6 bluepill, boot mode is 00 ("Main Flash Memory") I have read the whole section about it in the ...
Santiago's user avatar
0 votes
0 answers
77 views

Transfer a received array to memory in real-time

I'm using STM32F407. I save the data read from a microphone via the HAL_I2S_Receive_DMA API using a circular buffer. I store the received data in an ...
KaleM's user avatar
  • 405

1
2 3 4 5
18