Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
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Doubt flash memory chip [closed]
What type of memory is used on the PCB of 2.5" and 3.5" HDDs to store BIOS/firmware and S.M.A.R.T files?
How many years will these chips retain data in my room temperature of 33-36C?
user394129
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System crashing HTTP execution with GSM module and STM32L053c8t6 MCU
Well, I'm developing a system for reading sensors and sending them to a server.
I'm using a GSM LTE module to do this sending. At first it worked well, but after a while the system stopped sending ...
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Creating specific flash memory area in STM32G0 microcontroller
I am trying to create a 2K flash memory region in which user defined const uint32_t will be stored. The project is built in Keil uVision. The microcontroller has 64K of flash memory. The idea is to ...
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Altera Max10 DDR2 termination scheme
I am trying to interface a Altera Max 10 FPGA to Micron MT47H256M8 DDR2 chip. I am little big confused about the termination scheme.
Are the ODT75 terminations selectable in the memory chip by the ...
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Interfacing ReRAM in-memory computing within a system
ReRAM-based IMC techniques are promising for ML inference. Many research papers propose ReRAM IMC techniques for accelerating NN operations. However, they do not discuss the system integration of the ...
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Single port ROM: how does the CPU read constant data?
I am looking at different CPU micro-architectures.
Frequently, it happens that the ROM is supposed to contain only instruction data. See below for an example:
In such design, how is the CPU supposed ...
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stm32 memory remap and bootloader
I am having some confusion regarding the stm32f446xx memory remap feature in the reference manual. The system configuration memory remap is used to change the memory at 0x00000000.
I am having some ...
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Bit Banding in STM32 CORTEX M4
I am confused in the bit banding of Cortex M4. I was going through the datasheet of STM32F446ZE and found in the memory map there was only written SRAM (112 kB aliased
By bit-banding) What does that ...
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How does PCIe work?
I have gotten very confused with how PCIe works. I read that PCIe is a memory mapped protocol. That is, if the GPU wants to write to the CPU it will access the DDR memory located on the motherboard ...
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Core memory output line question
How is a bit read from the core memory pictured below? I understand current through 1 and 1 vs 0 and 0 will change the torus magnets field setting a bit. I’m confused how this field is read back using ...
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Remote update firmware for MCU
I am planning to implement a remote firmware update for my MCU and seek recommendations on the necessary features for the MCU. Specifically, I would like to understand the requirements regarding ...
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Memory view is showing multiple bytes change after a single byte is assigned to a register. Why?
I am debugging an issue I have on a legacy codebase that is running on an atxmega32c4u chip. I am writing single bytes to registers in PORTC, but the memory view is showing multiple bytes change. The ...
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SRAM not writing properly after radiation exposure
I have an SRAM memory device GM76C88AL with this datasheet. The RAM was exposed to a radioactive beta source (~2MeV) for some time (about 2 hours). The source was just right above it (placed on it), ...
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Creating ping-pong buffer using a simple dual port RAM
In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can ...
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How to access more storage?
I am doing a project with an STM32 chip. It needs to access megabytes of storage, but the chip can only access up to 32 Kilobytes of Flash memory.
Is there a way to add more memory?
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Simplest way to interface a high-speed (125 Msps) ADC: FIFO, RAM, SerDes or FPGA
I have a 1.8 V, 125 Msps ADC (ADS4125) with an output of 12-bit parallel LVDS or CMOS. The system is operating in bursts: the data is sampled for 8 - 30 us, with a 100 ms wait time in between. I need ...
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How to handle unused 32-bit data, dqs and dbi on DDR4 SODIMM module
In a design, I have used a DDR4 SODIMM module, which has 64-bit data, thus 8 groups of data (DQ), DQS and DBI.
However, I will only use the lower 32 bit on the module, thus have to handle the ...
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
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Weird SRAM failures when heat is applied to the system and when probed
I'm providing assistance on a project that is encountering some interesting behavior on an SRAM memory device when environmental temperature goes up or when someone probes/touches lines associated ...
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Behaviour of uninitialised RAM in an ASIC
This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers.
We are using the ET1200 EtherCAT ASIC (...
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STM32H matrix-vector-multiply throughput
Ill be working with a board that has a STM32H743 on it, and I have a hard time reasoning about the f32 matrix-vector multiply performance I can expect of the m7 core. As I understand the core itself, ...
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What does transfer rate in RAM actually mean? How do you actually measure it?
From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
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Memory clock and Bus clock
The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
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What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
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Is the communication between memory controller and RAM serial?
I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this:
But then, from Wikipedia article on memory ...
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How to understand Register Address, Bits, and Reset value of an electronic component?
Source: Page 31 ADXL355 MEMS' Datasheet.
Source: Page 32 ADXL355 MEMS' Datasheet
The above is some of ADXL355 Accelerometer Register map table. From that table, in the RESET column, there are their ...
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Problem in executing the memory stage that can perform call, ret, pop, etc
I am trying to implement a Y86 processor for my college assignment.
This is my MemoryStage:
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How is the structure of a matrix addressable memory block realized?
Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
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Can't write to status register of SST25VF010A flash memory
I'm having trouble writing to the status register of a SST25VF010A-33-4I-SAE 1Mbit SPI flash memory on a board I recently made. I'm using an STM32F401CBU6 to communicate with the memory.
I can read ...
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Picking the best memory technology for our needs
This is my first post here, but bear with me. I have come here after searching the internet for a while (like most of us do)
We are in the process of figuring out which memory option would be the best ...
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What do NRAM cells look like?
Note: I don't have any electrical engineering experience, so I'd like to apologize for my bad vocabulary about this subject.
I'm currently exploring the memory world and stumbled across NRAM which got ...
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Why memory cell basis is typically "paired inverters" and not "paired forwarders", revisited
I asked over a year ago (link) about why memory cells typically use paired inverters instead of paired buffers. The answer mentioned gain, "this is basically because it's hard to make non-...
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Why do AVR microprocessors have two ways (paths) to access I/O ports?
I've an ATmega328P.
Register Summary Page 275 ATmega328P datasheet.
The first address is the I/O address, and the second is the data memory address.
I'm going to set all (D ports) Data Direction ...
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What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?
I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
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What is the theoretical maximum capacity of 72-pin RAM modules?
I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect.
This is my current understanding:
A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
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STM32H7 QuadSPI CMSIS Read
So, I am trying to access an APS6404 IC (PSRAM) with QSPI on STM32H7 (currently in single-line mode). When I am writing to it, everything seems fine, but as soon as I read - the FIFO is empty and the ...
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Memory Capacity and Memory Addresses
According to this site, in Table2, HBM(HBM2e) has a capacity of 8Gb = 2^33 bits per channel. Here, it has a 24-bit address consisting of 4 bits from the Bank address BA[3:0], 15 bits from the Row ...
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Is it wrong to use Thévenin's theorem on this memory circuit?
In my electricals beginner class I was given a paper about memory circuits. There was a small section about how writing data to a single memory cell worked.
Here is the sketch of the memory cell:
The ...
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How to handle flash write/read operations on STM32L552 with ICACHE enabled without disabling it?
I am currently working with an STM32L552 microcontroller and encountering some peculiar behavior when writing and reading double words to and from the flash memory. After writing data to a specific ...
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How I can store data code for LONG time 100-200y - ESP32, Arduino, Data Retention, Reliability, Lifetime, Flash
I'm working on a research project in winch we want embedded sensors and logic, an ESP32, inside building's pillar surrounded by concrete. The ESP32 collects data through sensors, process them and send ...
ganatoci
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Why is memory addressed using 2 address decoders only and not more? [duplicate]
I am currently taking a university course about computer architecture in which we learned basic DRAM architecture and addressing. As far as I know, each latch is selected using decoder outputs to ...
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Synchronising data input and filter coefficient so that both reach at same time and give filter output in semi parallel/parallel filter in Verilog
I have designed an 8-tap filter using 8 coefficients in a semi-parallel fashion. I want to get the correct output for a FIR filter design by using 8 DSPs and one SRLC32E register. Here I pass my input ...
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6502 Extra Cycles on Page Cross
On the 6502 processor, when using the Absolute,X, Absolute,Y or (Indirect),Y addressing ...
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MUX in a 4 bit by 3 bit memory
Here is a 3-bit adressable memory with an adress space of 4.
My question is why is the book calling the 3 rightmost highlighted circuits MUXes? And what type of MUXes are they? 4:1 MUX? And if it is ...
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Finding correct memory IC [closed]
I have a project where I need to store data (~16Mo) on a memory IC and be able to fetch the data fast (<36000bits/s) (with DMA in the idea).
My µcontroller is an Arduino DUE. So far I've tried a ...
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Reflashing firmware for preventive purposes
This is a relatively common malfunction for the installed firmware in some old electrical devices to become corrupted. I often see this in repair videos, and there's often an easy fix - reflash the ...
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Finding memories power dissipation
Can someone tell me how to calculate the power dissipation of digital ICs like NAND Flash, QSPI NOR Flash and microcontrollers?
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eMMC interfacing with EC200U SDIO Power domain
I need to interface my eMMC(THGBMJG6C1LBAU7) memory with EC200U from Quectel.
The Quectel E200U has two SDIO ports one is working at 3.3V power domain and
other one is working at 1.8V power domain.
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