Questions tagged [memory]

Consider instead more specific tags, e.g., dram, sram, flash

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Keil uVision Disassembly Window with ARM Microcontroller

I have a couple of probably simple questions for you all regarding disassembly from C code to assembly code. I am using Keil uVision as a programmer and debugger with a TIVA TM4C123GXL microcontroller ...
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10 votes
7 answers
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How do 16-bit addresses work inside 8-bit data bus processors?

As a project I am building a small 8-bit RISC processor out of discrete ICs. I have 17 instructions and cannot fit all information into instructions that are only one byte, so I have been thinking ...
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RISCV Mem Virtualization: Sv57x4 58-bit VA is longer than 56-bit PA, how to form it?

I'm exploring RISCV Priveleged Spec and got confused with memory virtualization (especially hypervisor part and two-stage addr translation). How can we form Sv57x4 Virtual Address (VA) for G-stage if ...
0 votes
1 answer
71 views

State of STM32 pins from factory and after chip erase

What is the state of pins for an STM32 MCU after chip erase or when the device is fresh from factory? I'm asking in search of a controlled way to power up and test a new board with STM32.
0 votes
2 answers
50 views

Bistable memory cell with paired buffers instead of paired inverters

Bistable memory cells with paired inverters are very standard and basic building blocks (was used in Intel 8086 for example. ) But why not use paired buffers instead?
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2 answers
196 views

One-bit memory circuit using transistors

I'm trying to redesign this flip-flop circuit on the picture so I can use it to store one bit of memory. This circuit on the picture is operated with pushbuttons, but I want to operate it via a ...
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2 votes
2 answers
60 views

STM32 SD mounting returns error with SDIO

Overview I'm using a STM32F407ZGT6 and I'm currently trying to mount SD cards (MicroSD 32GB HCI and 256GB XCI picture) to the board using the FATFS library bare-metal. To handle low level I/O, I'm ...
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2 votes
1 answer
86 views

Custom Memory Allocator - How to find the required alignment for a platform?

I'm building a portable arena allocator for embedded systems. Like for malloc, one of the requirements is to return a pointer aligned with the memory. The question ...
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1 vote
2 answers
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Is my understanding on flip flops accurate?

I have done a lot of research on flip flops so to speak and I have put together my understanding, please correct were I’m wrong. Flip flops are bistable multivibrators able to store two states (one ...
0 votes
0 answers
75 views

Spansion/Cypress S29GL512T Write buffer programming - can't exceed 64 words at a time

I'm having issues with the write buffer programming on these Spansion (Cypress) devices. I can do 64 words (128 bytes) all day long, but it fails when I go over that. The datasheet says it can do 512 ...
1 vote
1 answer
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How to design interfaces for memory hungry circuits

I'm new to hardware design and one thing I'm struggling with is how to structure the communication between circuits (components). In VHDL you use the port map ...
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0 answers
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Reading from CFI registers always fails - Parallal NOR Flash M29EW

I'm trying to interface a 1Gbit Parallel NOR Flash (M29EW) to my MCU (STM32L552ZET). The FMC was setup for 16-bit access/26 address lines. Also, this was done on a custom board. No jumper wires, no ...
0 votes
1 answer
47 views

DDR3 Termination resistor value regarding

In a design, my senior put a 49.9ohm termination resistor to terminate the control, address, and control lines.Here I can't find the correct explation for this. My question is, 1.How to choose the ...
5 votes
6 answers
562 views

Why are flip flops criss crossed

I want to simulate how a computer works using logic gates, now I am trying to build out the memory aspect of it. After looking at various articles and books I see a lot of them using flip-flops/...
0 votes
0 answers
69 views

DRAM Refresh Time

I am trying to understand, how can I calculate the refresh time of DRAM, if I consider that as my memory requirement, that I need is 32 DRAM chip of 1M * 1bit each to get 4MB Memory capacity. Each ...
8 votes
3 answers
3k views

How long can a micro SD card hold data without being powered? [closed]

I lost a micro SD card few years ego, and I'm worried that someone may find it and misuse the data stored in it. How long can a micro SD card keeps the data without being powered, ignoring other ...
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8 votes
4 answers
3k views

Why does this SRAM chip have more physical bits than declared by the manufacturer?

I noticed while scanning the datasheet for a 23K256 SRAM chip that it has 32768 bytes (+262Kbit.) The manufacturer clearly identifies this chip as 256Kbit. Reading through the datasheet it clearly ...
0 votes
1 answer
66 views

STM32H743 MDMA can't access APB2

I have a code that mdma can access any variable feed to it by &var (AXI SRAM) also I have gave it an address of ADC common registers from APB1 but adress from APB2 &hrng.Instance.DR causes ...
2 votes
1 answer
146 views

Why DMA can't approach global variable (STM32)?

I test memory to memory DMA with my STM32H750VBT. I study with following this link. enter link description here According this link, source is inside flash and destination is inside SRAM. I test ...
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2 votes
1 answer
276 views

Do ASCII or Unicode Bit-Level Anagrams exist? [closed]

Is there such a thing as a bit-level ASCII anagram, that forms a natural language word when the bits are interpreted as ASCII from left to right, but a different natural language word when interpreted ...
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-1 votes
1 answer
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Instrumentation Tools for Collecting Data in DRAM accesses

We can use instrumentation tools, such as Pin tool, to collect memory accesses of an application running on a system. The type (read or write) and memory address can be collected. How about data? Can ...
11 votes
3 answers
2k views

Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?

Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.) The thing I do not understand is that why we see only one memory address space. For example, in tge ...
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Calculation of capacitor of deep trench DRAM

If I know the depth of the trench L, the size of the DRAM node D and the thickness of oxide (say HfO2) T. How can I calculate the capacitor of a trench?
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1 vote
2 answers
90 views

Non volatile memory on simple hardware board [duplicate]

I'm designing a low frequency board with some analog signals inputs and a few discrete logic gates which drive warning LEDs. I want to save the status of the LED even if the board is powered off. No ...
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0 answers
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Advice on SIPO FIFO clock, as well as 555 timer usage

I've made a circuit which involves me entering inputs, and the result being displayed in a seven segment LED. The LED must flash on and off and display the input number at least two times in two ...
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1 answer
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How do I use a 4x2 ROM to build a 16x4 ROM?

I tried solving it but I'm not sure if I got it right
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4 answers
232 views

How are ones and zeroes stored in a computer physically?

As I mentioned in the title "physically", when the computer is off and there is no power, how are the bits stored? For example, how can an image be stored?
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0 answers
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Error after flashing the example on my esp32-c3 board

I am currently trying to develop software for a board I created a short time ago with the esp32c3 as microprocessor. I followed all the steps of the espressif 'get started'. I firstly set the ...
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1 vote
1 answer
64 views

How much skew correction can typically be applied to DQS during DDR4 link training?

My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync. Is there ...
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1 vote
1 answer
77 views

DDR3 Termination Resistors and VTT Capacitors

I have a DDR3 implemented in our current design with 50 Ohm 0402 termination resistors and 0.1uF 0402 decoupling capacitors to VTT on the address, data and control lines. The design is working well ...
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0 votes
1 answer
121 views

How do computer memories interact with each other (registers, cache, RAM, ROM)?

After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
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3 votes
3 answers
1k views

What kind of IC is this, and how can I erase its memory to reuse it?

I have a PCB with an IC on it. All I want is to erase its memory so that I can reuse the chip. Any help with what sort of chip is this, or how I can erase the memory, would be very helpful.
1 vote
0 answers
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DDR interfacing with rockers3399 processor

I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things *Support 2 channels, each channel is 16 or ...
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2 answers
111 views

Best memory choice for my sensor

I'm a software developer and trodding in murky waters here so please do forgive my lack of knowledge. I've been developing a sensor with the nRF9160DK and some accelerometers. I need to continuously ...
1 vote
2 answers
196 views

STM32 bare-metal programming - Memory addressing in 32-bit system - memory offset

I am coming from a mechanical background and some Atmega experience, now doing some bare-metal programming courses on ARM processors. So far it is looking great, digging into documentation about uC ...
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0 answers
36 views

For SDRAM, how to tell how many ranks supported in each channel?

This is from Wiki: As an example, take an i945 memory controller with four Kingston KHX6400D2/1G memory modules, where each module has a capacity of 1 GiB. Kingston describes each module as composed ...
0 votes
2 answers
343 views

How do embedded systems deal with virtual and physical memory addressing?

I'm referring to the Wikipedia page about virtual memory, the last paragraph in Usage section: Embedded systems and other special-purpose computer systems that require very fast and/or very ...
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0 votes
2 answers
113 views

Saving a bit state with OR Gate using transistor doesn't work

I want make simple 1-bit memory using OR Gate like this picture It's working what I expect when using OR gate component. I change first input state to 1 so that it will give an output state of 1. ...
-2 votes
2 answers
197 views

What type of code is being stored in microcontroller RAM section? [closed]

The program memory layout looks like this: But in every embedded forum it is said that: Code is being stored in flash memory, RAM memory is for data Therefore, ...
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1 answer
35 views

How to interpret internal_ram data section in NXP

In .lcf (linker configuration file) in my project, in SRAM memory there is an internal_ram section: And in my case this ...
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0 votes
2 answers
136 views

How many times can a register bit be changed in AVR?

I am writing a program for an ATmega328P. I have a while loop inside which I am enabling the UART receiver complete interrupt flag using the command ...
0 votes
1 answer
100 views

Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?

The generated pinout does not list any VRP or VRN pins, or anything similar. I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
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0 votes
1 answer
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Why we used 128 bytes internal RAM memory instead of 256 bytes in 8051?

... since using 7-bit in 8-bit address bus wastes one wire. In 8051 there is a 8-bit address bus for internal RAM out of which we just use 7 wires making it addressable to just 128 byte locations, why ...
11 votes
9 answers
5k views

Best way to store very small amount of data?

I'm building a side project at the moment and I want to be able to store and retrieve a very small amount of data (10 kB tops). If the power is disconnected I want to be able to retain the data. I ...
12 votes
1 answer
2k views

How can I initialize/use SD cards with SPI?

I've seen various blog and forum posts, tutorials and application notes about accessing SD cards with microcontrollers using SPI, but I struggled a lot at different points when following them. In my ...
0 votes
1 answer
69 views

Externally triggered high impedance toggle for large number of parallel lines

First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty. I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address ...
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1 vote
2 answers
84 views

Basic memory element circuit

I am a beginner in digital electronics. I just completed combinational circuits and got introduced to sequential circuits. I come to know that a cascaded NOT gate circuit as follows: acts as a basic ...
1 vote
0 answers
143 views

Working with STM32 flash memories.. on renode

I am a newbie on embedded flash memories and in particular my university assigned me a job with them on a stm32f407 MCU. I have to work with renode (don't ask me why, they want so) and it has 0 ...
0 votes
4 answers
158 views

What are technical challenges of implementing DRAM memory modules on SBC like Raspberry PI?

I'm surprised to see no Single-Board Computer including Raspberry PI has memory modules for allow for flexible amount of memory (e.g. this review). And I have not found such discussions via web search,...
3 votes
2 answers
649 views

maximum memory supported by processor - why often stated less than 1TB?

I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki: Modern 64-bit processors such ...

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