Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
623
questions
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Why do we need interleaved memory?
I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says:
Interleaved memory results in contiguous reads (which are common both
in ...
0
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2answers
46 views
SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?
What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits?
Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
0
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1answer
38 views
Read-only for some masters but read-write for other?
Is it possible that a memory/memory region be read-only for some masters/chip components but read-write for others?
It is kind of vague question, but from a conceptual point view would this be ...
2
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0answers
26 views
eMMC Jedec Backward Compatibility
I'm working on a new design based on a Xilinx FPGA.
I'd like to use some eMMC devices but the FPGA controller supports JEDEC up to 4.51.
Nowadays, some eMMC devices are JEDEC 5.0 or 5.1 compliant ...
1
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1answer
115 views
PCB sound memory for toys [closed]
I want to build a toy. The initial build will be a prototype but if the idea 'sells,' I want to build en-masse.
For the prototype, as I do not have (beyond what I learnt at Uni) industry experience, ...
1
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1answer
111 views
Amplifier memory distortion application
I've found an article about memory distortion issues in audio analog amplifiers. Available for free here.
The author uses in the last configuration a CFP differential input with a cascode of FET ...
1
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1answer
51 views
Cortex-M3, Code region vs SRAM/RAM
In the ARM Cortex-M3 processor core, the memory map contains: a Code region, SRAM and a RAM. What makes the use of the code region different than the other memories? In addition, what is the nature of ...
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0answers
46 views
eMMC selection problem due to lifecycle
As you know while considering eMMC's lifecycle there are 3 technologies called SLC, MLC, and TLC.
But I could not understand exact speed of these. i.e. MLC's lifecycle.
Some say 3k like this one.
...
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0answers
50 views
Problems with Memory Initialization in Quartus
I have the following code snippet in my VHDL code to initialize a ROM block:
...
0
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1answer
83 views
Can a memory chip have a certain starting address
In my book there is a question stated:
Can a memory chip of capacity 512 KB have the starting address
2B0000h?
To me this seems like an incomplete question with a wrong answer in the book. The ...
1
vote
1answer
51 views
Diode ROM with decoder and multiplexers
I have this question on my exam I couldn't answer:
A diode ROM has been built using a decoder and multiplexers. If A4A3A2A1A0 = 01001, what is D3D2D1D0?
Here is the first schematic:
The answer is ...
2
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0answers
48 views
DDR3 SODIMM slow clock specification
I am considering to design memory controller handling 1GB of the RAM. I did already design controller for Micron's 32MB SDRAM in the past using Cyclone III device.
The new design is for retro ...
0
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1answer
85 views
Design this memory with D Flip-Flops
Design the following memory with D Flip-Flops. (you can use other gates or decoder if needed)
The following memory has 4 one-bit locations and can access 2 locations in each moment and read from ...
0
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1answer
66 views
Are Tri-state buffers even necessary?
I'm trying to make a 1-bit computer, and I'm stuck on the registers. I think I am going to have 2 of them, and I want a way to separate their outputs. Let me explain. Let's say Register A has a 0, and ...
0
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1answer
41 views
Temperature and flash corruption in microcontrollers
I'm repairing quite the pricey device, where a strain gauge failed. It's a pressurized device, and the strain gauge measures the internal pressure by means of it. The crux of the matter is that the ...
0
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2answers
65 views
Memory-mapped IO vs Port-mapped IO in microcontrollers
I've been reading about external peripheral mapping to microcontrollers.
I understand that memory-mapped IO means that the same address space in the microcontroller can be used for internal memory ...
0
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1answer
37 views
What is the delay incurred by ternary content-addressable memory (TCAM)?
What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM?
I understand their use cases are different. But assume, for an application, I can do an operation using ...
0
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1answer
53 views
How is the memory space calculated as 64KB for this MCU memory?
When it is about an 16 bit microcontroller with 16-bit adress 0xFFFF(the largest 16-bit number is 0xFFFF in hex or 65535 in decimal) the following picture is given and total memory space is given as ...
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1answer
37 views
DRAM late and early read and write
For read operation in DRAM, perform early read mean OE low before CAS is low so doesn't this mean that you just read in junk data ?
For write operation, i don't think there any problem with early ...
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0answers
25 views
Information about component quality in general and quality of memory IS25LP128-JBL
Most of us are faced with component quality especially when producing product in higher quantities. What is he right place to find information about component quality in general?
Currently we faced ...
0
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0answers
49 views
DRAM Memory Lines
I have been trying to understand DDR and DRAM memories and stumbled upon this video
In this video, from 20:00 to 23:00 he tells that the 8kb row buffer lines, actually come out as 64b and this 64b ...
0
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1answer
40 views
What is voltage level in DDR5 defined by JEDEC?
Voltage level in DDR4 is 1.2 volt, will it be same in DRR5 also? Also how much maximum voltage fluctuation will be allowed?
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3answers
66 views
External Memory IC which increments data on a clock pin
I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following:
Store 1MB of data of 16-bit data
This data is stored at specific ...
1
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1answer
94 views
Cortex M4 memory management suggestions: best data/code placement
I'm trying to implement a rather complex (at least for me!) system on a Cortex M4 mcu: LPC4370. This one has HighSpeed ADC (up to 80Msps), DMA and DSP (Single Instruction Multiple Data) instructions.
...
0
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1answer
50 views
Memory Boundaries in SRAM
I am trying to use the GPDMA which is present in LPC43XX parts.
The UM10503 data sheet constantly warns about memory boundaries (datasheet section 21): basically it says that you don't want to try a ...
1
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1answer
62 views
Is writing in FeRAM memory cell destructive?
I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
0
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3answers
127 views
Is there any memory cell that can store more than one bit? [closed]
SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
0
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1answer
71 views
Combine two 8bit EEPROM to make 16bit EEPROM
I am working on building a computer out of logic chips.
I want to use an EEPROM as the instruction memory. However, my EEPROM's only has 8bits data output, but I want my instructions to be 16bits long....
0
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2answers
64 views
STM32F103rb datasheet mentions 4gb address space, while only 128kb flash and 20kb RAM?
I am trying to advance my way into the STM32F103RB, and I don't understand the address space mapping defined in chapter 3.2 in the the STM32F103RB datasheet.
It states:
Program memory, data memory,...
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1answer
97 views
In practical, what really is a memory word in PLC?
I came across some plc code (structured text) being used in an industrial company. When I asked the question, I got a blurry answer. However, what I picked up is that it has something to do with the ...
0
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1answer
82 views
Help with understanding the Memory Map of MLX90393
(Using a Raspberry Pi 3 Model B+ and python)
I needed some assistance in understanding the memory map of MLX90393
I've attached the memory map here and you could also find it in the datasheet.
I'm a ...
0
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1answer
53 views
Adapt EEPROM EMULATOR STM32F103VE
I'm working with STM32F103VE and STM32F746, and i want to use my Flash memory as EEPROM EMULATOR for writing and reading data easily.
I have searched for axemples of Emulation of EEPROM for my board ...
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2answers
53 views
Data Bus and High Impedance
Let's consider an interface between a simple microprocessor and a certain memory. For instance, let's assume that the microprocessor drives the address bus, a read signal, a write signal, and that the ...
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2answers
52 views
Data transfer from/to memory [closed]
Consider an interface (between a memory and a processor, or between a memory and an ASIC, or similar situations) in which there is a data bus of 8 bit. Suppose I want read a 16 bit data from memory, ...
0
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3answers
113 views
RAM and Flash structure difference
I am trying to get a better understanding for RAM and Flash and I hope you could help me out with some things.
What I know about Flash (or at least I think to know), is that there are different Flash ...
-1
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3answers
98 views
Startup code in pure Assembly program [closed]
I came across some articles and books that saying when, I write in high-level language like C, startup code is used to prepare for my main code but when I write my program in pure Assembly there is no ...
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2answers
68 views
Linker script and data allocation
I know that .data will be in the RAM, but I came across article that says during boot of an micro-controller the initial value of variables is stored in the ROM and ...
2
votes
1answer
52 views
Writing data to memory devices [closed]
Do all memory devices use shift registers for writing data to memory?
For example
USB, EEPROM, RAM
Serial in and parallel out into memory devices data in lines?
Or
Parallel in parallel out into ...
0
votes
1answer
93 views
How is an EEPROM different from a Flash memory? [duplicate]
I am trying to understand the terminology used for various non-volatile memory chips for example as EEPROM and Flash.
Is there any preference to use the word EEPROM or Flash for specific type of ...
3
votes
2answers
98 views
How to detect Corrupt Flash Memory? [closed]
I am checking PCB board of a commercial device that has W25Q256JV 32MByte SPI Flash on it. The device is in use for more than a year now at more than 2000 client locations. It has internal backup ...
4
votes
1answer
104 views
Building a byte-addressable memory
I am building a memory module:
32 bits wide,
parallel, and,
byte-addressable.
I did a research and i could not find an memory IC that will suit my needs.
It ...
5
votes
4answers
2k views
Memory capability and powers of 2
Why are computer memory capabilities often multiples of a power of two, such as 2^10 = 1024 bytes?
I think it is something related to the binary logic, but I do not understand the precise reason for ...
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0answers
49 views
Writing Flash Memory Serially
I am looking into writing data onto some Flash memory serially, the requirement is to replace the old parallel programmer with a serial based programmer example Cheetah SPI Host Adapter. The Flash ...
3
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1answer
133 views
What's the difference between 1kb(64x16) and 1kb(128x8) for EEPROM memory size?
In addition to the question in the title, I have the following subquestions:
I'm guessing 64x16 means something like 64 cells of 16 bytes each. Is this accurate?
What is the significance (if any) of ...
0
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2answers
63 views
Reading current memory image from a micro controller
I have the MPLAB XPress Evaluation Board, which has the PIC16F18855 microcontroller on it. The way to program it is just to copy a ...
2
votes
1answer
94 views
How can I protect a microcontroller from memory corruption due to buffer overruns? [closed]
I have recently been working on what I believe is a buffer overrun problem in a microcontroller with software that I wrote. I'm using an Atmega328PB, so it has no such thing as a MMU or address space ...
5
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1answer
122 views
why pre-post amble is required?
why do we need pre-post amble for READ or WRITE DQS ?
1 ) one reason could be -->
Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
0
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2answers
80 views
DDR UDQS and LDQS into one DQS controller
I have one x16 memory chip () that has two Data Strobe pairs (UDQS and LDQS), on the other hand, I have arm chip (i.MX6 ULZ) that has one Data Strobe pair (DQS). Is there any way of connecting them, I'...
12
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7answers
3k views
Need a non-volatile memory IC with near unlimited read/write operations capability
I need a memory solution which is going to be used to keep track of an accumulated count on a micro-controller based project.
By accumulated count, I mean to say that the micro-controller uses this ...
1
vote
1answer
123 views
Causes for Double Bit error
If I have a 1 Gb memory with EDAC for single bit correction for a critical application, what could cause a double bit error in this memory? Provided that the queues never get out of sync which causes ...
