Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
717
questions
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HyperRAM Linear Burst size throughput
Turned out to be a lengthy question, please feel free to skip and go directly to the questions
Intro
I am considering utilizing a HyperRAM in the next design, and studying the datasheet has lead me to ...
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1answer
33 views
How do you figure out the decoder inputs for a memory expansion?
How do you know what the two inputs will be for this 2-to-4 decoder? Also, what changes would be made to the circuit if the 2 data lines are not the same?
The original problem:
I drew the circuit, ...
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2answers
115 views
Is not it too much memory consumption for a simple thing?
I was trying to lower the memory consumption in my project and realized that a simple change of "uint8_t" value to the "define" shows effect much more and I thought. It seems I'm ...
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36 views
How do I get the number of address lines of 12G * 64?
The example problems I'm seeing in the book gives me nice numbers where the size of the ram can easily fit into a power of 2, but this one doesn't.
The original question:
This is all I have:
I was ...
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1answer
27 views
Micron MT25QL512ABB8ESF-0SIT not working after Non Volatile Configuration register setting
I'm using the STM32H7 Evaluation board. There is an on-chip QSPI DUAL NOR CHIP MT25QL512ABB8ESF-0SIT. After setting up the Non-volatile configurations Register value to 0x89D6 and power cycle, FLASH ...
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2answers
42 views
SPD I2c Address for DDR4 SODIMM
While designing DDR4 SODDIM schematic for a mini-pc motherboard, I understood that I need to set an address to Serial Presence Detect (SPD) EEPROM so the CPU can identify the memory.
While looking at ...
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2answers
89 views
Difference between ARM7 and intel i3, i5 & i7 processors
I am just starting out on a journey to understand microcontroller and microprocessor design. Have read briefly on their differences (ARM7 and Intel i3, i5 & i7).
Couldn't find any information on ...
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2answers
146 views
Reading SPI flash W25Q128FV with raspberry pi, what am I doing wrong?
This is the pinout I have for the flash memory W25Q128FV which I'm trying to interact with
I'm trying to control it with a raspberry pi 3 B+.
Here's how I wired everything:
...
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1answer
48 views
Termination Regulator for DDR4
I went through a previous Industrial PC Motherboard design in my company where Ritchtek RT9045 was used for DDR4 design. it's clearly recommended tat this device is ideal for DDRII/DDRIII in the ...
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1answer
25 views
Memory row driver does not have enough driving power
I am building the row driver of a piece of RRAM. Different from traditional memory, RRAM's cells are composed of resistor-like elements. I tried using a single inverter and a back-to-back inverter ...
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1answer
59 views
How to prevent a function from overwriting memory?
I'm writing a program that basically aquires samples from a signal and does FFT on it (I'm using STM32L432KC MCU). I'm trying to send results from the FFT calculations through UART but there is a ...
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1answer
35 views
Unexpected behaviour of data memory in modelsim testbench
I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not
understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
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0answers
16 views
How do I read the value of registers in Logism?
I am designing a CPU in logism. One of the components of the CPU is a register circuit (RegFile), which stores the registers data. The register circuit (RegFile) is shown below:
I am able to write ...
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0answers
29 views
Do SRAM Macros register the inputs?
In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file).
My question is this: SRAMs ...
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1answer
87 views
Logism: Rising-Edge J-K flip-flop outputs 0 when J = 1 and K = 0 [closed]
According to the truth table of the J-K flip-flop:
When J = 1, K = 0, and CLK (Clock Signal) = 1, Q = 1.
FYI, the flip-flop is a Rising-Edge flip-flop. Below are the timing diagrams which show the ...
1
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1answer
67 views
tRAS definition for DDR memory
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
1
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1answer
42 views
Industry Standard for Memory Address Decoder Design
I am currently designing the address decoder of a piece of ReRAM that will be sent to TSMC and manufactured. I have studied in class and textbook that there are two common address decoder designs. One ...
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2answers
63 views
STM32 runtime Variable value manipulation
So basically I am not an expert, altho I think I have a good basis of knowledge.
I am using an STM32 Cortex 4 (discovery) for a hobby CNC machining application.
So lets assume we have a SW under ...
2
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2answers
89 views
How to reason about this 'adder with memory' circuit?
I'm reading through "Code" by Charles Petzold and I had a question about the following circuit illustrated in the book:
Let's assume that the latches in the 16-bit counter and the 8-bit ...
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4answers
150 views
Why is bool type typically 1 byte long?
I was reading: https://www.quora.com/Why-is-the-bool-type-typically-8-bits-long
And the answer was:
Because it’s the smallest type that has an individual memory address
so that you can take a pointer ...
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2answers
43 views
Do bank/rows/columns based NOR flash memory exist?
SDRAM supports more addresses than their address bus width allows thanks to the bank/row/column scheme it's based on.
My question is if there are non volatile parallel memories that are based on the ...
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1answer
30 views
Operative Definitions of Memory in Circuits
I've been studying Memristors (non-ideal) and some related circuits depending on pinched hysteresis of the IV for use in memory. I'm still puzzled by the lack of general framework for what constitutes ...
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1answer
58 views
What is scratchpad memory?
What is a scratchpad memory?
I mean I get the article in principle, but I can't figure out how it exactly differs from other memories e.g. L1 Cache.
It
is a high-speed internal memory used for ...
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2answers
150 views
ALU result is 0, how to fix this?
In system-verilog I am trying to build a small ALU unit which takes a and calculates the negative value of it (-1) in a CPU.
I wrote:
...
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2answers
128 views
Building a 2x8 memory using flip-flops and logic gates
The image represents a 4x3 memory.Build a 2x8 memory.
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1answer
55 views
How does this expanded memory bus work?
I'm reverse engineering a laser printer (Laserjet 1320) and I need to infer some things about the memory bus. The full schematic I've made while reversing is here (in pdf) on Drive. I'm not all that ...
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3answers
79 views
Would this type of design be scale-able? [closed]
With current technologies within a modern system, we have pushed the limits of computations within the CPU portion of the system where it now exceeds that of the memory units. Moving memory is slow ...
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1answer
40 views
GPIO Boundary Address confusion
Background
I'm currently digging into STM32L0 series and I stumbled something I couldn't answer.
According the the datasheet page 58 we can see all the peripherals are clumped into a section of 512 MB,...
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1answer
41 views
Decoupling data fetching from processing and publishing
I am a software developer working on a personal project involving Raspberry Pi, Arduino and accelerometer sensors.
I already asked this question in the iot.stackexchange but I haven't had much luck. I ...
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0answers
20 views
Lines transferred from main memory to Cache
I'm studying Cache memories and I would like to know exactly how the lines are transferred from memory to cache.
Supposing I have a 32-bit machine with a 16kB directly mapped cache and 8 words per ...
0
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1answer
38 views
Specifying the address range of each memory block
Four 16x4bit blocks are interconnected to form a 64-bit memory as shown below
First of all why is a block here called 16x4bit ; 4 bits are related to the input gates but what's with 16 here ?
I also ...
0
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1answer
63 views
DRAM cells capacitor operation
I have a question about reading and writing operations.
Say if i wanted to read or write the column WL0, i would enable the WL0 lines.
For either a read of a write i would drive the bit lines to ...
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0answers
38 views
DRAM, multi-channel, memory access
I'm looking for a way, under any configuration/OS(windows or linux)/programming language you suggest to simultaneously access memory addresses, that are under different channels, meaning the access ...
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0answers
82 views
How do I transfer contents of one memory to another in one clock cycle
I have a 9 X 8 memory with me, there are 9 memory addresses with a byte of data in each.
I need to transfer the contents of this memory to a sub module but I'm one cycle.
...
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0answers
25 views
Confused on How to Determine Block Size of a Cache
I have some confusion on determining the block size of a cache. I read that to get the block size, you do 2^(block offset bits). However, if you're given a block offset and a byte offset, do you ...
1
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1answer
88 views
Why my register file operates abnormally
I tried to implement a 32x32 bit register file using Logisim, however once I have finished drawing and proceeded to test it by initializing the content of individuals registers to zero using the reset ...
1
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1answer
45 views
Trouble Storing Information in D Flip Flop
So I'm really not understanding how to store bits in flip flops and have them enable for to change on a condition. Here's the general setup that I'm trying to do but it just doesn't seem to work.
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2answers
101 views
Why are transparent latches discouraged / encouraged in digital design?
I have come across material per review from my past encounters with digital sequential logic and I wanted to pose a specific and hopefully general question for the community to help shed some light.
I ...
0
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2answers
72 views
Why are DRAM cells laid out in a square with regards to demux size?
I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of....
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1answer
38 views
DDR4 DIMM/component, different CL?
I'm learning the DDR4 technology and I don't understand how the DIMM/component can change its CL automatically.
FPGAs/ASICs can basically choose the frequency to apply to the DIMM/component.
Why do ...
0
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1answer
84 views
Difference between 24 bit and 32 bit addressing mode in QSPI flash
I would like to know the difference between 24-bit and 32-bit QSPI flash? why 24-bit address is used in flash?
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0answers
65 views
Harvard architecture total bus count
This might be a simple or obvious question but I wasn't able to find a distinctive answer to it.
To actually access memory, a processor writes an value to an address bus and recieves the data on the ...
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1answer
64 views
The total size of 32-bit memory address, 32-bit data words memory arrays?
I see that the total size of 32Kb = 32 x 1Kb.
The ARM architecture uses 32-bit memory addresses and 32-bit data words.
This means, the ARM memory array depth-width is 2^32 words and 32-bit, which is ...
0
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3answers
106 views
Storing data for a really really long time [closed]
How might one store data for the far future? (100 years and up, possibly centuries)
This is entirely hypothetical but would it be possible for semiconductor based data storage to have similar ...
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0answers
20 views
Recover correct value from unstable memory through read operation
We are given a memory with 32-bit width for each word. it has the length (N - number of rows) which is not relevant for the question. we know that the memory has a problem where at any row, one bit ...
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0answers
16 views
Why are the mosfet gate tunneling currents disappearing in a bsim4 simulation under a width and/or length of 10µm? (TSMC65)
I am trying to simulate the current from the gate of a mosfet to its body (drain, source and bulk are shorted). But with a downscaling of the transistor the current disappears abruptly and fully under ...
3
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2answers
141 views
ATmega: Can one determine if an address is program memory or data memory?
On an Atmel ATmega1284 (or any of its AVR cousins), is there any way to determine at compile time or at runtime whether an address that is passed to a function belongs to program memory space or data ...
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1answer
44 views
How to Use Addresses with Single Port RAM on FPGA
I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means ...
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3answers
78 views
Calculating RAM memory capacity from schematic symbol
Is it possible to calculate the memory capacity of a RAM given its schematic symbol?
I made a first guess from an example but seems to be incorrect:
If the address bus is 15-bit width, there are a ...
0
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2answers
71 views
ddr3 content after intialization
I am verifying a memory interface to MIG IP from Xilinx.
The MIG IP is connected to a ddr3 SDRAM from Micron. I have a ddr3 model from Micron that I included in my testbench.
I waited until the ...
