Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
788
questions
-4
votes
0
answers
45
views
Where is bios stored in MSI GF63 THIN 9SC laptop? [closed]
I have wanted to know in which component the bios of my laptop is stored, but I cannot identify where it is stored.
I have read that in newer laptops the configuration is stored in eeprom memories and ...
0
votes
0
answers
42
views
DRAM Refresh Time
I am trying to understand, how can I calculate the refresh time of DRAM, if I consider that as my memory requirement, that I need is 32 DRAM chip of 1M * 1bit each to get 4MB Memory capacity. Each ...
8
votes
3
answers
2k
views
How long can a micro SD card hold data without being powered? [closed]
I lost a micro SD card few years ego, and I'm worried that someone may find it and misuse the data stored in it.
How long can a micro SD card keeps the data without being powered, ignoring other ...
- 83
8
votes
4
answers
3k
views
Why does this SRAM chip have more physical bits than declared by the manufacturer?
I noticed while scanning the datasheet for a 23K256 SRAM chip that it has 32768 bytes (+262Kbit.)
The manufacturer clearly identifies this chip as 256Kbit.
Reading through the datasheet it clearly ...
- 199
0
votes
1
answer
38
views
STM32H743 MDMA can't access APB2
I have a code that mdma can access any variable feed to it by &var (AXI SRAM) also I have gave it an address of ADC common registers from APB1 but adress from APB2 &hrng.Instance.DR causes ...
- 444
1
vote
1
answer
71
views
STM32) Why DMA can't approach global variable?
I test memory to memory DMA with my STM32H750VBT.
I study with following this link. enter link description here
According this link, source is inside flash and destination is inside SRAM.
I test ...
- 105
2
votes
1
answer
263
views
Do ASCII or Unicode Bit-Level Anagrams exist? [closed]
Is there such a thing as a bit-level ASCII anagram, that forms a natural language word when the bits are interpreted as ASCII from left to right, but a different natural language word when interpreted ...
- 2,925
-1
votes
1
answer
57
views
Instrumentation Tools for Collecting Data in DRAM accesses
We can use instrumentation tools, such as Pin tool, to collect memory accesses of an application running on a system. The type (read or write) and memory address can be collected. How about data? Can ...
11
votes
3
answers
1k
views
Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?
Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.)
The thing I do not understand is that why we see only one memory address space. For example, in tge ...
- 165
0
votes
0
answers
30
views
Calculation of capacitor of deep trench DRAM
If I know the depth of the trench L, the size of the DRAM node D and the thickness of oxide (say HfO2) T. How can I calculate the capacitor of a trench?
- 11
1
vote
2
answers
76
views
Non volatile memory on simple hardware board [duplicate]
I'm designing a low frequency board with some analog signals inputs and a few discrete logic gates which drive warning LEDs. I want to save the status of the LED even if the board is powered off. No ...
- 33
0
votes
0
answers
42
views
How do I configure the DDR controller in an FPGA?
I am a beginner with FPGAs and I am trying to run a 'Hello world' project on a Zynq Ultrascale+ SoC (my SoC is the ZU3EG).
The ZU3EG is mounted on a development-board which contains the following ...
- 63
0
votes
0
answers
31
views
Advice on SIPO FIFO clock, as well as 555 timer usage
I've made a circuit which involves me entering inputs, and the result being displayed in a seven segment LED. The LED must flash on and off and display the input number at least two times in two ...
- 37
0
votes
1
answer
66
views
How do I use a 4x2 ROM to build a 16x4 ROM?
I tried solving it but I'm not sure if I got it right
- 25
0
votes
4
answers
206
views
How are ones and zeroes stored in a computer physically?
As I mentioned in the title "physically", when the computer is off and there is no power, how are the bits stored? For example, how can an image be stored?
- 69
0
votes
0
answers
34
views
Error after flashing the example on my esp32-c3 board
I am currently trying to develop software for a board I created a short time ago with the esp32c3 as microprocessor.
I followed all the steps of the espressif 'get started'.
I firstly set the ...
- 125
1
vote
1
answer
37
views
How much skew correction can typically be applied to DQS during DDR4 link training?
My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there ...
- 6,647
1
vote
1
answer
45
views
DDR3 Termination Resistors and VTT Capacitors
I have a DDR3 implemented in our current design with 50 Ohm 0402 termination resistors and 0.1uF 0402 decoupling capacitors to VTT on the address, data and control lines. The design is working well ...
- 56
0
votes
1
answer
69
views
How do computer memories interact with each other (registers, cache, RAM, ROM)?
After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
- 103
3
votes
3
answers
999
views
What kind of IC is this, and how can I erase its memory to reuse it?
I have a PCB with an IC on it.
All I want is to erase its memory so that I can reuse the chip.
Any help with what sort of chip is this, or how I can erase the memory, would be very helpful.
- 67
1
vote
0
answers
26
views
DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
- 572
0
votes
2
answers
110
views
Best memory choice for my sensor
I'm a software developer and trodding in murky waters here so please do forgive my lack of knowledge. I've been developing a sensor with the nRF9160DK and some accelerometers. I need to continuously ...
1
vote
2
answers
92
views
STM32 bare-metal programming - Memory addressing in 32-bit system - memory offset
I am coming from a mechanical background and some Atmega experience, now doing some bare-metal programming courses on ARM processors. So far it is looking great, digging into documentation about uC ...
- 47
0
votes
0
answers
26
views
For SDRAM, how to tell how many ranks supported in each channel?
This is from Wiki:
As an example, take an i945 memory controller with
four Kingston KHX6400D2/1G memory modules, where each module has a
capacity of 1 GiB. Kingston describes each module as composed ...
- 37
0
votes
2
answers
185
views
How do embedded systems deal with virtual and physical memory addressing?
I'm referring to the Wikipedia page about virtual memory, the last paragraph in Usage section:
Embedded systems and other special-purpose computer systems that require very fast and/or very ...
- 175
0
votes
2
answers
79
views
Saving a bit state with OR Gate using transistor doesn't work
I want make simple 1-bit memory using OR Gate like this picture
It's working what I expect when using OR gate component. I change first input state to 1 so that it will give an output state of 1. ...
-2
votes
2
answers
116
views
What type of code is being stored in microcontroller RAM section? [closed]
The program memory layout looks like this:
But in every embedded forum it is said that:
Code is being stored in flash memory, RAM memory is for data
Therefore, ...
- 175
0
votes
1
answer
32
views
How to interpret internal_ram data section in NXP
In .lcf (linker configuration file) in my project, in SRAM memory there is an internal_ram section:
And in my case this ...
- 175
0
votes
2
answers
130
views
How many times can a register bit be changed in AVR?
I am writing a program for an ATmega328P.
I have a while loop inside which I am enabling the UART receiver complete interrupt flag using the command ...
- 163
0
votes
1
answer
51
views
Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?
The generated pinout does not list any VRP or VRN pins, or anything similar.
I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
- 529
0
votes
1
answer
112
views
Why we used 128 bytes internal RAM memory instead of 256 bytes in 8051?
... since using 7-bit in 8-bit address bus wastes one wire.
In 8051 there is a 8-bit address bus for internal RAM out of which we just use 7 wires making it addressable to just 128 byte locations, why ...
11
votes
9
answers
5k
views
Best way to store very small amount of data?
I'm building a side project at the moment and I want to be able to store and retrieve a very small amount of data (10 kB tops). If the power is disconnected I want to be able to retain the data. I ...
0
votes
0
answers
51
views
Configuration Memory Device Nexys A7-50T
I have a question about configuring the memory device of the Nexys A7.
How do I program my .bit file in Vivado such that the FPGA board will run the program as soon as it is powered on? I cannot find ...
- 11
12
votes
1
answer
1k
views
How can I initialize/use SD cards with SPI?
I've seen various blog and forum posts, tutorials and application notes about accessing SD cards with microcontrollers using SPI, but I struggled a lot at different points when following them.
In my ...
- 491
0
votes
1
answer
63
views
Externally triggered high impedance toggle for large number of parallel lines
First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty.
I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address ...
- 131
1
vote
2
answers
67
views
Basic memory element circuit
I am a beginner in digital electronics. I just completed combinational circuits and got introduced to sequential circuits.
I come to know that a cascaded NOT gate circuit as follows:
acts as a basic ...
- 111
1
vote
0
answers
81
views
Working with STM32 flash memories.. on renode
I am a newbie on embedded flash memories and in particular my university assigned me a job with them on a stm32f407 MCU.
I have to work with renode (don't ask me why, they want so) and it has 0 ...
0
votes
4
answers
131
views
What are technical challenges of implementing DRAM memory modules on SBC like Raspberry PI?
I'm surprised to see no Single-Board Computer including Raspberry PI has memory modules for allow for flexible amount of memory (e.g. this review). And I have not found such discussions via web search,...
- 187
3
votes
2
answers
469
views
maximum memory supported by processor - why often stated less than 1TB?
I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki:
Modern 64-bit processors such ...
- 187
0
votes
0
answers
37
views
What is the difference between Content Memory Addressing (CMA) and Content Addressable Memory (CAM)?
I have been looking over the internet for Content Memory Addressing(CMA) but whenever I search for it I get Content Addressable Memory (CAM). So I am confused, is CMA and CAM the same thing. If ...
1
vote
1
answer
100
views
Strange behavior of flash memory S29AL016J
Recently I was looking for a replacement for my old flash memory chip. I've soldered a S29AL016J memory chip in my boards and started checking if everything worked correctly like with my previous ...
- 129
1
vote
0
answers
72
views
Memory Mapping Table
I am a begginer in the field of microcomputers and their architecture and recently I got an assignment with the following instructions:
With the use of the mapping table find out which adresses in ...
1
vote
2
answers
92
views
How to choose the memory size to port a soft from 68HC11 8bit to RISC-V based MCU 32bits target [closed]
I have to build a new hardware with a new 32bit microcontroller. I have a working project on an 8bit microconttroller.
When compiling the C program for my new target what will be the needed size of ...
- 11
0
votes
2
answers
121
views
Microcontroller and Memory size allocation
Below are two custom made microcontrollers. The only difference between this is memory size.
My question:
Can someone tell me what is their start address and end address? Like, for the first one - ...
- 2,292
1
vote
0
answers
65
views
DDR4 Routing Consideration
I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2).
each BO has different impedance ...
- 533
-2
votes
3
answers
91
views
How can I flash a microcontroller from a GUI? (A driver software concept) [closed]
Assuming that I have three LED lights, and I have created a GUI that allows the end customers to choose which color each LED is going to display and then save it to the permanent memory of the ...
1
vote
1
answer
72
views
DDR3 logic levels - AC or DC?
In a DDR3 datasheet, I found different voltage levels (AC and DC.) I already know about DC logic levels but I don't know about AC logic levels.
What is the difference between the two?
Do the AC values ...
- 572
0
votes
1
answer
82
views
EEPROM memory erase bit vs word
If I have an EEPROM 1K X 16, can I erase bit by bit or just word by word (2 bytes/16 bits) in my matrix of registers ? In digital systems - TOCCI, the EEPROM is modeled by a matrix of registers, each ...
- 119
0
votes
0
answers
56
views
how to enable and store the data in EMMC memory chip
I'm working on a board which has an FPGA, USB controller, EMMC memory chip and a USB 3.0 connector. Now the data has to be transferred from the host PC through USB 3.0. From the USB controller the ...
0
votes
2
answers
191
views
What does the RZQ stands for?
While manually configuring a Memory Interface Generator in Vivado, I saw an option related to the output driver impedance. There were two options selectable, RZQ/6 ...
- 227