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Questions tagged [metastability]

Questions about the behaviour of FlipFlops when the normal input setup or hold requrements are not respected, usually when launch and capture clocks are not synchronous.

2
votes
3answers
57 views

Clock domain cross and metastablilty problem

I understand the problem of metastability and understand that we can't get a stable value in a bounded time so we need unbonded time but it is not practical, so we put another flip flop with no ...
2
votes
2answers
110 views

VHDL: Metastability check for hold time fails

I'm trying to model an SN74HC573 D-type latch in VHDL to get back into it. Here's what I got so far: ...
0
votes
2answers
69 views

Temperature and Voltage variation affects on Metastability

Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?
12
votes
6answers
2k views

Why do cascading D-Flip Flops prevent metastability?

I understand what metastability is but don't understand how linking together flip flops reduces this? If the output of the first flipflop is metastable, this gets used as input for the second one. ...
2
votes
2answers
107 views

Crossing independent domain clocks (slow to fast)

I have 2 time domain clocks (completely independent) and a bit stream (single bit) The first clocks is at 12.29 MHz . I want to asynchronously reclock it to a second time domain. Meta stability is ...
3
votes
1answer
74 views

Metastability Deserialization and clock crossing domain

I have a question on metastability and clock crossing domain. I need to deserialize a bitstream out of an ADC. TXCLK, TXOUT1, INCLK are the outputs of the ADC. So the idea was to register the DATA ...
0
votes
3answers
722 views

How would a ring oscillator with even number of inverters behave?

Intuitively, I understand that with an even number of stages, the output of the last would be the same logic level as the input of the first, so that the output eventually latches to a certain logic ...
1
vote
0answers
98 views

What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?

Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
0
votes
1answer
718 views

Violating the minimum clock pulse width of a D-type flip flop

Any D-type flip flop has a specification for a minimum clock pulse width. For example, the 74LVC374 has a typical time of 1.5ns for Vcc=3V. But what can happen to the flip flop if a shorter pulse is ...
1
vote
1answer
201 views

Metastability simulation

I am trying to observe the metastability by simulating (LTSpice) a chain of inverters and probe the signals in between. The oscillation never happens (I put more than 5 inverters to ensure enough ...
0
votes
1answer
3k views

Why non repeated poles at imaginary axis makes LTI system marginally stable?

I understand that stability for an LTI system is defined with respect to Bounded input bounded output condition. However I'm not clear on why non repeated poles on the imaginary axis makes the system ...
5
votes
3answers
406 views

After metastability, does the value eventually settle to the correct value?

I'm confused about metastability. I know that metastability is the condition wherein the output of a flip flop becomes unpredictable (either high or low) for some "duration of time"... Okay, from this ...
9
votes
2answers
3k views

How does 2-ff synchronizer ensure proper synchonization?

Using 2-ff synchronizers has been a standard for a signal to cross clock boundaries. And there are lots of paper/figures illustrating the mechanism, such as this one: It seems bclk can only sample ...
4
votes
2answers
520 views

Metastability error propagation with flip flop

I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain ...
0
votes
1answer
168 views

What will the output of filp-flop if its input is metastable?

I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt. Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
3
votes
1answer
475 views

Output of a D flipflop upon power up?

I guess the output state of a D-flipflop is unknown upon power up. But what are the chances that it is neither 0 nor 1 but an intermediate state such as VDD/2? The D-flipflop in this question has an ...
0
votes
1answer
71 views

Do any flip-flops use separate clock levels for “sample” and “propagate” events

Many kinds of sequential logic require that the output of one register be fed into the input of another register which is strobed by the same clock. In such logic, it's necessary to ensure that a ...
2
votes
1answer
196 views

Do Schmitt-trigger specs give requirements to avoid metastability?

Although Schmitt triggers are not usually regarded as latches with setup/hold constraints, a Schmitt trigger is functionally a sort of latch which is forced one way when the input is above a certain ...