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Questions tagged [microsemi-fpga]

Use this tag when your question specifically pertains to the Microsemi line of FPGAs and SoC-FPGAs.

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61 views

Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
6
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1answer
864 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...
0
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1answer
184 views

which interface to use TBI, GMII or MII? (FPGA)

I am working with the SoC FPGA Smartfusion2 M2S010-MKR-KIT. It is intended to exchange some data between the SoC and the PC. For that reason, I aim to use Ethernet. As far as I understood, in order ...
-1
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1answer
64 views

How does Flash*Freeze reduce power consumption in Microsemi FPGAs?

Microsemi FPGAs are marketed as being low power. They have this flash freeze mode that is supposed to achieve much lower power dissipation, down to micro watts. I am trying to understand how exactly ...
0
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0answers
65 views

Pin strength configuration

Please, help me understand the specsheet on page 2-22. The table says that 3.3V standard supports 12mA drive strength, but there is also a "software" defined strength. What is it? There is also a "...
0
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1answer
123 views

APB PENABLE stays only for one PCLK regardless of PREADY signal

I followed the AMBA 3 APB specification to design my APB slave. Reading from slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
0
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2answers
289 views

Simultaneous write and read to/from a FIFO

Could someone, please, clarify whether or not I could simultaneously read and write from the soft FIFO described in this document on p.157? It does say that I can use separate read and write clocks. I ...
3
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1answer
321 views

How to “Pull Down” LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
0
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2answers
249 views

Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
1
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1answer
150 views

Unused bits on a DDR3 chip

I have 2 DDR3 x16 chips (MT41K256M16xx) interfaced with an FPGA (M2S150TS-1FCS536). I plan on using point-to-point data & fly-by address/command topologies. I'm using ECC with a 16 bit bus, so 18 ...
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0answers
56 views

SoftConsole VS Keil for Smatfusion2 or any other development environment?

In order to program the ARM Cortex-M3 processor which is embedded in the Microsemi FPGA board SmartFusion2, I think there is two possibilities (correct me if wrong): Keil MDK (Microcontroller ...
2
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1answer
287 views

Microsemi IGLOO2 FPGA design resources [closed]

I want to start working on IGLOO2 FPGA, and I'm new to FPGAs. I searched throughout the internet for tutorials and training courses for Microsemi devices. It has a bad support and resources compared ...
0
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1answer
1k views

TCL command in Libero SOC [Microsemi] to generate the IP cores

Does anybody knows the TCL command to generate the IP cores in a design for the Libero Soc tool of Microsemi (v11.4 SP1)? So the IP core (e.g. a FIFO) is configured and in the design. However, the ...
4
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1answer
596 views

What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?

This question is along the lines of What files/directories are needed to recreate a Xilinx PlanAhead project? but for an Actel/Microsemi FPGA design. I'm looking for a fairly standard design with ...