Questions tagged [microsemi-fpga]

Use this tag when your question specifically pertains to the Microsemi line of FPGAs and SoC-FPGAs.

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Active Low LED and Active Low Switch behavior on FPGA counter-intuitive

I was following a tutorial to get started with Libero SoC with MicroSemi SmartFusion FPGA. I coded a small LED toggle module ...
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209 views

24-bit binary to 32-bit bcd

I'm trying to write a 24bin-32bcd BCD counter. Can anyone explain how to implement it ? Here is my code: http://tpcg.io/JOHf4IFj but it needs to be checked. I have some problems with "valid" ...
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Time to Digital Converter using FPGA with Coarse Counter in Verilog

I am currently using Verilog to program an FPGA and create a time-to-digital converter. What I am trying to do is measure the time interval when a square wave is high and then convert this to a binary ...
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38 views

How to Connect an External Signal to Digi-Key SmartFusion2 M2S010-MKR-KIT?

I am currently trying to configure my board to take an external square wave from a function generator, measure the time interval between rising and falling edges, then output the measurement on screen....
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SmartFusion 2 Pin Assignments using Libero

I am currently trying to find the schematic or pinout chart for a MicroSemi's SmartFusion 2. I have read all of their reference documents and release notes, but I can't find which pin is wired into ...
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108 views

Converting a 50MHz clock to 1Hz to blink an LED

My board uses a 50MHz clock which I am trying to convert to 1Hz so that I can blink an LED. The way my code works is it counts up to 25,000,000 and then the divided clock signal switches from 0 to 1. ...
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38 views

Actel ProASIC3 FPGA all IO pins are getting active high after programming

I am kind new to Microsemi FPGA environment. I am using ProASIC3 FPGA with Libero SoC 11.9 tool. I am simply assigning inputs to outputs but the real trouble is having 3.3 volts on input channels by ...
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24 views

Is Microsemi Libero supposed to have many arithmetic cores inside its catalogue?

Here is a screenshot of the Libero catalogue tab in my machine. I am using Libero 11.9. There are only 3 design blocks which frankly are trivial. There is no divider, no floating point maths blocks, ...
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128 views

Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
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883 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...
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340 views

which interface to use TBI, GMII or MII? (FPGA)

I am working with the SoC FPGA Smartfusion2 M2S010-MKR-KIT. It is intended to exchange some data between the SoC and the PC. For that reason, I aim to use Ethernet. As far as I understood, in order ...
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106 views

How does Flash*Freeze reduce power consumption in Microsemi FPGAs?

Microsemi FPGAs are marketed as being low power. They have this flash freeze mode that is supposed to achieve much lower power dissipation, down to micro watts. I am trying to understand how exactly ...
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Pin strength configuration

Please, help me understand the specsheet on page 2-22. The table says that 3.3V standard supports 12mA drive strength, but there is also a "software" defined strength. What is it? There is also a "...
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181 views

APB PENABLE stays only for one PCLK regardless of PREADY signal

I followed the AMBA 3 APB specification to design my APB slave. Reading from slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
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2answers
500 views

Simultaneous write and read to/from a FIFO

Could someone, please, clarify whether or not I could simultaneously read and write from the soft FIFO described in this document on p.157? It does say that I can use separate read and write clocks. I ...
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1answer
393 views

How to “Pull Down” LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
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2answers
372 views

Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
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1answer
207 views

Unused bits on a DDR3 chip

I have 2 DDR3 x16 chips (MT41K256M16xx) interfaced with an FPGA (M2S150TS-1FCS536). I plan on using point-to-point data & fly-by address/command topologies. I'm using ECC with a 16 bit bus, so 18 ...
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66 views

SoftConsole VS Keil for Smatfusion2 or any other development environment?

In order to program the ARM Cortex-M3 processor which is embedded in the Microsemi FPGA board SmartFusion2, I think there is two possibilities (correct me if wrong): Keil MDK (Microcontroller ...
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1answer
293 views

Microsemi IGLOO2 FPGA design resources [closed]

I want to start working on IGLOO2 FPGA, and I'm new to FPGAs. I searched throughout the internet for tutorials and training courses for Microsemi devices. It has a bad support and resources compared ...
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1answer
2k views

TCL command in Libero SOC [Microsemi] to generate the IP cores

Does anybody knows the TCL command to generate the IP cores in a design for the Libero Soc tool of Microsemi (v11.4 SP1)? So the IP core (e.g. a FIFO) is configured and in the design. However, the ...
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1answer
619 views

What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?

This question is along the lines of What files/directories are needed to recreate a Xilinx PlanAhead project? but for an Actel/Microsemi FPGA design. I'm looking for a fairly standard design with ...