Questions tagged [microsemi-fpga]

Use this tag when your question specifically pertains to the Microsemi line of FPGAs and SoC-FPGAs.

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Microsemi FPGA Post-Layout Simulation know-hows

I currently want to simulate a big design in the Microchip ProASIC3E FPGA which contains full usage of internal SRAM memory and numerous counters in logic cells. The design is clocked at 40MHz and has ...
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Minimum FPGA clock frequency

I currently work with two FPGAs, Microchip/Microsemi ProASIC3E and AMD/Xilinx Zynq-7020. In their datasheets, the recommended minimum operating frequency is 1.5 MHz for the A3PE ProASIC3E chip. The ...
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Microchip FPGA Internal Short Circuit

We are using the FPGA ProASIC3E A3PE1500-PQ208. The FPGA got internally short circuited during runtime. The FPGA IO Supply Voltage and FPGA ground are permanently short circuited and it is not ...
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Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Some of the labels used in back-annotated netlist descriptions generated by Microchip (Microsemi) Libero rely on forward slash naming conventions as shown below ...
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Error message vsim-3171 keeps popping up in Modelsim DE 2021.1 even though it was solved in Modelsim ME 10.2c

I have a test bench where I'm using a SystemVerilog bind construct. My test bench follows a similar organization to the one described at this link Every time I run it, error vsim-3171 shows up. I came ...
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When is it safe to ignore clock-domain crossing results from Microchip (Microsemi) Libero SoC's CDC report?

Inside my design, I'm only adding synchronizers to the control signals traveling between two different clock domains. The data buses are aligned with a pretty simple handshake scheme and don't have ...
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Libero does synthesis again before programming the device

I am using a ProASIC3E PQ208 FPGA and Libero tool to write the vhdl code and program the board on which the FPGA is soldered. When I try to open Libero again to program file, it starts the synthesis ...
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HLS like programming on Actel devices

I have been using Xilinx FPGA devices for a while and I use HLS extensively to create parts of my design. I have currently switched to Actel FPGA devices and specifically the ProASIC3 family, and ...
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Why program for MI-V bigger than 64 kB does not build properly?

I am woking with Microsemi Polarfire Splashkit evaluation board (Microchip's Polarfire MPF300T FPGA on board). My project has Mi-V RV32 Softcore processor (RISC-V ISA) and I am writing firmware for it....
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FPGA simulation with crystal oscillator what to do with XTL input?

I instantiated a crystal oscillator (and CCC) in a Microchip/Microsemi IGLOO2 FPGA design, and the oscillator's VHDL module has a XTL input pin. What is the proper preparation/wiring for simulation? ...
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Is it possible to write an "interconnect" in VHDL by hand?

An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...
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Is there a reason to have different files or entities with same name in FPGA project?

In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things: Is it a good practice to have multiple entities in same file? What if entity and ...
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Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10

An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate ...
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Program FPGA without JTAG?

I write embedded software that runs on a single board computer running Linux and talking to FPGAs. I do not do FPGA design, so I'm at the edge of my knowledge with this question: how do I program an ...
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Is there a "universal" JTAG controller peripheral?

JTAG can be used to read/write data from/to FPGAs. I want to know if there is any device with an interpreter that can be used with user written STAPL files. Basically the peripheral shall wiggle the ...
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How to transfer blocks of data into FPGA to aid in testing?

How can one transfer data from PC to FPGA and read back result for test purpose where the data must not get corrupted i.e resend if data integrity was lost or use some other error recovery mechanism. ...
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Ethernet Auto Negotiation Timeout

I am currently trying to get a basic Ethernet communication between a laptop and and FPGA Development board working correctly, however, I seem to be facing an issue where the auto-negotiation is ...
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Ethernet Data Transfer (ARM M3-Cortex to PC)

I am having some trouble trying to understand how I can use Ethernet to transmit some data to a computer. To be clear this would be a direct connection (an Ethernet cable will run from my development ...
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Smartfusion2 Programmer Error

I have recently start using the M2S150 Development kit from Microsemi and have run into an issue when attempting to program the board (via Libero 12.1). When running the "Run PROGRAM Action" ...
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Active Low LED and Active Low Switch behavior on FPGA counter-intuitive

I was following a tutorial to get started with Libero SoC with MicroSemi SmartFusion FPGA. I coded a small LED toggle module ...
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24-bit binary to 32-bit bcd

I'm trying to write a 24bin-32bcd BCD counter. Can anyone explain how to implement it ? Here is my code: http://tpcg.io/JOHf4IFj but it needs to be checked. I have some problems with "valid" ...
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How to Connect an External Signal to Digi-Key SmartFusion2 M2S010-MKR-KIT?

I am currently trying to configure my board to take an external square wave from a function generator, measure the time interval between rising and falling edges, then output the measurement on screen....
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SmartFusion 2 Pin Assignments using Libero

I am currently trying to find the schematic or pinout chart for a MicroSemi's SmartFusion 2. I have read all of their reference documents and release notes, but I can't find which pin is wired into ...
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Converting a 50MHz clock to 1Hz to blink an LED

My board uses a 50MHz clock which I am trying to convert to 1Hz so that I can blink an LED. The way my code works is it counts up to 25,000,000 and then the divided clock signal switches from 0 to 1. ...
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Is Microsemi Libero supposed to have many arithmetic cores inside its catalogue?

Here is a screenshot of the Libero catalogue tab in my machine. I am using Libero 11.9. There are only 3 design blocks which frankly are trivial. There is no divider, no floating point maths blocks, ...
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Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
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what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...
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which interface to use TBI, GMII or MII? (FPGA)

I am working with the SoC FPGA Smartfusion2 M2S010-MKR-KIT. It is intended to exchange some data between the SoC and the PC. For that reason, I aim to use Ethernet. As far as I understood, in order ...
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How does Flash*Freeze reduce power consumption in Microsemi FPGAs?

Microsemi FPGAs are marketed as being low power. They have this flash freeze mode that is supposed to achieve much lower power dissipation, down to micro watts. I am trying to understand how exactly ...
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Pin strength configuration

Please, help me understand the specsheet on page 2-22. The table says that 3.3V standard supports 12mA drive strength, but there is also a "software" defined strength. What is it? There is also a "...
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APB PENABLE stays only for one PCLK regardless of PREADY signal

I followed the AMBA 3 APB specification to design my APB slave. Reading from slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
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Simultaneous write and read to/from a FIFO

Could someone, please, clarify whether or not I could simultaneously read and write from the soft FIFO described in this document on p.157? It does say that I can use separate read and write clocks. I ...
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3 votes
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How to "Pull Down" LVDS input in FPGA

One of my hardware modules uses a state machine which is triggered when the input signal IN is HI (that's an LVDS pair on Microsemi proASIC FPGA). The problem arises when nothing is connected to the ...
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1 vote
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Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
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Unused bits on a DDR3 chip

I have 2 DDR3 x16 chips (MT41K256M16xx) interfaced with an FPGA (M2S150TS-1FCS536). I plan on using point-to-point data & fly-by address/command topologies. I'm using ECC with a 16 bit bus, so 18 ...
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SoftConsole VS Keil for Smatfusion2 or any other development environment?

In order to program the ARM Cortex-M3 processor which is embedded in the Microsemi FPGA board SmartFusion2, I think there is two possibilities (correct me if wrong): Keil MDK (Microcontroller ...
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Microsemi IGLOO2 FPGA design resources [closed]

I want to start working on IGLOO2 FPGA, and I'm new to FPGAs. I searched throughout the internet for tutorials and training courses for Microsemi devices. It has a bad support and resources compared ...
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TCL command in Libero SOC [Microsemi] to generate the IP cores

Does anybody knows the TCL command to generate the IP cores in a design for the Libero Soc tool of Microsemi (v11.4 SP1)? So the IP core (e.g. a FIFO) is configured and in the design. However, the ...
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4 votes
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What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?

This question is along the lines of What files/directories are needed to recreate a Xilinx PlanAhead project? but for an Actel/Microsemi FPGA design. I'm looking for a fairly standard design with ...
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