Questions tagged [modelsim]

ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.

Filter by
Sorted by
Tagged with
2
votes
0answers
53 views

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
0
votes
0answers
18 views

Testbench for RTL and GLS simulation

I want to do the GLS simulation after the RTL simulation. I was asked to add uut : entity work.eq3(structure) instead of the one specified below used for RTL <...
1
vote
0answers
39 views

Simulation of IP Core using ModelSim

I try to use IP core in Xilinx ISE 14.2. When the simulation done with ISim it works fine. Now I need to do the simualtion with ModelSim SE-64 10.7. I compile HDL Simualtion Libraries Fig.1. I run ...
1
vote
0answers
18 views

Post-synthesis simulation using Nangateopencelllibrary_pdkv1_3_v2010_12

I'm wondering if anyone has used the open-source Nangate library to do synthesis and post-synthesis simulation? I was trying to synthesis my processor and got the netlist verilog file from design ...
0
votes
0answers
34 views

ModelSim does not run until “$stop” command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
0
votes
1answer
97 views

Why is my 8-bit counter only counting until 127?

I recently coded an 8-bit counter in Libero and simulated it in ModelSim using Verilog. When I simulated my design, it only went up to 127. Shouldn't an 8-bit counter go up to 255? Here is my HDL Code:...
0
votes
1answer
85 views

Writing to a Register happens one or two clock cycles after asserting write enable?

I am using the code shown here Verilog: Writing to a Register Happens A Clock Cycle Late and that user posted a picture where output would change 2 cycles after asserting write enable. That post got ...
0
votes
0answers
38 views

error loading design

I am trying to simulate a testbench. I have compiled the testbench and the file it is testing and everything compiles without errors. When I try to simulate the testbench it says "error loading design"...
0
votes
0answers
139 views

How to use VHDL Entity in logisim evolution?

I'm new in Logisim and VHDL. I'm trying to use VHDL entity-component but the output always is "x". Then I read a document ( this link ) that said Logisim requires ModelSim to use this feature. So I ...
2
votes
1answer
93 views

Verilog output is hiZ in testbench

I'm new to verilog and modelsim. I'm having trouble with my AND and OR modules in this particular testbench. The output is always Z(hi impedance) ...
0
votes
0answers
16 views

What is the easiest way to simulate and experiment with FPGA using simulated external DDR3?

For a computer architecture school project I have to implement an algorithm in verilog, such design have to input and output a VERY large ammount of data that wouldn't fit in on-chip memory, hence I ...
0
votes
1answer
55 views

Help on writing test bench for up counter in verilog

preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.) However, I am very new at Verilog and also have never used ...
0
votes
0answers
52 views

Why am I getting weird behavior when building 4-bit down counter?

I'm attempting to build a 4-bit modulo-10 down-counter (i.e 9,8,7...,1,0,9,8,7...0). Here is my code so far: ...
0
votes
0answers
53 views

Range error during Modelsim simulation of a VHDL user-defined resolved data type

When running a simulation of a testbench involving a user-defined resolved data-type, I get an error report of the form: "** Fatal: (vsim-3734) Index value 1 is out of range 0 to 1" , followed by ...
0
votes
0answers
9 views

How to print line coverage for a particular line in a Verilog code, in Modelsim?

The following line gives the line coverage for an instance of a module in Modelsim. ...
1
vote
2answers
64 views

Sequential logic in VHDL

Does anyone know of a way I can use sequential statements in VHDL without using the traditional if, case, when statements? I am building an 8 bit word splitter that will then pass a 4 bit nibble to ...
0
votes
1answer
83 views

vhdl output pulse

I have another question regarding some VHDL, I am trying to create a pulse of 5ms output for (in my code a_full) however I am struggling to find any information on how to generate this, basically I ...
0
votes
2answers
62 views

ModelSim wave window showing zero time transitions

I'm new to verilog and so ModelSim. There's a problem or actually may not be a problem that I have noticed. It seems to me that ModelSim wave window imposes by default a transition at time zero on ...
0
votes
1answer
65 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
0
votes
1answer
87 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
0
votes
1answer
491 views

My work directory in ModelSim is always empty. How can I resolve this problem?

I'm new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was ...
1
vote
1answer
271 views

Verilog Missing connection for port

I was creating a circuit using two dual input AND gates into a dual input NOR using three modules and module instantiation. The first module is for the AND inputs and the second module is for the ...
0
votes
1answer
709 views

How to come out of the transcript window of Modelsim which is stuck?

I am running a Modelsim script and the transcript window gets stuck. I have tried the following to go to the next line in the transcript window without any success. Simulate > End simulation Simulate ...
0
votes
0answers
92 views

Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
1
vote
1answer
228 views

Why is this VHDL pseudo random number generator not working as expected?

I'll start off by saying I have about 2 days experience in VHDL so there's a strong chance my code is horrible. I would appreciate any tips on better VHDL practice. I am busy trying to simulate a ...
0
votes
1answer
1k views

Removing modelsim error

I am trying to simulate a simple inverter in verilog using modelsim 10.7 version. While compiling the code I am getting the -novopt error (error code 12110). As per user manual page 80; the -novopt ...
0
votes
1answer
68 views

Set alternative editor for ModelSim

I want to set an alternative editor in ModelSim. I tried How to configure my favorite editor in ModelSim? and after I set the altEditor I get "unknown command external_editor". Unfortunately my ...
0
votes
1answer
79 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
-2
votes
1answer
254 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
7
votes
1answer
210 views

VHDL Procedure - Same variable for input/output parameter

I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this: ...
0
votes
0answers
61 views

VHDL - Unable to correctly implement complex scheduling of data lines to Inputs of multiplexers

In my design, I have two configurable parameters ...
1
vote
1answer
164 views

Why am I getting a red wire for my out?

I am attempting to create an output that goes on for a certain amount of time an then goes low for a certain amount of time and my out simply won't simulate. Attached is my code, test bench, and ...
0
votes
1answer
118 views

How add delays to everything in Verilog or SystemVerilog outside of .v or .sv file

All delay documentation I've seen is pretty low level -- add a #5 or whatever and that particular assignment gets a delay. Use this in a module and instantiate, etc, etc. There are variations on ...
0
votes
1answer
1k views

error loading design - modelsim

I'm new to modelsim and Verilog and I have got an error in it: # Region: /seqdectorTB # Error loading design 1.3.v: ...
-1
votes
1answer
2k views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
0
votes
1answer
403 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
0
votes
2answers
378 views

Passing VHDL string generic with spaces via Modelsim command line

Given the following code: entity foo is generic ( VAL : string ); end entity foo; architecture behav of foo is begin end architecture behav; How can I ...
0
votes
1answer
234 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
0
votes
1answer
88 views

Problem in blocking and non-blocking - verilog

I have this code and I am having a problem in the product output, any ideas? I've tried a lot and it doesn't work.
0
votes
1answer
156 views

Modelsim: resume simulation future

I have long running simulation in Modelsim for VHDL/Verilog designs. I want to know are there any way to save current simulation progress and resume it somehow in later time?
0
votes
1answer
1k views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
2
votes
0answers
132 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
-1
votes
1answer
59 views

ModelSIM not generating outputs for any variables

I have been working on this issue for days and have not been able to figure it out. I was hoping one of you could help me solve this issue. So, when I run my SV code in Quartus and compile it, I don'...
0
votes
2answers
689 views

Altera-Modelsim simulation wont start when I add a module instance in my main testbench module

Edit: it is something with the simulate_camera_output module that Modelsim doesn't like. Tried with a simple test module and it works fine. Looking for a way to ...
1
vote
1answer
147 views

1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSim

I have made a 1 byte instruction register in VHDL. Instead of having a 1 byte output, I have created an upper nibble output and a lower nibble output. The lower nibble output is special because it ...
3
votes
2answers
410 views

how slow are modelsim free licences?

I know in free licenses of modelsim / questa simulations run slower than the full version. But how slow? will it be 2x 3x 10x faster in the paid version? what about actel/microsemi free version ?
0
votes
1answer
310 views

Negative Edge Trigger and Asynchronous Clear not working in ModelSim

I have created a 4 bit counter with the following inputs and outputs clockN: active low clock clearN: active low clear cP: When high, the counter counts. When low, the counter stays the same. eP: ...
0
votes
1answer
177 views

Is there a way to suppress the output when compiling multiple vhd files except for errors?

I have a compilation script I run before simulating on QuestaSim 10.7: ...
0
votes
1answer
1k views

Modelsim simulation doesn't work Pleas help

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...
0
votes
1answer
785 views

This model of a D-Flip flop with Enable not working as expected

This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera: ...