Questions tagged [modelsim]

ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.

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60 views

Sequential logic in VHDL

Does anyone know of a way I can use sequential statements in VHDL without using the traditional if, case, when statements? I am building an 8 bit word splitter that will then pass a 4 bit nibble to ...
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1answer
67 views

vhdl output pulse

I have another question regarding some VHDL, I am trying to create a pulse of 5ms output for (in my code a_full) however I am struggling to find any information on how to generate this, basically I ...
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2answers
36 views

ModelSim wave window showing zero time transitions

I'm new to verilog and so ModelSim. There's a problem or actually may not be a problem that I have noticed. It seems to me that ModelSim wave window imposes by default a transition at time zero on ...
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1answer
45 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
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1answer
40 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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1answer
108 views

My work directory in ModelSim is always empty. How can I resolve this problem?

I'm new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was ...
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0answers
16 views

How to use the dumplog64 to open the contents of the WLF file as per specified time units(us, ms,ns)

I have used the command dumplog64 to open the contents of the specified WLF file in a readable format in Notepad. I have found the readable format of wlf file in the below format in Notepad. For ...
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1answer
112 views

Verilog Missing connection for port

I was creating a circuit using two dual input AND gates into a dual input NOR using three modules and module instantiation. The first module is for the AND inputs and the second module is for the ...
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1answer
192 views

How to come out of the transcript window of Modelsim which is stuck?

I am running a Modelsim script and the transcript window gets stuck. I have tried the following to go to the next line in the transcript window without any success. Simulate > End simulation Simulate ...
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0answers
16 views

How to generate .lst output files by running Modelsim without GUI

The question I am trying to generate an output list file using a tcl file (provided at the end of this question). There is a line for .list file generation which is as follows: ...
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0answers
45 views

Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
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1answer
192 views

Why is this VHDL pseudo random number generator not working as expected?

I'll start off by saying I have about 2 days experience in VHDL so there's a strong chance my code is horrible. I would appreciate any tips on better VHDL practice. I am busy trying to simulate a ...
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1answer
285 views

Removing modelsim error

I am trying to simulate a simple inverter in verilog using modelsim 10.7 version. While compiling the code I am getting the -novopt error (error code 12110). As per user manual page 80; the -novopt ...
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1answer
51 views

Set alternative editor for ModelSim

I want to set an alternative editor in ModelSim. I tried How to configure my favorite editor in ModelSim? and after I set the altEditor I get "unknown command external_editor". Unfortunately my ...
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1answer
69 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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1answer
116 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
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1answer
150 views

VHDL Procedure - Same variable for input/output parameter

I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this: ...
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0answers
61 views

VHDL - Unable to correctly implement complex scheduling of data lines to Inputs of multiplexers

In my design, I have two configurable parameters ...
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1answer
113 views

Why am I getting a red wire for my out?

I am attempting to create an output that goes on for a certain amount of time an then goes low for a certain amount of time and my out simply won't simulate. Attached is my code, test bench, and ...
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1answer
99 views

How add delays to everything in Verilog or SystemVerilog outside of .v or .sv file

All delay documentation I've seen is pretty low level -- add a #5 or whatever and that particular assignment gets a delay. Use this in a module and instantiate, etc, etc. There are variations on ...
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1answer
676 views

error loading design - modelsim

I'm new to modelsim and Verilog and I have got an error in it: # Region: /seqdectorTB # Error loading design 1.3.v: ...
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1answer
1k views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
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1answer
186 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
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0answers
95 views

ALU not working in Verilog MIPS Single cycle implementation

I have written the following code in Verilog which for the time being caters to only a subset of R-type, load word and store word instructions in the single cycle implementation based on the diagram ...
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2answers
239 views

Passing VHDL string generic with spaces via Modelsim command line

Given the following code: entity foo is generic ( VAL : string ); end entity foo; architecture behav of foo is begin end architecture behav; How can I ...
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1answer
188 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
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1answer
87 views

Problem in blocking and non-blocking - verilog

I have this code and I am having a problem in the product output, any ideas? I've tried a lot and it doesn't work.
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1answer
106 views

Modelsim: resume simulation future

I have long running simulation in Modelsim for VHDL/Verilog designs. I want to know are there any way to save current simulation progress and resume it somehow in later time?
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1answer
944 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
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0answers
124 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
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1answer
50 views

ModelSIM not generating outputs for any variables

I have been working on this issue for days and have not been able to figure it out. I was hoping one of you could help me solve this issue. So, when I run my SV code in Quartus and compile it, I don'...
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2answers
498 views

Altera-Modelsim simulation wont start when I add a module instance in my main testbench module

Edit: it is something with the simulate_camera_output module that Modelsim doesn't like. Tried with a simple test module and it works fine. Looking for a way to ...
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1answer
95 views

1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSim

I have made a 1 byte instruction register in VHDL. Instead of having a 1 byte output, I have created an upper nibble output and a lower nibble output. The lower nibble output is special because it ...
3
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2answers
334 views

how slow are modelsim free licences?

I know in free licenses of modelsim / questa simulations run slower than the full version. But how slow? will it be 2x 3x 10x faster in the paid version? what about actel/microsemi free version ?
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1answer
220 views

Negative Edge Trigger and Asynchronous Clear not working in ModelSim

I have created a 4 bit counter with the following inputs and outputs clockN: active low clock clearN: active low clear cP: When high, the counter counts. When low, the counter stays the same. eP: ...
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1answer
132 views

Is there a way to suppress the output when compiling multiple vhd files except for errors?

I have a compilation script I run before simulating on QuestaSim 10.7: ...
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1answer
823 views

Modelsim simulation doesn't work Pleas help

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...
0
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1answer
585 views

This model of a D-Flip flop with Enable not working as expected

This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera: ...
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2answers
919 views

Opening and reading pixel values from bitmap images in Modelsim

How do I open a bitmap image, read the pixel data (24 bits) and store it in a memory that I created in a Verilog module in ModelSim? How do I open the below image in Modelsim? Is it possible in the ...
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1answer
6k views

Work library is empty after compiling Verilog source file in Modelsim [closed]

How I can solve this problem: my Work library is always empty after compiling a selected file in Modelsim?
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1answer
1k views

Aggregate of 2 vectors in VHDL

I am checking what I can and cannot do in aggregating and concatenating in VHDL. while I can combine two vectors by concatenating them, I keep getting error if I use aggregate. I saw one answer here ...
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2answers
115 views

What is the equivalent of compile of modelsim in quartus prime?

In ModelSim, I can click compile and ModelSim will compile it quickly, around 1 or 2 seconds. But in Quartus Prime, I need to run Analysis & Elaboration or Analysis & Synthesis which runs ...
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1answer
1k views

How do I tell Modelsim to not create a wlf file when I carry out simulation?

The wlf file contains the wave dump data. For some reason I get this message on my computer: ...
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0answers
330 views

How to specify library to low level Verilog component in VHDL testbench

I have written a VHDL testbench to test a Verilog design. A lower level Verilog module instantiates some FIFOs through Altera Megawizard. The read FIFO code is below: ...
3
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2answers
414 views

Design a T flip flop in VHDL using Modelsim, signal values not changing as expected

I was trying to design a TFF in VHDL. I wrote the code below ...
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0answers
387 views

How to easily generate a signal wave in Modelsim having the amplitude-time data already known

I have to generate waveform in modelsim, with data that comes from a NI (national instrument) oscilloscope. The data is amplitude and time, it describes a waveform from a sensor in a machine. The ...
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1answer
1k views

Quartus, Modelsim, VHDL - Viewing Internal Signals

This question is rather specific which makes it rather hard to answer. I'm using Quartus Prime software from Altera to do an FPGA design in VHDL. Quartus exports to Modelsim for the simulation. I'm ...
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1answer
1k views

Why does modelsim show St0, St1 & Pu0 for value of logic signal?

The design block in question is generated by Quartus, it is the shift register megafunction. When I simulate the design I find that some of the signals do not show 0 or 1, rather they show different ...
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0answers
844 views

VHDL Multidimensional arrays with different internal size

I'm wondering if it is possible or not to create bi-dimensional arrays having different inner sizes. For example I can create ...
3
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2answers
1k views

VHDL process requires multiple clock cycles

I wrote a simple counter in VHDL for a program counter. Everything is done in a process, but what I dont understand is that in the simulation, the addition of the program counter, is only done at the ...