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Questions tagged [modelsim]

ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.

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What is difference between QuestaSim "batch mode" and "command line" mode

Running vsim -h in the terminal reveals these two switches: ...
quantum231's user avatar
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QuestaSim shows internal signals of VHDL module but not SystemVerilog module

So for the first time, I created a SystemVerilog module and testbench in QuestaSim today. I created a project inside QuestaSim and then created a counter and a testbench for the counter. When I ...
quantum231's user avatar
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Getting HiZ for my output for a 5 to 1 mux

I'm having trouble with Verilog code for a 5 to 1 MUX. ...
Michael's user avatar
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1 answer
61 views

Post Synthesis Simulation in QuestaSim

I am attempting to perform post-synthesis simulation of a Verilog system designed in Vivado on QuestaSim. I am using QuestaSim 2021.2_1 and Vivado 2020.2. Here are the steps I have followed: I ...
Adam01's user avatar
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2 answers
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Verilog Double Counter Testbench Issues

I've been practicing writing some more advanced testbenches for my Verilog circuits. I thought I'd work with something simple: a double counter setup, where c0 is 3-bits long and c1 is 16-bits long. ...
aofarmakis's user avatar
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2 answers
139 views

How can I run Verilog code with data at a specific time in the past?

My simulation takes hours until it's stopped from my SystemVerilog code using $stop;. When it stops, to have proper information, I need to run a Verilog task/...
None's user avatar
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1 answer
73 views

How to stop ModelSim at a condition based on signals?

From the window, I'd like to give a condition in the console when to stop the simulation. I've tried: when {/tb/DUT/sequence==256806} {stop} run -all but it doesn'...
None's user avatar
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1 answer
429 views

Questasim Unable to find VHDL package not compiled into work

I'm currently trying to simulate a VHDL module with a SV testbench. The VHDL module contains several packages that are compiled into various libraries so in order to avoid compile errors within the ...
EpicFoodCartDestroyer's user avatar
1 vote
1 answer
60 views

My 4x4 parallel multiplier outputs are all x, just like the inputs

I'm new to Verilog and I am using ModelSim to compile and simulate. Here is my code for code for PM: ...
JarvisLYu1's user avatar
1 vote
1 answer
184 views

Using behavioural modelling, how do I design a positive edge triggered T flip-flop with asynchronous preset and clear?

I am having trouble doing the above. I have written a little bit of code along with a testbench, and it requires some changes. I also need to add the conditions for preset. How do I do that? ...
Gun_Gani's user avatar
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1 answer
169 views

Why am I getting a red wire for my output?

This is my code, my testbench, my simulation. ...
Nistor Carina's user avatar
-3 votes
1 answer
83 views

** Error: (vlog-13069) D:/CCSIT/DMSD/traffic_light_controller.v(2): near "traffic_light_controller": syntax error, unexpected IDENTIFIER [duplicate]

There is some problem with my code, but I can't find it. ...
hamad alsowaigh's user avatar
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1 answer
742 views

Modelsim does not show sim window

I'm new to ModelSim software and also VHDL codes. I want to simulate my test bench code via ...
Babak.Abad's user avatar
1 vote
1 answer
989 views

Multiple wire type objects declaration Verilog

I get an error everytime I try to use the same line to declare more than one wire type, is this because they are of different size (but I get the error even when they're of the same size, declaring ...
SM32's user avatar
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1 answer
236 views

FPGA I2C master not working

I have written an I2C master for the DE10-Nano FPGA which is meant to communicate with the SSD1306 OLED display driver. The issue I'm having is that it simply is not working when I actually test it on ...
IanRider's user avatar
2 votes
1 answer
653 views

How to set QuestaSim/ModelSim to print time value in arbitrary unit?

Here is the code: ...
gyuunyuu's user avatar
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1 answer
202 views

Modelsim merge libraries into same namespace

I am trying to figure out the best way to simulate an FPGA project in modelsim that contains multiple Xilinx Vivado IP. I have gone through the process of "Generating Output Products" for ...
Sittin Hawk's user avatar
1 vote
0 answers
190 views

ModelSim can not simulate my VHDL code

I am learning to program FPGAs and my code is compiled in Quartus prime but my .do file does not simulate in ModelSim. Any help is appreciated. ...
koushiksk's user avatar
1 vote
1 answer
382 views

SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
Karl.52's user avatar
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1 vote
1 answer
88 views

Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Some of the labels used in back-annotated netlist descriptions generated by Microchip (Microsemi) Libero rely on forward slash naming conventions as shown below ...
nanoeng's user avatar
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1 answer
419 views

Experiencing issues with VHDL Code ModelSim: Wave Generation

I'm working on this project where I'm basically supposed to generate square wave (and other types of wave) using VHDL. The time period can be adjusted to either increase or decrease its frequency, and ...
Thanos's user avatar
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1 answer
2k views

Modelsim: Debugging "NUMERIC_STD.TO_UNSIGNED: Vector truncated"

I might be able to post some code if needed, it's hard though cause the code is on a different machine. But I'm looking more a general approach to debugging this warning "NUMERIC_STD.TO_UNSIGNED: ...
Dylan's user avatar
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1 vote
1 answer
264 views

Signals acting weirdly in VHDL

I've always been told that a signal updates its values after a wait statement, or after a rising edge if we have for example if rising_edge(clk) then but in this testbench, after the first wait ...
B.Adlane's user avatar
-1 votes
1 answer
359 views

Error message vsim-3171 keeps popping up in Modelsim DE 2021.1 even though it was solved in Modelsim ME 10.2c

I have a test bench where I'm using a SystemVerilog bind construct. My test bench follows a similar organization to the one described at this link Every time I run it, error vsim-3171 shows up. I came ...
nanoeng's user avatar
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1 answer
1k views

How to randomize the seed-number in Modelsim?

In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number. I was ...
Taher Anaya's user avatar
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0 answers
335 views

I have prepared a file in ModelSim and saved it in a library named "work" and for graph I am not able to find my project under my saved library

I have written the code and compilation was successful but when I go for simulation I am not able to find my project under the saved library and it is empty. I have tried to change the directory but ...
Skysam's user avatar
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1 vote
0 answers
85 views

Initializing feedback signal in ModelSim simulation

I'm trying to simulate a MOUSETRAP asynchronous pipeline for FPGA. For the control stage, I need to implement the following circuit: DELAY is a delay element which I have correctly implemented using ...
Nacib Neme's user avatar
0 votes
1 answer
522 views

For QuestaSim, what's the difference between vsim.exe and vsimk.exe? [closed]

For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe? for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, ...
pico's user avatar
  • 183
2 votes
1 answer
582 views

Why is my counter not working? (Verilog)

I'm trying to create a counter that will display how many 1's are in the inputs. This is a little piece of code in the program: ...
tadm123's user avatar
  • 153
1 vote
1 answer
1k views

I'm trying to build a 16-bit adder in Verilog but my output and carryout always have a value of X

...
RiceBoy25's user avatar
1 vote
1 answer
1k views

How to manage multiple testcases in a VHDL testbench

I'm trying to implement a testbench for a relatively complex module and I need multiple test cases to cover all the functionality. I'd like to find an elegant way to perform multiple testcases without ...
Ben's user avatar
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2 answers
168 views

Unexpected change when reading input signals in a VHDL Finite State Machine

I implemented a FSM in vhdl using two processes; A sync process for state transition ...
Ahmed's user avatar
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1 vote
1 answer
688 views

Radix-4 Booth's Multiplier verilog code error

I wrote the code for radix 4 booth's multiplier. But, I am getting 2 errors. I am not able to solve it. Could you please help? The errors are: Error: C:/modelsim_dlx64_2021.1/examples/assignment/...
satoru's user avatar
  • 13
2 votes
1 answer
744 views

Where did I code my multiplier wrong?

I've wrote a verilog code for Multiplier (8bit). I'm not getting the right result. Kindly tell me where i went wrong. ...
Kuchi Yashwanth's user avatar
1 vote
1 answer
140 views

Coarse counter giving incorrect pulse length measurements at high frequencies

I am using a simple counter to measure pulse length. I have copied the code below, but the counter increments by 1 at each positive edge of the clock. Once the counter is done incrementing for that ...
PrematureCorn's user avatar
0 votes
1 answer
3k views

How to view the internal signals of module in ModelSim using the testbench?

I have looked over this tutorial (Tutorial - Using Modelsim for Simulation, for Beginners. ) how to add waves and write test benches for VHDL module I looked over some answers as well like this one to ...
Yaakov's user avatar
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0 votes
1 answer
94 views

Unexpected behaviour of data memory in modelsim testbench

I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
Lara's user avatar
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1 vote
1 answer
74 views

How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?

I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output: ...
Jake Nixon's user avatar
0 votes
1 answer
511 views

Does Quartus support UVM in files with .sv extension?

I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make ...
esencia's user avatar
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0 votes
2 answers
641 views

Errors in VHDL code

The VHDL code was written by me for a 4-bit PIPO DFF register. I have been encountering some errors when i did so. Kindly check the code and errors below. ...
Kuchi Yashwanth's user avatar
1 vote
1 answer
800 views

How do i read the RGB values of an image in Verilog from a hex file generated in Matlab for processing?

I have used Matlab to generate hex file for an image (1200 * 900 resolution). The hex file is like There are such 3240000 rows. How do i read this in verilog to performing some processing (filtering ...
yk_learner's user avatar
-1 votes
1 answer
6k views

Verilog code for construction of 4x16 decoder using 3x8 decoder [closed]

This is my 3x8 verilog module: ...
SUSMITHA M 's user avatar
1 vote
0 answers
178 views

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
HypeInst's user avatar
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1 vote
0 answers
393 views

Simulation of IP Core using ModelSim

I try to use IP core in Xilinx ISE 14.2. When the simulation done with ISim it works fine. Now I need to do the simualtion with ModelSim SE-64 10.7. I compile HDL Simualtion Libraries Fig.1. I run ...
Yacine Bouali's user avatar
0 votes
0 answers
546 views

ModelSim does not run until "$stop" command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
yer's user avatar
  • 67
0 votes
1 answer
741 views

Why is my 8-bit counter only counting until 127?

I recently coded an 8-bit counter in Libero and simulated it in ModelSim using Verilog. When I simulated my design, it only went up to 127. Shouldn't an 8-bit counter go up to 255? Here is my HDL Code:...
yer's user avatar
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0 votes
1 answer
1k views

Writing to a Register happens one or two clock cycles after asserting write enable?

I am using the code shown here Verilog: Writing to a Register Happens A Clock Cycle Late and that user posted a picture where output would change 2 cycles after asserting write enable. That post got ...
simedro's user avatar
1 vote
0 answers
4k views

How to use VHDL Entity in logisim evolution?

I'm new in Logisim and VHDL. I'm trying to use VHDL entity-component but the output always is "x". Then I read a document ( this link ) that said Logisim requires ModelSim to use this feature. So I ...
Wachira's user avatar
  • 111
3 votes
1 answer
2k views

Verilog output is hiZ in testbench

I'm new to verilog and modelsim. I'm having trouble with my AND and OR modules in this particular testbench. The output is always Z(hi impedance) ...
Amai Shopai's user avatar
0 votes
1 answer
715 views

Help on writing test bench for up counter in verilog

preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.) However, I am very new at Verilog and also have never used ...
muyustan's user avatar
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