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Questions tagged [modelsim]

ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.

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1answer
58 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
4
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0answers
66 views

VHDL Procedure - Same variable for input/output parameter

I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this: ...
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0answers
52 views

VHDL - Unable to correctly implement complex scheduling of data lines to Inputs of multiplexers

In my design, I have two configurable parameters ...
1
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1answer
98 views

Why am I getting a red wire for my out?

I am attempting to create an output that goes on for a certain amount of time an then goes low for a certain amount of time and my out simply won't simulate. Attached is my code, test bench, and ...
0
votes
1answer
40 views

How add delays to everything in Verilog or SystemVerilog outside of .v or .sv file

All delay documentation I've seen is pretty low level -- add a #5 or whatever and that particular assignment gets a delay. Use this in a module and instantiate, etc, etc. There are variations on ...
0
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1answer
135 views

error loading design - modelsim

I'm new to modelsim and Verilog and I have got an error in it: # Region: /seqdectorTB # Error loading design 1.3.v: ...
-1
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1answer
204 views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
0
votes
1answer
47 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
0
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0answers
70 views

ALU not working in Verilog MIPS Single cycle implementation

I have written the following code in Verilog which for the time being caters to only a subset of R-type, load word and store word instructions in the single cycle implementation based on the diagram ...
0
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2answers
101 views

Passing VHDL string generic with spaces via Modelsim command line

Given the following code: entity foo is generic ( VAL : string ); end entity foo; architecture behav of foo is begin end architecture behav; How can I ...
0
votes
1answer
97 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
0
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1answer
82 views

Problem in blocking and non-blocking - verilog

I have this code and I am having a problem in the product output, any ideas? I've tried a lot and it doesn't work.
0
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1answer
72 views

Modelsim: resume simulation future

I have long running simulation in Modelsim for VHDL/Verilog designs. I want to know are there any way to save current simulation progress and resume it somehow in later time?
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1answer
431 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
0
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0answers
88 views

VHDL-2008 generic packages for post-fit simulation in QuestaSim

I created a testbench for a VHDL design including integrated circuit models to check interface timing requirements. Within each model, I instantiate a generic package (genpkg) to print detected errors ...
2
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0answers
109 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
-1
votes
1answer
39 views

ModelSIM not generating outputs for any variables

I have been working on this issue for days and have not been able to figure it out. I was hoping one of you could help me solve this issue. So, when I run my SV code in Quartus and compile it, I don'...
0
votes
2answers
237 views

Altera-Modelsim simulation wont start when I add a module instance in my main testbench module

Edit: it is something with the simulate_camera_output module that Modelsim doesn't like. Tried with a simple test module and it works fine. Looking for a way to ...
1
vote
1answer
61 views

1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSim

I have made a 1 byte instruction register in VHDL. Instead of having a 1 byte output, I have created an upper nibble output and a lower nibble output. The lower nibble output is special because it ...
2
votes
2answers
192 views

how slow are modelsim free licences?

I know in free licenses of modelsim / questa simulations run slower than the full version. But how slow? will it be 2x 3x 10x faster in the paid version? what about actel/microsemi free version ?
0
votes
1answer
111 views

Negative Edge Trigger and Asynchronous Clear not working in ModelSim

I have created a 4 bit counter with the following inputs and outputs clockN: active low clock clearN: active low clear cP: When high, the counter counts. When low, the counter stays the same. eP: ...
0
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1answer
70 views

Is there a way to suppress the output when compiling multiple vhd files except for errors?

I have a compilation script I run before simulating on QuestaSim 10.7: ...
0
votes
1answer
458 views

Modelsim simulation doesn't work Pleas help

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...
0
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0answers
107 views

Limitations of VCD Files in modelsim

I use vcd files command in ModelSim to record vcd files for different steps of simualtion something like this: ...
0
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1answer
305 views

This model of a D-Flip flop with Enable not working as expected

This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera: ...
1
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2answers
607 views

Opening and reading pixel values from bitmap images in Modelsim

How do I open a bitmap image, read the pixel data (24 bits) and store it in a memory that I created in a Verilog module in ModelSim? How do I open the below image in Modelsim? Is it possible in the ...
0
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0answers
117 views

Multiple VHDL testbench for Single entity

I have VHDL design of Clock generator entity which require 8 input parameters and as per parameters generates single clock output. I have tested using single VHDL testbench and simulated in Modelsim. ...
1
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1answer
4k views

Work library is empty after compiling Verilog source file in Modelsim [closed]

How I can solve this problem: my Work library is always empty after compiling a selected file in Modelsim?
2
votes
1answer
719 views

Aggregate of 2 vectors in VHDL

I am checking what I can and cannot do in aggregating and concatenating in VHDL. while I can combine two vectors by concatenating them, I keep getting error if I use aggregate. I saw one answer here ...
1
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2answers
90 views

What is the equivalent of compile of modelsim in quartus prime?

In ModelSim, I can click compile and ModelSim will compile it quickly, around 1 or 2 seconds. But in Quartus Prime, I need to run Analysis & Elaboration or Analysis & Synthesis which runs ...
0
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1answer
725 views

How do I tell Modelsim to not create a wlf file when I carry out simulation?

The wlf file contains the wave dump data. For some reason I get this message on my computer: ...
0
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0answers
235 views

How to specify library to low level Verilog component in VHDL testbench

I have written a VHDL testbench to test a Verilog design. A lower level Verilog module instantiates some FIFOs through Altera Megawizard. The read FIFO code is below: ...
3
votes
2answers
265 views

Design a T flip flop in VHDL using Modelsim, signal values not changing as expected

I was trying to design a TFF in VHDL. I wrote the code below ...
0
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0answers
319 views

How to easily generate a signal wave in Modelsim having the amplitude-time data already known

I have to generate waveform in modelsim, with data that comes from a NI (national instrument) oscilloscope. The data is amplitude and time, it describes a waveform from a sensor in a machine. The ...
0
votes
1answer
620 views

Quartus, Modelsim, VHDL - Viewing Internal Signals

This question is rather specific which makes it rather hard to answer. I'm using Quartus Prime software from Altera to do an FPGA design in VHDL. Quartus exports to Modelsim for the simulation. I'm ...
1
vote
1answer
647 views

Why does modelsim show St0, St1 & Pu0 for value of logic signal?

The design block in question is generated by Quartus, it is the shift register megafunction. When I simulate the design I find that some of the signals do not show 0 or 1, rather they show different ...
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0answers
669 views

VHDL Multidimensional arrays with different internal size

I'm wondering if it is possible or not to create bi-dimensional arrays having different inner sizes. For example I can create ...
3
votes
2answers
860 views

VHDL process requires multiple clock cycles

I wrote a simple counter in VHDL for a program counter. Everything is done in a process, but what I dont understand is that in the simulation, the addition of the program counter, is only done at the ...
0
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0answers
548 views

Modelsim: Unresolved defparam reference to somewhere

In Quartus ii schematic diagram, i've generated an lpm_ff. Then i've converted the design to a .v file. when i want to use this ...
0
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1answer
111 views

SystemVerilog in ModelSim ignores negedge/posedge when monitoring

Using SystemVerilog and ModelSim, I want to monitor the values of some signals in my design when the clock is on its negative edge. Strangely, the code responses on both edges (positive and negative). ...
1
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1answer
2k views

Export Modelsim waveforms as image for printing

I want to export the Modelsim waveforms of my simulated design in a form where they can look decent when printed. To be more specific, without the black background, in a vector format preferably. Not ...
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1answer
60 views

How to do simulation on modelsim 10.4 se?

I want to make a test bench for my mux21 but can't find a way, and online there is nothing clear, here is my code. ...
1
vote
1answer
93 views

Verilog Synchronous bit alternator (Quartus/Modelsim) - Altera FPGA

I am trying to make a simple bit alternator for the purpose of learning how to use verilog for FGPA design and how to simulate in modelsim. Here is my code: ...
1
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1answer
2k views

Suppress Specific IP Warnings in Modelsim

A Vivado IP is generating an inordinate amount of Modelsim warnings which are making it difficult to assess the simulation for warnings I actually care about. I see from the Modelsim command ...
0
votes
1answer
777 views

Is it possible to show fixed point numbers as base 10 in modelsim wave?

If a person is creating a system using fixed point numbers a decimal point is implied. In this case, if one is going to use the wave window to see the result, it will be beneficial to see the actual ...
2
votes
2answers
3k views

What is the standard way to represent fixed point numbers in VHDL?

Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be ...
0
votes
1answer
285 views

How to model devices external to FPGA in a testbench?

FPGA could connect to lot of devices like memory devices (SRAM, SDRAM, DDR RAMs), data converters and various other complex ICs. Is it a normal practice to model them in a testbench to make ...
0
votes
1answer
183 views

Unexpected behaviour in Altera clock crossing FIFO

As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall ...
0
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2answers
572 views

Fatal Error for simulation of Full Adder in ModelSim

I am quite a novice in VHDL, but I decided to practice today my skills on designing a full adder. Simple task I thought, except that I somehow cannot manage to simulate my code correctly, even though ...
0
votes
1answer
396 views

Can ModelSim PE Student Edition co-simulate with MATLAB/Simulink?

I successfully simulated my Verilog code in ModelSim-Altera Starter Edition. I want to incorporate MATLAB/Simulink in my simulations. However, I failed. I have this error in ModelSim-Altera Starter ...