Questions tagged [modelsim]

ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.

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Multiple wire type objects declaration Verilog

I get an error everytime I try to use the same line to declare more than one wire type, is this because they are of different size (but I get the error even when they're of the same size, declaring ...
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1 answer
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FPGA I2C master not working

I have written an I2C master for the DE10-Nano FPGA which is meant to communicate with the SSD1306 OLED display driver. The issue I'm having is that it simply is not working when I actually test it on ...
2 votes
1 answer
52 views

How to set QuestaSim/ModelSim to print time value in arbitrary unit?

Here is the code: ...
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1 answer
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Modelsim merge libraries into same namespace

I am trying to figure out the best way to simulate an FPGA project in modelsim that contains multiple Xilinx Vivado IP. I have gone through the process of "Generating Output Products" for ...
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ModelSim can not simulate my VHDL code

I am learning to program FPGAs and my code is compiled in Quartus prime but my .do file does not simulate in ModelSim. Any help is appreciated. ...
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117 views

ModelSim transcript is not showing error log properly

ModelSim simulation gives me Error loading design error only I can't find out what the is problem. As far as I know, ModelSim should print such blue messages like ...
1 vote
1 answer
91 views

SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
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51 views

Modelsim Image Export Do Command

Is it possible to export a waveform in Modelsim as an image using a do command? I am able to do this through File->Export->Image, but I would like to automate the process to just spit out the ...
1 vote
1 answer
48 views

Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Some of the labels used in back-annotated netlist descriptions generated by Microchip (Microsemi) Libero rely on forward slash naming conventions as shown below ...
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-1 votes
1 answer
124 views

Experiencing issues with VHDL Code ModelSim: Wave Generation

I'm working on this project where I'm basically supposed to generate square wave (and other types of wave) using VHDL. The time period can be adjusted to either increase or decrease its frequency, and ...
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-1 votes
1 answer
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Modelsim: Debugging "NUMERIC_STD.TO_UNSIGNED: Vector truncated"

I might be able to post some code if needed, it's hard though cause the code is on a different machine. But I'm looking more a general approach to debugging this warning "NUMERIC_STD.TO_UNSIGNED: ...
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1 vote
1 answer
89 views

Signals acting weirdly in VHDL

I've always been told that a signal updates its values after a wait statement, or after a rising edge if we have for example if rising_edge(clk) then but in this testbench, after the first wait ...
-1 votes
1 answer
105 views

Error message vsim-3171 keeps popping up in Modelsim DE 2021.1 even though it was solved in Modelsim ME 10.2c

I have a test bench where I'm using a SystemVerilog bind construct. My test bench follows a similar organization to the one described at this link Every time I run it, error vsim-3171 shows up. I came ...
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1 answer
352 views

How to randomize the seed-number in Modelsim?

In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number. I was ...
1 vote
0 answers
54 views

Initializing feedback signal in ModelSim simulation

I'm trying to simulate a MOUSETRAP asynchronous pipeline for FPGA. For the control stage, I need to implement the following circuit: DELAY is a delay element which I have correctly implemented using ...
0 votes
1 answer
209 views

For QuestaSim, what's the difference between vsim.exe and vsimk.exe? [closed]

For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe? for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, ...
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2 votes
1 answer
264 views

Why is my counter not working? (Verilog)

I'm trying to create a counter that will display how many 1's are in the inputs. This is a little piece of code in the program: ...
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1 vote
1 answer
470 views

I'm trying to build a 16-bit adder in Verilog but my output and carryout always have a value of X

...
1 vote
1 answer
386 views

How to manage multiple testcases in a VHDL testbench

I'm trying to implement a testbench for a relatively complex module and I need multiple test cases to cover all the functionality. I'd like to find an elegant way to perform multiple testcases without ...
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2 answers
95 views

Unexpected change when reading input signals in a VHDL Finite State Machine

I implemented a FSM in vhdl using two processes; A sync process for state transition ...
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1 vote
1 answer
302 views

Radix-4 Booth's Multiplier verilog code error

I wrote the code for radix 4 booth's multiplier. But, I am getting 2 errors. I am not able to solve it. Could you please help? The errors are: Error: C:/modelsim_dlx64_2021.1/examples/assignment/...
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2 votes
1 answer
385 views

Where did I code my multiplier wrong?

I've wrote a verilog code for Multiplier (8bit). I'm not getting the right result. Kindly tell me where i went wrong. ...
1 vote
1 answer
66 views

Coarse counter giving incorrect pulse length measurements at high frequencies

I am using a simple counter to measure pulse length. I have copied the code below, but the counter increments by 1 at each positive edge of the clock. Once the counter is done incrementing for that ...
0 votes
1 answer
1k views

How to view the internal signals of module in ModelSim using the testbench?

I have looked over this tutorial (Tutorial - Using Modelsim for Simulation, for Beginners. ) how to add waves and write test benches for VHDL module I looked over some answers as well like this one to ...
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1 answer
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Unexpected behaviour of data memory in modelsim testbench

I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
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1 vote
1 answer
57 views

How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?

I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output: ...
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1 answer
244 views

Does Quartus support UVM in files with .sv extension?

I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make ...
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2 answers
428 views

Errors in VHDL code

The VHDL code was written by me for a 4-bit PIPO DFF register. I have been encountering some errors when i did so. Kindly check the code and errors below. ...
0 votes
0 answers
143 views

How to log Fixed-size Array with Mentor Modelsim/Questa in a tcl with add wave *

I have Fixed-size Array in port Out but my wildcard doesn't include them and I didn't find anything in the manual. ...
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1 vote
1 answer
339 views

How do i read the RGB values of an image in Verilog from a hex file generated in Matlab for processing?

I have used Matlab to generate hex file for an image (1200 * 900 resolution). The hex file is like There are such 3240000 rows. How do i read this in verilog to performing some processing (filtering ...
-1 votes
1 answer
3k views

Verilog code for construction of 4x16 decoder using 3x8 decoder [closed]

This is my 3x8 verilog module: ...
1 vote
0 answers
125 views

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
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1 vote
0 answers
197 views

Simulation of IP Core using ModelSim

I try to use IP core in Xilinx ISE 14.2. When the simulation done with ISim it works fine. Now I need to do the simualtion with ModelSim SE-64 10.7. I compile HDL Simualtion Libraries Fig.1. I run ...
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279 views

ModelSim does not run until "$stop" command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
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1 answer
364 views

Why is my 8-bit counter only counting until 127?

I recently coded an 8-bit counter in Libero and simulated it in ModelSim using Verilog. When I simulated my design, it only went up to 127. Shouldn't an 8-bit counter go up to 255? Here is my HDL Code:...
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1 answer
391 views

Writing to a Register happens one or two clock cycles after asserting write enable?

I am using the code shown here Verilog: Writing to a Register Happens A Clock Cycle Late and that user posted a picture where output would change 2 cycles after asserting write enable. That post got ...
1 vote
0 answers
2k views

How to use VHDL Entity in logisim evolution?

I'm new in Logisim and VHDL. I'm trying to use VHDL entity-component but the output always is "x". Then I read a document ( this link ) that said Logisim requires ModelSim to use this feature. So I ...
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3 votes
1 answer
1k views

Verilog output is hiZ in testbench

I'm new to verilog and modelsim. I'm having trouble with my AND and OR modules in this particular testbench. The output is always Z(hi impedance) ...
0 votes
1 answer
360 views

Help on writing test bench for up counter in verilog

preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.) However, I am very new at Verilog and also have never used ...
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1 vote
2 answers
93 views

Sequential logic in VHDL

Does anyone know of a way I can use sequential statements in VHDL without using the traditional if, case, when statements? I am building an 8 bit word splitter that will then pass a 4 bit nibble to ...
2 votes
1 answer
265 views

VHDL output pulse

I have another question regarding some VHDL. I am trying to create a pulse of 5 ms output (in my code a_full), however, I am struggling to find any information on how to generate this, basically I ...
1 vote
3 answers
285 views

ModelSim wave window showing zero time transitions

I'm new to verilog and so ModelSim. There's a problem or actually may not be a problem that I have noticed. It seems to me that ModelSim wave window imposes by default a transition at time zero on ...
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1 answer
295 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
0 votes
1 answer
439 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
-1 votes
1 answer
1k views

My work directory in ModelSim is always empty. How can I resolve this problem?

I'm new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was ...
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1 answer
1k views

Verilog Missing connection for port

I was creating a circuit using two dual input AND gates into a dual input NOR using three modules and module instantiation. The first module is for the AND inputs and the second module is for the ...
0 votes
1 answer
3k views

How to come out of the transcript window of Modelsim which is stuck?

I am running a Modelsim script and the transcript window gets stuck. I have tried the following to go to the next line in the transcript window without any success. Simulate > End simulation Simulate ...
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1 vote
0 answers
257 views

Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
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1 vote
1 answer
481 views

Why is this VHDL pseudo random number generator not working as expected?

I'll start off by saying I have about 2 days experience in VHDL so there's a strong chance my code is horrible. I would appreciate any tips on better VHDL practice. I am busy trying to simulate a ...
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1 answer
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Removing modelsim error

I am trying to simulate a simple inverter in verilog using modelsim 10.7 version. While compiling the code I am getting the -novopt error (error code 12110). As per user manual page 80; the -novopt ...