Questions tagged [modelsim]
ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.
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Can you interface a Modelsim testbench with an external stimuli
I am working on a team that is doing both driver software and FPGA development. The FPGA simulation is being done in Modelsim and driver software is written in C. To minimize integration risk, I ...
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VHDL: What does STD_INPUT and STD_OUTPUT appearing in std.textio mean?
The package contains the following lines:
file INPUT: TEXT is in “STD_INPUT”;
file OUTPUT: TEXT is out “STD_OUTPUT”;
For some reason these remind me of the standard input and output streams from my ...
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Simulating IBIS Model in modelSim
I am developing a logic in an FPGA that will act as a controller for a chip by TI. I got the TI chip IBIS model from the TI website.
My controller is ready and I want to simulate it using ModelSim. ...
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Estimating power consumption in cadence RTL compiler with VCD file
I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files:
gcm.v (This is the main circuit. Module name is "gcm")
tb.v (This is the ...
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Can VHDL read binary files i.e non text files?
I have a binary file which represents memory contents of a memory device. I want to load these into my testbench. The hex file obviously is not text file thus no concept of line break and carriage ...
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Quartus, Modelsim, VHDL - Viewing Internal Signals
This question is rather specific which makes it rather hard to answer.
I'm using Quartus Prime software from Altera to do an FPGA design in VHDL. Quartus exports to Modelsim for the simulation. I'm ...
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Help on writing test bench for up counter in verilog
preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.)
However, I am very new at Verilog and also have never used ...
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