Questions tagged [modelsim]

ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.

Filter by
Sorted by
Tagged with
1
vote
1answer
88 views

Where did I code my multiplier wrong?

I've wrote a verilog code for Multiplier (8bit). I'm not getting the right result. Kindly tell me where i went wrong. ...
0
votes
0answers
18 views

SPI Altera master IP not behaving as expected

Using Platform designer on Quartus, This is a system with Nios and SPI IP. The code on the nios is attached. This code is supposed to drive the MOSI output to 1 forever, the MOSI on the waveform is ...
1
vote
1answer
48 views

Coarse counter giving incorrect pulse length measurements at high frequencies

I am using a simple counter to measure pulse length. I have copied the code below, but the counter increments by 1 at each positive edge of the clock. Once the counter is done incrementing for that ...
0
votes
1answer
71 views

How to view the internal signals of module in ModelSim using the testbench?

I have looked over this tutorial (Tutorial - Using Modelsim for Simulation, for Beginners. ) how to add waves and write test benches for VHDL module I looked over some answers as well like this one to ...
0
votes
0answers
23 views

Why I cannot edit waveform in ModelSim Intel?

I would like to create my own testbench for the code vhdl. I tried to use the edit function from ModelSim but it does show blank as you see on the picture. what could I have missed?
0
votes
1answer
35 views

Unexpected behaviour of data memory in modelsim testbench

I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
0
votes
1answer
44 views

How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?

I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output: ...
0
votes
1answer
31 views

Does Quartus support UVM in files with .sv extension?

I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make ...
0
votes
2answers
83 views

Errors in VHDL code

The VHDL code was written by me for a 4-bit PIPO DFF register. I have been encountering some errors when i did so. Kindly check the code and errors below. ...
0
votes
0answers
31 views

How to log Fixed-size Array with Mentor Modelsim/Questa in a tcl with add wave *

I have Fixed-size Array in port Out but my wildcard doesn't include them and I didn't find anything in the manual. ...
0
votes
0answers
41 views

Error loading design Instantiation of 'addtwobit' failed. The design unit was not found

I was writing Verilog code for an ALU from the nand2tetris course This code compiled without any errors in ModelSim but when I try to start simulation it throws an error Error loading design ...
1
vote
1answer
108 views

How do i read the RGB values of an image in Verilog from a hex file generated in Matlab for processing?

I have used Matlab to generate hex file for an image (1200 * 900 resolution). The hex file is like There are such 3240000 rows. How do i read this in verilog to performing some processing (filtering ...
-1
votes
1answer
754 views

Verilog code for construction of 4x16 decoder using 3x8 decoder [closed]

This is my 3x8 verilog module: ...
0
votes
0answers
35 views

Verilog State Diagram Problem

I am trying to implement the SPI_SLAVE ...
2
votes
0answers
78 views

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
0
votes
0answers
18 views

Testbench for RTL and GLS simulation

I want to do the GLS simulation after the RTL simulation. I was asked to add uut : entity work.eq3(structure) instead of the one specified below used for RTL <...
1
vote
0answers
110 views

Simulation of IP Core using ModelSim

I try to use IP core in Xilinx ISE 14.2. When the simulation done with ISim it works fine. Now I need to do the simualtion with ModelSim SE-64 10.7. I compile HDL Simualtion Libraries Fig.1. I run ...
1
vote
0answers
36 views

Post-synthesis simulation using Nangateopencelllibrary_pdkv1_3_v2010_12

I'm wondering if anyone has used the open-source Nangate library to do synthesis and post-synthesis simulation? I was trying to synthesis my processor and got the netlist verilog file from design ...
0
votes
0answers
82 views

ModelSim does not run until “$stop” command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
0
votes
1answer
116 views

Why is my 8-bit counter only counting until 127?

I recently coded an 8-bit counter in Libero and simulated it in ModelSim using Verilog. When I simulated my design, it only went up to 127. Shouldn't an 8-bit counter go up to 255? Here is my HDL Code:...
0
votes
1answer
98 views

Writing to a Register happens one or two clock cycles after asserting write enable?

I am using the code shown here Verilog: Writing to a Register Happens A Clock Cycle Late and that user posted a picture where output would change 2 cycles after asserting write enable. That post got ...
0
votes
0answers
66 views

error loading design

I am trying to simulate a testbench. I have compiled the testbench and the file it is testing and everything compiles without errors. When I try to simulate the testbench it says "error loading design"...
0
votes
0answers
472 views

How to use VHDL Entity in logisim evolution?

I'm new in Logisim and VHDL. I'm trying to use VHDL entity-component but the output always is "x". Then I read a document ( this link ) that said Logisim requires ModelSim to use this feature. So I ...
2
votes
1answer
309 views

Verilog output is hiZ in testbench

I'm new to verilog and modelsim. I'm having trouble with my AND and OR modules in this particular testbench. The output is always Z(hi impedance) ...
0
votes
0answers
18 views

What is the easiest way to simulate and experiment with FPGA using simulated external DDR3?

For a computer architecture school project I have to implement an algorithm in verilog, such design have to input and output a VERY large ammount of data that wouldn't fit in on-chip memory, hence I ...
0
votes
1answer
80 views

Help on writing test bench for up counter in verilog

preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.) However, I am very new at Verilog and also have never used ...
0
votes
0answers
52 views

Why am I getting weird behavior when building 4-bit down counter?

I'm attempting to build a 4-bit modulo-10 down-counter (i.e 9,8,7...,1,0,9,8,7...0). Here is my code so far: ...
0
votes
0answers
113 views

Range error during Modelsim simulation of a VHDL user-defined resolved data type

When running a simulation of a testbench involving a user-defined resolved data-type, I get an error report of the form: "** Fatal: (vsim-3734) Index value 1 is out of range 0 to 1" , followed by ...
1
vote
2answers
70 views

Sequential logic in VHDL

Does anyone know of a way I can use sequential statements in VHDL without using the traditional if, case, when statements? I am building an 8 bit word splitter that will then pass a 4 bit nibble to ...
1
vote
1answer
121 views

vhdl output pulse

I have another question regarding some VHDL, I am trying to create a pulse of 5ms output for (in my code a_full) however I am struggling to find any information on how to generate this, basically I ...
0
votes
2answers
103 views

ModelSim wave window showing zero time transitions

I'm new to verilog and so ModelSim. There's a problem or actually may not be a problem that I have noticed. It seems to me that ModelSim wave window imposes by default a transition at time zero on ...
0
votes
1answer
104 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
0
votes
1answer
181 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
0
votes
1answer
840 views

My work directory in ModelSim is always empty. How can I resolve this problem?

I'm new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was ...
1
vote
1answer
411 views

Verilog Missing connection for port

I was creating a circuit using two dual input AND gates into a dual input NOR using three modules and module instantiation. The first module is for the AND inputs and the second module is for the ...
0
votes
1answer
1k views

How to come out of the transcript window of Modelsim which is stuck?

I am running a Modelsim script and the transcript window gets stuck. I have tried the following to go to the next line in the transcript window without any success. Simulate > End simulation Simulate ...
0
votes
0answers
134 views

Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
1
vote
1answer
269 views

Why is this VHDL pseudo random number generator not working as expected?

I'll start off by saying I have about 2 days experience in VHDL so there's a strong chance my code is horrible. I would appreciate any tips on better VHDL practice. I am busy trying to simulate a ...
0
votes
1answer
2k views

Removing modelsim error

I am trying to simulate a simple inverter in verilog using modelsim 10.7 version. While compiling the code I am getting the -novopt error (error code 12110). As per user manual page 80; the -novopt ...
0
votes
1answer
77 views

Set alternative editor for ModelSim

I want to set an alternative editor in ModelSim. I tried How to configure my favorite editor in ModelSim? and after I set the altEditor I get "unknown command external_editor". Unfortunately my ...
0
votes
1answer
100 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
-2
votes
1answer
392 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
7
votes
1answer
244 views

VHDL Procedure - Same variable for input/output parameter

I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this: ...
0
votes
0answers
61 views

VHDL - Unable to correctly implement complex scheduling of data lines to Inputs of multiplexers

In my design, I have two configurable parameters ...
1
vote
1answer
211 views

Why am I getting a red wire for my out?

I am attempting to create an output that goes on for a certain amount of time an then goes low for a certain amount of time and my out simply won't simulate. Attached is my code, test bench, and ...
0
votes
1answer
143 views

How add delays to everything in Verilog or SystemVerilog outside of .v or .sv file

All delay documentation I've seen is pretty low level -- add a #5 or whatever and that particular assignment gets a delay. Use this in a module and instantiate, etc, etc. There are variations on ...
0
votes
1answer
2k views

error loading design - modelsim

I'm new to modelsim and Verilog and I have got an error in it: # Region: /seqdectorTB # Error loading design 1.3.v: ...
-1
votes
1answer
3k views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
0
votes
1answer
667 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
0
votes
2answers
514 views

Passing VHDL string generic with spaces via Modelsim command line

Given the following code: entity foo is generic ( VAL : string ); end entity foo; architecture behav of foo is begin end architecture behav; How can I ...