Questions tagged [modelsim]

ModelSim is hardware simulation and debug environmment targeted at ASIC and FPGA designs with native support for Verilog, SystemVerilog for design, VHDL, and SystemC.

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11
votes
1answer
10k views

How do I debug red signals in ModelSIM?

I have to design a state machine using only NAND gates for the combinatorial part and D flip flops for the sequential logic. Everything should run at a clock of 1ghz/53. Now before you assault me ...
10
votes
2answers
7k views

Can you interface a Modelsim testbench with an external stimuli

I am working on a team that is doing both driver software and FPGA development. The FPGA simulation is being done in Modelsim and driver software is written in C. To minimize integration risk, I ...
8
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1answer
2k views

Why does this simple VHDL pattern for a shift register not work as expected

At first glance you would expect the VHDL source code below to behave as a shift register. In that q, over time would be ...
7
votes
1answer
244 views

VHDL Procedure - Same variable for input/output parameter

I've written a component where I use the same variable for the input and output parameter of a procedure. A reduced example looks like this: ...
6
votes
1answer
32k views

How do I save a waveform from ModelSim for later opening/viewing

If I save the waveform, it is saved as a .do file in ModelSim/QuestaSim. This does not help as later I will have to run the simulation to get the wave back anyway! What I am looking for is means by ...
5
votes
1answer
383 views

Simulating an IP core in Modelsim is delayed by one clock cycle

I compiled the IP core library in Modelsim. The library from Xilinx is installed on my computer and I also created a ROM using the Xilinx tools. However when I simulate the IP core I find that ...
4
votes
3answers
27k views

How to Add the Xilinx Library to Modelsim?

I'm trying to simulate an example design of an IP Core, but the version of ModelSim I have installed (Altera Edition/Linux) does not link to the Xilinx library. How can I permanently or temporarily ...
4
votes
1answer
7k views

VHDL simulation shows 'X' for input

I'm new to VHDL and I'm trying to simulate an array multiplier.(I have used verilog before). However in the simulation results it shows 'X' for inputs which used to be '1'.Here is the result: And this ...
4
votes
2answers
5k views

ModelSim Error : “ could not find interpreter ”ScintillaTk“ ”

I have installed ModelSim 10.4 X64, when I want to open a vhd file in editor an error shown in "Transcript" window as : " could not find interpreter "ScintillaTk" " I searched about that and I found ...
3
votes
2answers
2k views

What does delta stands for in ModelSIM?

I ran a simulation for a combinational logic circuit with 8 inputs, 4 outputs inside MODELSIM. When I view the simulated waveform everything looks fine, however when I export result to a list file ...
3
votes
2answers
2k views

Simulation of large RAM

I want to test a video IP core that reads a block of memory and writes to it again. The IP core is using the VFBC. My idea for testing was to write a core that looks like the VFBC, but just uses a ...
3
votes
2answers
5k views

What is the standard way to represent fixed point numbers in VHDL?

Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be ...
3
votes
2answers
467 views

how slow are modelsim free licences?

I know in free licenses of modelsim / questa simulations run slower than the full version. But how slow? will it be 2x 3x 10x faster in the paid version? what about actel/microsemi free version ?
3
votes
1answer
774 views

Simulating IBIS Model in modelSim

I am developing a logic in an FPGA that will act as a controller for a chip by TI. I got the TI chip IBIS model from the TI website. My controller is ready and I want to simulate it using ModelSim. ...
3
votes
2answers
3k views

Open a picture and read its Pixel Values

I want to calculate the Histogram of an Image is grayscale color mode I have designed a memory and a Calculator of Histogram value, now I want to get Pixel values and put them in Calculator as Input ...
3
votes
1answer
1k views

ModelSim Altera: simulating the “lpm_add_sub” module?

I'm trying to simulate a verilog module that uses the "lpm_add_sub" module to provide an adder with a separate carry in (for some reason Quartus II doesn't recognise that ...
3
votes
4answers
368 views

Simulating Altera FPGAs with an old version of ModelSim?

I'm hoping to do some development work on Altera FPGAs that will likely be larger than is supported by the free edition of ModelSim. I have an old copy of the full version hanging around (version 6.5,...
3
votes
1answer
3k views

Why does Modelsim say that VHDL shared variables must be protected?

So I created a shared variable in a purely non-synthesizeable code. When compiling ModelSim generates a warning: (vcom-1236) Shared variables must be of a protected type. Why is it a warning and ...
3
votes
4answers
7k views

How to speed up Modelsim simulation

How can I get Modelsim to run faster for simulation rather than something in the picosecond range (time interval)? Are there any other methods for speeding up simulation? It takes 45 minutes to get ...
3
votes
2answers
1k views

VHDL: What does STD_INPUT and STD_OUTPUT appearing in std.textio mean?

The package contains the following lines: file INPUT: TEXT is in “STD_INPUT”; file OUTPUT: TEXT is out “STD_OUTPUT”; For some reason these remind me of the standard input and output streams from my ...
3
votes
2answers
2k views

Is it possible to have multiple wave windows in ModelSim?

Is it possible to have multiple Wave windows opened in ModelSim simultaneously? I know it is possible to add multiple "Window panes" in a single Wave window but it's so buggy and un-flexible that is ...
3
votes
2answers
2k views

VHDL process requires multiple clock cycles

I wrote a simple counter in VHDL for a program counter. Everything is done in a process, but what I dont understand is that in the simulation, the addition of the program counter, is only done at the ...
3
votes
1answer
176 views

Modelsim - Weird verification problem with DDR and Xilinx UNISIM

I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...
3
votes
1answer
2k views

How to reference subsets of logic[31:0] in SystemVerilog?

(I have two questions for you at the end.) I'm using SystemVerilog to do various exercises (for personal edification) in Digital Design and Computer Architecture's chapter 7. I'm using Altera's ...
3
votes
2answers
683 views

Design a T flip flop in VHDL using Modelsim, signal values not changing as expected

I was trying to design a TFF in VHDL. I wrote the code below ...
2
votes
2answers
2k views

QuestaSim/ModelSim simulation gives me unkown value in wave window. However I get them as X and x, what is the difference between the two?

What is the difference between big X and small x when we get red (unknown) signals in QuestaSim? I would assume it to be the same in ModelSim simulation as well.
2
votes
1answer
2k views

Aggregate of 2 vectors in VHDL

I am checking what I can and cannot do in aggregating and concatenating in VHDL. while I can combine two vectors by concatenating them, I keep getting error if I use aggregate. I saw one answer here ...
2
votes
2answers
5k views

How do I compare waveforms from multiple simulations in QuestaSim/ModelSim

I want to compare the waveform result from different tets. So basically the test stimulus changes but the unit under test is the same in all cases. What steps do I need to follow to do this? ...
2
votes
1answer
468 views

In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

I'm writing some verilog and simulating it using modelsim. I have a block that looks like this: ...
2
votes
2answers
348 views

Histogram Graph in ModelSim Simulator

I have a Memory (Register Bank), this bank has 255 registers that each register contains a 16 bit number, type of registers is STD_LOGIC_VECTOR but there is no problem if I should convert them to ...
2
votes
1answer
1k views

Using generic packages with protected type in Modelsim 10.xy

I am trying to use generic packages with a protected type in Modelsim 10.0a. The technote vhdl2008.note states: a basic generic package and its instantiation with some noteworthy restrictions:...
2
votes
1answer
310 views

Verilog output is hiZ in testbench

I'm new to verilog and modelsim. I'm having trouble with my AND and OR modules in this particular testbench. The output is always Z(hi impedance) ...
2
votes
2answers
926 views

disable “show base” item in Modelsim for automation

I have trying to write a do do file for automation. I want to disable the "show base " item in waveform. So what is the command ?
2
votes
0answers
78 views

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
2
votes
0answers
145 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
2
votes
0answers
1k views

Export Modelsim waveform as image from command-line

Is there a way to export Modelsim/VCS waveforms as images (png, jpeg or SVG)? Currently the only method I know of is to fire up the simulator, run the simulation and then either do a Print Screen or ...
2
votes
0answers
212 views

Reading of hex file in testbench : Verilog [duplicate]

I have converted an image file into hex file which has R,G,B and alpha values in multiple columns. For example : 3c 48 36 ff 1d 2b 19 ff 08 18 06 ff 08 17 05 ff 14 1f 0d ff 1b 22 11 ff 1a 1f 0e ff 1a ...
1
vote
2answers
3k views

Flip signal values in verilog simulation

I use "force" command in modelsim to force an internal signal to a specific value (not primary inputs). Sometimes, the value I force is the same as the original value. Is there any command that can ...
1
vote
1answer
2k views

ModelSim: Why can't I see generics in simulation?

When I start simulation, I can see signals and ports in the objects window for what I have selected in the Sim window. Besides this, I can see processes for the same thing in the processes window. ...
1
vote
1answer
2k views

Does modelsim support shift right arithmetic in verilog?

I am using ModelSim PE Student Edition, and I am trying to write a module which shifts right arithmetic. After searching online, and consulting a Verilog textbook, I found to shift right arithmetic I ...
1
vote
1answer
88 views

Where did I code my multiplier wrong?

I've wrote a verilog code for Multiplier (8bit). I'm not getting the right result. Kindly tell me where i went wrong. ...
1
vote
2answers
4k views

Export Modelsim waveforms as image for printing

I want to export the Modelsim waveforms of my simulated design in a form where they can look decent when printed. To be more specific, without the black background, in a vector format preferably. Not ...
1
vote
1answer
2k views

TEXTIO : Read past end of file in ModelSim Simulation

...
1
vote
1answer
48 views

Coarse counter giving incorrect pulse length measurements at high frequencies

I am using a simple counter to measure pulse length. I have copied the code below, but the counter increments by 1 at each positive edge of the clock. Once the counter is done incrementing for that ...
1
vote
1answer
11k views

Work library is empty after compiling Verilog source file in Modelsim [closed]

How I can solve this problem: my Work library is always empty after compiling a selected file in Modelsim?
1
vote
2answers
148 views

What is the equivalent of compile of modelsim in quartus prime?

In ModelSim, I can click compile and ModelSim will compile it quickly, around 1 or 2 seconds. But in Quartus Prime, I need to run Analysis & Elaboration or Analysis & Synthesis which runs ...
1
vote
1answer
789 views

VHDL - Issue with simulation of testbench - Modelsim PE Student 10.4

I'm very new to VHDL and got an issue with the simulation time in Modelsim PE Student Edition 10.4. I wrote some files for a RTL-model such as multiplexer, demultiplexer and register. To test my ...
1
vote
1answer
490 views

Compile error in testbench with UVM (mtiRnm library)

I'm trying to compile a very basic testbench (that actually does nothing) with Modelsim 10.3b. However, I'm facing the error: ...
1
vote
1answer
158 views

Cursor (waveform) reading not the same with transcript window

I have run a simulation of a Verilog code testbench. I ran it in ModelSim, but why the reading I got from just using the cursor on the waveform is different from the one in transcript window. While ...
1
vote
1answer
2k views

How can I find out if library has already been compiled in ModelSim/QuestaSim to speed up simulation scripts?

How can I find out if library has already been compiled in ModelSim/QuestaSim to speed up simulation scripts? I have some files that contain multiple vlog commands to compile several libraries and ...