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Questions tagged [module]

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1answer
32 views

Measure Power Consumption of Battery Charger?

I want to ask how to measure power consumption of battery (Li-On 18650) charger module (TP4056 and USB Boost) and the total power consumption, if i have this circuit: I have already know the power ...
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3answers
78 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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1answer
55 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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2answers
94 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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1answer
22 views

How to assign a single output to different modules in Verilog?

I have designed a simple ALU using Floating Point IP Cores in Xilinx ISE. I have an adder, a subtractor, and a multiplier. The IP Core of addition does the subtraction too and we have only two modules ...
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2answers
35 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
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3answers
103 views

doubt when Arduino connects to multiple i2c devices

I am using Arduino nano to drive multiple i2c devices, actually, they are premade modules which are available on eBay. ads1115 ADC, ds3231 RTC, 20x4 character LCD i2c module, at24c02 EEPROM module ...
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0answers
20 views

Timing relay for delayed pulse

I'm trying to achieve this Tried many timing relays but couldn't find one with this function. There are ones to delay both rising and falling edges but it doesn't work when delay is longer than ...
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1answer
44 views

Verilog Include Statement Error

I'm trying to teach myself Verilog. I have some previous experience using VHDL. I am using Lattice Diamond as my environment. I successfully created and simulated a full adder. I now want to use this ...