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Questions tagged [module]

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91 views

Should I remove the termination resistor from the CAN Bus transceiver module?

I develop a CAN-BUS receiver (logger) with an ESP32 and CAN-BUS transceiver. The CAN-BUS transceiver modules which I found and bought have both 120 Ohm termination resistors. But the CAN-BUS to which ...
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1answer
50 views

Any solution to avoid humming sound / speaker noise for MP3 bluetooth module?

So I have here sub woofer Simbadda CST 5100N and I want to convert it to bluetooth, so bought an MP3 bluetooth module to convert it. The module needed 5 to 12 volt DC to operate. Inside the speaker, ...
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2answers
95 views

ESP32 FCC Certification

I want to build an esp32 device using the esp32-pico-d4 chip that I will sell to hobbyists. However, I recently came across something called the FCC. It requires radio devices to get certified which ...
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1answer
58 views

Verilog Missing connection for port

I was creating a circuit using two dual input AND gates into a dual input NOR using three modules and module instantiation. The first module is for the AND inputs and the second module is for the ...
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0answers
29 views

Connecting BLE module to Lipo battery and recharge it?

I would like to use a BLE module, where I can solder a tactile switch. There should be also the option to charge the module via USB. Earlier I have only worked with breakout boards, where I could ...
1
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1answer
76 views

Instrumentation Amplifier Connection Problem

I am trying to build a circuit capable of measuring ECG signals following the scheme attached. Since AD623 was out of stock, i ended up buying something like this: https://www.arduino-tech.com/cjmcu-...
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3answers
89 views

Instantiating module in condiotional block verilog

Considering a module cannot be instantiated inside if block, how are we supposed to instantiate the module outside the if-else ...
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1answer
37 views

What is the difference between a hard module and a softmodule in RTL verilog code?

I understand a Verilog code is made up of modules there are RTL codes where a lot of submodules can be instantiated in the main module. If I assume the main module(the top one) to be the parent and ...
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2answers
97 views

Step down converter PCB

Is one side of R050 connected to OUT- ? To nut for the acrylic housing would bridge the little gap there - is that a problem? Thx.
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1answer
55 views

Module identification

Can anyone recognize this module in this pic here? I am analysing a circuit and it would help me a lot!
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0answers
55 views

What can i do with a WM8192EU USB module?

I recently came across a wm-8192eu usb module from an old electronic doorbell. It had a socket on the board that it just slid right out of. When i googled the chip it showed a bunch of usb wifi ...
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0answers
51 views

Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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1answer
68 views

Measure Power Consumption of Battery Charger?

I want to ask how to measure power consumption of battery (Li-On 18650) charger module (TP4056 and USB Boost) and the total power consumption, if i have this circuit: I have already know the power ...
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1answer
58 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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3answers
138 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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2answers
148 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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1answer
24 views

How to assign a single output to different modules in Verilog?

I have designed a simple ALU using Floating Point IP Cores in Xilinx ISE. I have an adder, a subtractor, and a multiplier. The IP Core of addition does the subtraction too and we have only two modules ...
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2answers
49 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
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3answers
179 views

doubt when Arduino connects to multiple i2c devices

I am using Arduino nano to drive multiple i2c devices, actually, they are premade modules which are available on eBay. ads1115 ADC, ds3231 RTC, 20x4 character LCD i2c module, at24c02 EEPROM module ...
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0answers
32 views

Timing relay for delayed pulse

I'm trying to achieve this Tried many timing relays but couldn't find one with this function. There are ones to delay both rising and falling edges but it doesn't work when delay is longer than ...
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1answer
56 views

Verilog Include Statement Error

I'm trying to teach myself Verilog. I have some previous experience using VHDL. I am using Lattice Diamond as my environment. I successfully created and simulated a full adder. I now want to use this ...