Questions tagged [multiplication]

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How to multiply by 3 a natural number given in binary, using combinatorial logic?

How to multiply by 3 a natural number in n-bit binary representation? Adding x to 2x(x shifted one bit position to the higher significance positions) reads simple enough. For a ripple carry adder, ...
greybeard's user avatar
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Adding four numbers of 1 bit each and then cascading them

When I add four bits (NOT FOUR BIT ADDER, only four bits), the result can go to a maximum of 100 (4 in decimal, if all are ones). Now, here 0 (LSB) is the sum and 10 is carry. If I want to transfer ...
Shehryar Kashif's user avatar
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Frequency multiplication with PLL circuit

I am currently working on frequency multiplication with a PLL circuit. I want to give it an input frequency of 10 kHz to 100 kHz and I want to get 160 kHz to 1.6 MHz from the VCO output. That's a ...
natarajmarble's user avatar
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Multiplication of pulse trains

Suppose I have two pulse trains, with pulses some tens of nanoseconds apart and long (evenly spaced and equally for both of them). Each of the pulses has some amplitude \$v_n\$ in one train and \$v_n'\...
benfisch's user avatar
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Demonstration of Unsigned to Signed Binary Multiplication

I am trying to deepen my knowledge about multiplication with signed binary numbers (in two's complement) and as I was following along a video about the multiplication of 4-bit signed binary numbers, I ...
Filipe Almeida's user avatar
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Multiplication 32x32 Mealy machine using 16x8 multiplier Verilog code

I am trying to implement a multiplication 32x32 Mealy machine using a 16x8 multiplicator in Verilog. I wrote the arithmetic part and the FSM part + a code to connect both and a test bench, but when I ...
SpaceNugget's user avatar
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Is there a modular multiplier design that can give the result in 1 cycle?

I need to perform modular multiplication on two large numbers (more than 10,000 bits wide). I've found papers that give designs that can that calculate the result in N cycles, but in my case, that ...
Hisoka's user avatar
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Avr-gcc using repeated addition instead of MULU instructions

I recently compiled some C++ code for the ATmega1284P in Atmel Studio and was analyzing the timings of some routines using my scope. To my surprise, a loop I thought I had optimized was taking longer ...
Hackstaar's user avatar
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FPGA multiplication using DSP hardware, signed vs. unsigned

I'm using the DSP unit (just a fancy name for the multiplier/accumulator unit) of the Gowin GW1N devices to do some fairly simple math. These units accept two 18 bit inputs for the multiplier adding ...
gnuarm's user avatar
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Multiplying twos complement binary numbers

I have a project where I am developing a basic processing core on a FPGA from logic gates. So of course I have an ALU that I am building out of logic gates. I have no issues with the rest of the ALU ...
David777's user avatar
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