Questions tagged [nand]

Use this tag when referring to any circuit that uses NAND gate / NAND logic, or for asking questions relating to NAND gates.

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9T SRAM Circuit Supporting 1-bit Multiplication

I was reading a paper that added a 3T NAND gate, consisting of two NMOS and one PMOS, to the regular 6T SRAM, achieving 1-bit multiplication. However, I'm struggling to understand how the NAND part of ...
BlueSun's user avatar
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0 votes
2 answers
222 views

Implementing a circuit using only NAND-2 gates

I have this boolean expression that I got through a k-map twice, once using POS and the other SOP, and I am supposed to implement both minimized f's that I found using only NAND-2 gates but I am very ...
Salma Mostfa's user avatar
-1 votes
1 answer
178 views

SPI NAND rewrite issue

I'm using Alliance Memory's AS5F38G04SND-08LIN 8Gbit(1 Gbyte) SLC NAND flash with STM32. Datasheet So my question is, Can I re-write a page with data already in it? Page size is 4096 bytes. For ...
Alatriste's user avatar
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2 answers
62 views

How does moving an input signal node closer to the output node reduce parasitic capacitance

So I have been studying about logic gates designed using the CMOS family and in my professors notes it says "Move NMOSFET-B closer to output node, without changing the functionality , to reduce ...
zero_day's user avatar
0 votes
1 answer
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Some chips (probably DRAM) on NVMe SSD are lower than others, resulting heatsink having no contact with those chips after installation

I believe most of the NVMe SSD heatsinks' contact surface is just one flat piece, but not all the chips on the NVMe SSDs have the same height. From my recent observation, there are air gaps between ...
Sij's user avatar
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2 votes
2 answers
232 views

NAND gate with two vs. one BJT transistor(s)

Why is everybody discourage from this paired NAND BJT Transistor "design"? I already saw a few posts where somebody asked something about the paired BJT NAND "design" and the ...
wolflu's user avatar
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1 vote
1 answer
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Current flow in PMOS when not active

how can it be that Q2 is active when VA and VB are HIGH? If I understand correctly, a current (shown in yellow) should flow... But that is in my understanding not possible because both NMOS are ...
BukkitDEV's user avatar
1 vote
0 answers
156 views

Chaining NAND gates does not work and results in wrong simulation with LTspice

I started building basic logic gates. I wanted to start basic and understandable so I started building some NAND gates just using two transistors. On its own hooked up to a switch and a LED they work ...
wolflu's user avatar
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6 votes
7 answers
2k views

Should I glue BGA chips in the corners before soldering them with hot air?

I have often see ball grid array (BGA) chips, mostly those from CPUs or GPUs, being glued around in the corners with some red glue or to the perimeter with a translucent one. Having to manually solder ...
OuzoPower's user avatar
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1 answer
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MOSFET circuit truth table

In the attached image you can find a simple circuit with two self blocking N channel MOSFETs. If the gate is powered they conduct. So my truth table looks like a AND operation. Why is this wrong? Why ...
Robert's user avatar
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4 votes
2 answers
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"Path to ground with no resistance!" error when trying to simulate a circuit

I'm trying to simulate a NAND gate using transistors and I have remade the circuit as it was in the notebook, but the simulator shows me the error in the title. This is the circuit scheme: What is ...
Kudor's user avatar
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1 answer
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Can the internal FET be disabled?

In this device, can the internal FET be disabled for the CRD_PWR pin? Can the CRD_PWR pin be left floating?
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1 vote
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What should I fix in my settings in PSpice for simulation?

I am trying to build a D flip-flop from CMOS NAND gates. This is the CMOS circuit to be built with NAND gates: I can simulate NAND gate logic like this, and it works: 1 0 = 1, 0 1 = 1, 0 0 = 1, 1 1 = ...
Phongpit Sribua's user avatar
0 votes
3 answers
177 views

Schottky TTL current calculator [closed]

I have a problem from university where I have to calculate the I ccl. I am a little bit confused because I don't know how to do it. The problem says as well that Schottky TTL state is 0 logic (I think ...
Florin Sebastian's user avatar
2 votes
0 answers
152 views

Frequency counter capable of measuring a range of 0 to 99 Hz

The frequency counter in Figure 2 has a range of 0 to 9 Hz and a resolution of 1 Hz. The schematic for this circuit is shown below: I'm trying to understand how this circuit works and how to increase ...
Licentia's user avatar
1 vote
0 answers
271 views

Mux 2:1 with NAND gate and function generator

I want to simulate the operation of a 2:1 mux using only NAND gates. I want to insert two square wave signals and obtain the corresponding result depending on whether the selection is 0 or 1. With the ...
Majid Benkirane Y Bakhat's user avatar
1 vote
3 answers
394 views

SR flip-flop with Preset and Clear should not work as described

In the presented flip-flop, suppose the Enable signal is high, the S is low, and R is high. Now we set the Preset low (0) and the Clear high (1). In this condition, we expect Q=1 and Q'=0. But ...
Tomas's user avatar
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6 votes
1 answer
537 views

Minimizing logic expression for two-input NAND gate implementation

I have recently been struggling with this homework problem that is requiring minimization of a logic expression to be implemented using all NAND gates. The problem requires a very small number of NAND ...
armencm02's user avatar
2 votes
2 answers
1k views

Why is this NAND gate not turning on with both inputs off?

Problem I am trying to simulate a circuit that acts like a memory bit in Logisim Evolution but for some reason the NAND gates don't turn on with both outputs set to 0. I suspect that the problem ...
Sujal Singh's user avatar
0 votes
2 answers
142 views

NAND output connected to P-MOSFET gate

I am connecting an NAND logic gate output to a Pchannel mosfet gate and intending under normal conditions to sink current into the NAND output. But there are two scenarios about this setup which are ...
Feynman137's user avatar
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How can we know that when n1 and n2 is 1, the output is 0? What makes the circuit a NAND?

We start with the obvious part of the circuit, N1 and N2 are in series. I was given the truth table, where both N1 and N2 are 1, then the output is 0 and the rest is 1. By this picture, how can we ...
data 's user avatar
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0 votes
2 answers
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Can circuit without memory give output depending on the order in which input pins were activated for non-commutative operations?

Going trough making small NAND based computer. I have two input pins zy (zero 16 bit Array y), ny (negate bitwise 16 bit Array y). Implementing each one separately or in connection is no problem but ...
Andrey Sergeev's user avatar
2 votes
1 answer
126 views

Modeling a NAND flash cell (a MOSFET with a floating gate)

After checking the ADS component palette, I found there are some MOSFET models available but there are no NAND flash cell models. How do I create one? A NAND flash cell can hold different states (...
kintaro's user avatar
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1 vote
0 answers
918 views

T flip flop from NAND gates

I recently was interested in whether a T flip flop could easily be made from NAND gates. A google search did reveal lots of examples that basically all look like an RS flip flop with two additional ...
user52366's user avatar
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0 answers
411 views

Convert boolean expression to nand gate only. X = A'B'C+AB'C'+A'B'

I have already made a diagram. However, it won't match the truth table that I have made, which I got from the logic converter in multisim. Could you please help me out with where did I go wrong? Is it ...
trese's user avatar
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0 votes
2 answers
754 views

How to invert a NAND gate IC and have it work like an AND gate IC?

I have created this circuit design using tinkercad. I thought I had two 74HC08 IC:s. Turns out I only have one. Can I replace the second 74HC08 with an inverted 74HC00 and if so how do I do this? If ...
Dyson's user avatar
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1 vote
2 answers
749 views

How do I make a NAND SR-latch with transistors

I'm trying to make a NAND SR-latch using only transistors, by combining a schematic for a NAND gate and a schematic for an SR-latch. The resulting circuit looks like this: (One thing not shown is ...
Johannes Hoff's user avatar
2 votes
0 answers
127 views

NAND read returns 0 blocks

I need to perform a firmware extraction, so I extrcted the NAND TSOP48 chip from the board. Chip part no: S34MS01G200TFI00 Link to chip: link to chip I then mounted it on a NAND reader Link to NAND ...
dclaudiud's user avatar
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4 votes
1 answer
629 views

Line follower robot using only NAND gates

I'm stuck on this and would appreciate some pointers. So for class I have to figure out the logic for a line follower robot using at maximum 8 NAND gates (two 74HC00 Quad NAND ICs). The robot has ...
Talar's user avatar
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0 votes
2 answers
165 views

Trying to drive the clock pulse of a counter by a NAND gate output but the counter misbehaves

I have connected the output (2Y) of the NAND gate to the clock pulse (CP0) input of the counter, but as soon as I send an input to the NAND gate the counter misbehaves; it does not count in sequence ...
Ashish Kumar's user avatar
0 votes
0 answers
62 views

CMOS logic gates | Number of Logic Gates issue

I came across this question for CMOS logic gates: Question - "Draw the schematic diagrams for CMOS logic-based implementations of f = a(b + c) + bc. Use minimum number of gates. Assume that all ...
Azure's user avatar
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0 votes
1 answer
225 views

What's the difference between normal read and fast read on the W25N01GVxxIG?

I noticed that there were two separate instructions to read data from the data buffer of the W25N01GVxxIG flash chip. There is Read Data(0x13) and Fast Read(0x0B), but their descriptions seem to be ...
Sagar Patil's user avatar
1 vote
0 answers
154 views

NAND circuit from boolean expression

What is the best way to convert following boolean expression to circuit based only on NOT, NAND gates? I already done OR, AND circuit. But what is the method to receive that?
Mr.Cheese's user avatar
0 votes
0 answers
633 views

Fan-Out Calculation on LTSpice

I need to find the fan-out of the circuit below. This is a Schmitt Trigger TTL NAND Gate. How can I exactly find the fan-out of the given circuit using LTSpice or calculate it theoretically?
Boffin's user avatar
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2 votes
3 answers
382 views

Intuition for building OR gate from NAND gates

The problem was to build an OR gate from NAND gates. I managed to do this in a kind of brute-force way just trying different variations, and finally got it but am feeling unsatisfied since I don't ...
sco's user avatar
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1 vote
0 answers
229 views

Memory Mapping Table

I am a begginer in the field of microcomputers and their architecture and recently I got an assignment with the following instructions: With the use of the mapping table find out which adresses in ...
Tibor Galambos's user avatar
0 votes
0 answers
94 views

Is there some way to differentiate between NAND and other flash types on a PCB?

Modern devices (smartphone, notebooks) often use some kind of flash for data storage. Depending on the vendor this can be emmc, ufs, nvme and maybe even plain old NAND. The problem is you can't really ...
inume's user avatar
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2 votes
1 answer
322 views

What does the "source-like" symbol mean in the first NMOS of the CMOS NAND gate?

I would assume that it means the source is not left floating if Q4 is off (boot-strapping ?).
A.H.Z's user avatar
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5 votes
5 answers
1k views

Boolean Logic - Realization with using only 4 NAND gates

I am currently preparing the next semester of my program at university and I am stuck at a question of the "Digital Circuits" class. Here is the task: [...] pump P1 runs when the fill-level ...
jesm86's user avatar
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0 votes
2 answers
364 views

Is a NAND flash chip better for power saving purposes as a micro SD card?

I know, they are technically the same, but from what I read, NAND flash chips can be controlled better like putting it into standby and waking it up in the matter of a few nanoseconds, which could be ...
Krauseler's user avatar
0 votes
2 answers
124 views

Generating random bits using two oscillators and a D Flip-Flop

I'm an electronic musician and computer science student I have been tinkering a lot lately with Arduino and analog ways of sound synthesis. Mainly I've been using 4093 ICs (NAND gates) to make ...
Catalina Cuellar's user avatar
-4 votes
2 answers
112 views

SR Flip Flop Latches

Which gate, NAND or NOR is a better choice for making SR Flip Flop latch? Please, provide the reason too.
Gnanabalan Gnanalosan's user avatar
0 votes
0 answers
192 views

Method to realize any function with 2 input NAND/NOR gate

I'm preparing for a competitive exam where often these type of questions are asked Find the minimum number of 2 input NAND gates required to implement the function F(A, B, C, D) = AB + ACD + BC’ ...
dshrikant's user avatar
0 votes
1 answer
985 views

How to find NAND logic with the help of full adder?

Obtain a NAND logic diagram of a single full-adder from the Boolean functions: C= xy+xz+yz S= C’(x+y+z)+xyz I didn't understand the question. What do I have to do here? Do I have to simplify the ...
Hoppo's user avatar
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0 votes
0 answers
152 views

How can I make this symmetric non-overlapping clock using digital Logic components?

How can I make a (dead-time) non overlapping symmetric clock like this with digital components such as inverters and NAND gates with 7 separate phases? The first photo is doctored to show what I want ...
Josh Girgis's user avatar
1 vote
2 answers
5k views

Why is the PMOS in NAND gate in Parallel and NMOS Series?

Why is the PMOS in Parallel, and the NMOS is in series?
Dugong98's user avatar
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0 votes
1 answer
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What NAND gate chips should I use to create a simple computer

I have been reading the bool 'The Elements of Computing Systems' and I have designed a circuit for the computer that will use 1232 NAND gates, which assuming that there are 4 on a chip, is 308 chips. ...
finlay morrison's user avatar
2 votes
2 answers
2k views

Multiple Switch Equation to NAND Only equation

I'm trying to convert a regular Boolean equation that has multiple inputs into a NAND only equation. My guess is that I'm supposed to convert using DeMorgan's law, but I'm not entirely sure how to do ...
GainzNerd's user avatar
  • 147
1 vote
3 answers
322 views

Implement \$AB \overline{C}+\overline{BC}\$ using only a maximum of three 3-input NAND gates only

I need help with this question, I am lost.
Jordan's user avatar
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0 votes
1 answer
60 views

Does a secure erase on a SSD with lots of free space cost less P/E cycles than an SSD that's almost full?

Doing an ATA Secure Erase on an SSD should reset all of the cells to factory condition, which results in a program/erase cycle on cells at least in blocks that contain data. On self-encrypting drives,...
Victor's user avatar
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