Questions tagged [nand]

Use this tag when referring to any circuit that uses NAND gate / NAND logic, or for asking questions relating to NAND gates.

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58 views

Confused about positive edge-triggered D flip-flop

I'm reading the book Digital Design and Computer Architecture. I don't understand this passage: This is a D flip-flop with active low asynchronous set and reset inputs. If S' and R' are both 1, the ...
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38 views

Is there a diagram or a graph that describes the regions of both transistors in the TTL circuit?

Can someone describe in what regions both transistors will be in this graph?
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67 views

Memory Mapping Table

I am a begginer in the field of microcomputers and their architecture and recently I got an assignment with the following instructions: With the use of the mapping table find out which adresses in ...
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182 views

How to find NAND logic with the help of full adder?

Obtain a NAND logic diagram of a single full-adder from the Boolean functions: C= xy+xz+yz S= C’(x+y+z)+xyz I didn't understand the question. What do I have to do here? Do I have to simplify the ...
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35 views

Is there some way to differentiate between NAND and other flash types on a PCB?

Modern devices (smartphone, notebooks) often use some kind of flash for data storage. Depending on the vendor this can be emmc, ufs, nvme and maybe even plain old NAND. The problem is you can't really ...
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62 views

What does the "source-like" symbol mean in the first NMOS of the CMOS NAND gate?

I would assume that it means the source is not left floating if Q4 is off (boot-strapping ?).
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991 views

Boolean Logic - Realization with using only 4 NAND gates

I am currently preparing the next semester of my program at university and I am stuck at a question of the "Digital Circuits" class. Here is the task: [...] pump P1 runs when the fill-level ...
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3answers
802 views

Properly simulating a NAND gate? (I'm building a computer in my computer)

I am about to embark on a project, enspired by Nand2Tetris (http://www.nand2tetris.org/), to fully simulate a computer, building the entire thing up from NAND gates. I want to simulate everything ...
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1k views

Minimum number of NAND gates to implement f(x,y,z,w)=x(y+zw)+yz'

As the title states, given a function \$f(x, y, z, w) = x.(y + z.w) + y.\bar{z}\$, what are the minimum number of NAND gates you need to implement f? My first attempt at a solution was to draw a kmap ...
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399 views

momentary switch latching circuit

I'm very new at all this and hope you will have patients with me, I'm trying to use this circuit diagram to turn a momentary switch into a latching switch, I though it would be straightforward but ...
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84 views

Is a NAND flash chip better for power saving purposes as a micro SD card?

I know, they are technically the same, but from what I read, NAND flash chips can be controlled better like putting it into standby and waking it up in the matter of a few nanoseconds, which could be ...
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82 views

Generating random bits using two oscillators and a D Flip-Flop

I'm an electronic musician and computer science student I have been tinkering a lot lately with Arduino and analog ways of sound synthesis. Mainly I've been using 4093 ICs (NAND gates) to make ...
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11k views

how can i build a 3-input OR gate using only 2-input NAND gates [closed]

How can i build the above circuit?I have to use the boolean algebra rules like de morgans law.I tried already to simplify the equation,but nothing correct yet
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SR Flip Flop Latches

Which gate, NAND or NOR is a better choice for making SR Flip Flop latch? Please, provide the reason too.
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Method to realize any function with 2 input NAND/NOR gate

I'm preparing for a competitive exam where often these type of questions are asked Find the minimum number of 2 input NAND gates required to implement the function F(A, B, C, D) = AB + ACD + BC’ ...
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412 views

Multiple Switch Equation to NAND Only equation

I'm trying to convert a regular Boolean equation that has multiple inputs into a NAND only equation. My guess is that I'm supposed to convert using DeMorgan's law, but I'm not entirely sure how to do ...
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51 views

How can I make this symmetric non-overlapping clock using digital Logic components?

How can I make a (dead-time) non overlapping symmetric clock like this with digital components such as inverters and NAND gates with 7 separate phases? The first photo is doctored to show what I want ...
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1k views

Why is the PMOS in NAND gate in Parallel and NMOS Series?

Why is the PMOS in Parallel, and the NMOS is in series?
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64 views

What NAND gate chips should I use to create a simple computer

I have been reading the bool 'The Elements of Computing Systems' and I have designed a circuit for the computer that will use 1232 NAND gates, which assuming that there are 4 on a chip, is 308 chips. ...
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194 views

Using NAND gates to construct OR/AND gates

I have this Boolean equation B'*C'*D' + A*C*D + C*D*E' and I was just wondering how to use nand gates to express this equation. With the schematic the inputs are NAND1 it is B'*C'*D' NAND ...
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145 views

Converting gates in XOR circuit to NAND gates

I have this XOR circuit: I tried to write it using only NAND gates and this was the furthest I got: According to my book, it should look like this: I did this: $$(x.y')+(x' . y) = ( (x. y')+(x' . y)...
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Nand gate is not working

I am trying to use a nand gate from a 4093BE chip with a digital sensor which is supposed to output 5 V when an obstruction is detected and 0 when not. I am setting both inputs of gate to the output ...
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How to build a 3-input NAND gate from 2-input NAND gates or a 3-input NOR gate from 2-input NOR gate?

For NAND, I am doing a truth table for it and then truth tables for all the possible combinations, but as you can see the process is very long and I am still yet to get an answer. Same goes for NOR ...
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46 views

Does a secure erase on a SSD with lots of free space cost less P/E cycles than an SSD that's almost full?

Doing an ATA Secure Erase on an SSD should reset all of the cells to factory condition, which results in a program/erase cycle on cells at least in blocks that contain data. On self-encrypting drives,...
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Realizing an XOR expression using NAND gates [duplicate]

I've been trying really hard to understand the construction of a logical circuit using only NAND while also trying to minimize the number of gates. The minimization of gates is what is really ...
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103 views

SN74LS26 2-input NAND gate. No output

I purchased SN74LS26N quadruple 2-input NAND Gates chips for my circuit. Before I insert any chip into circuit I test it on separate breadboard. So I did with this chip and I get NO output when my ...
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99 views

What happens when you nand the same input?

I am trying to conceptually understand what happens to the output of the second nand gate when input into the 1st nand gate are combinations 00, 01, 10, 11.
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136 views

Circuit using only NAND gates

I am starting to get beyond frustrated with gates and breadboards now in general because of this simple circuit (which is literally experiment #1 in my digital logic class). Using only NAND gates, ...
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1answer
33 views

Can I read programmed content inside any sort of non-volatile re-programmable memory device with Microscope, X-ray, etc.?

Non-volatile re-programmable memory like NAND flash, NOR flash, and etc. stores information in forms of electron charges and doesn't change in structural forms that can be inspected with X-ray or ...
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96 views

NAND flash pull ups

I am new to electronics, but always wanted to build my own devices and decided to start with simple usb flash drive as a first project. I found some reference designs by cypress and it confused me a ...
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110 views

Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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101 views

Digital electronics design

Our professor asked us to name the pins of the gates as below based on a chip pinout diagram he provided which includes only NAND and NOR but in the circuit diagram, there's a negative OR gate. Can ...
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1answer
59 views

Wear leveling and supply of voltage

Does anyone know if a NAND flash device (e.g. microSD) has to be continuously supplied with energy for its wear leveling algorithms work as designed? Or, if it doesn't matter if the device is (safely) ...
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555 views

File system to use with NAND Flash and 32 bit microcontroller

I am searching for a file system, suitable for NAND flash memory chips. Currently I use a Micron 256MB SPI NAND flash memory where I write and read raw sensors data but without a file system and ...
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1answer
59 views

Can't read an entire page at once (NAND flash)

I am working for quite a while now with a GD5F1GQ4UCYIG from GigaDevice. The goal is to dump the content of the flash. To do so I use a BusPirate. The NAND flash itself is still attached to the board,...
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1answer
593 views

TTL Logic Gate Resistor Values

I've been teaching myself the basics of circuits for the last few months and have been enjoying going into chip schematics. I'm trying to understand why the resistor values are as they are. For ...
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10k views

TTL NAND gate (totem pole) current and voltage analysis

I am working on a few practice problems for my course and I am unsure about my working throughout. hoping for some feedback and guidance from the community as it's not my strongest topic. Here is ...
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Is there a need for a third transistor in a NAND gate?

I was attempting to create my "own" NAND-gate S/R latch using NPN transistors (I know there are ICs available for that) From my own knowledge of how transistors work, I came up with this circuit for ...
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47 views

User controlled storage devices existence

Today's memory devices have a lot of logic embedded before data is actually written onto the NAND pages. An example could be wear levelling algorithm , FTL functionalities etc. The typical life of a ...
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146 views

Why is there no race around condition in NOR SR latch when S=R=0(initially)?

When the IC gets connected to the Vcc+, both the NOR gates get the input 0 and 0 (low) which yields the output 1. Now since both the outputs are again connected as one of the input to each of the NOR ...
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194 views

obsolete DTL chip substitution

I'm trying to substitute the obsolete NAND chip in this circuit (part of an audio synthesizer) with a standard CMOS one (for example CD4011). The original NAND chip is a DTL chip by Motorola, MC846. ...
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1answer
125 views

Output on Pass-transistor NAND gate lower than expected

I have an assignment to design an IC NAND gate, consisting og 2 NMOS-transistors and a designed inverter as seen in figure 1 and 2. But when measuring the output at Vout, we only get about 60% of the ...
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More Fun with the CD4093 IC as Schmitt Trigger Oscillator. Any practical difference between circuit version with "Enable" pin and Without?

I built two Schmitt trigger oscillator circuits using the CD4093BE IC from Texas Instruments. The CD4093 is a quad NAND gate with Schmitt trigger inputs. You can find the datasheet here: http://www....
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249 views

1 TTL IC -> inverter + 2-input NAND + 3-input NAND

I came across this question in my homework: Implement the following gates using only one TTL IC: one inverter, one 2-input NAND and one 3-input NAND. The type of IC they're talking about has 14 pins,...
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230 views

Can anyone help me to understand what these capacitors do in this design?

I have a circuit design makes a button latch on-off and drive a mosfet. When I energize the circuit Vout that drives thr mosfet is initially low. After pressing the button, the button state changes ...
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472 views

use minimum number of NAND gates to realize this boolean expression [closed]

How should I proceed to find the minimum number of 2 input NAND gates to realize this boolean expression. I am allowed to use both complemented and non-complemented inputs. $$F = X.Y + Y.Z + \...
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182 views

CD4011BE (DUAL INPUT NAND GATE) not working

I am using my CD4011BE NAND Gate IC. I connected a 9V battery in the 14th pin. And grounded the 7th pin. Then I provided input in the first 2 pins. I took a 330 ohm resistor from the third pin and ...
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401 views

Is there an intuitive reason for why NAND gate is a universal gate?

Now I know the maths and logic to figure out that every boolean function can be expressed using only AND and NOT gates, which in turn can be expressed using only NAND gate and hence every boolean ...
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Flash memory : What are blocks and pages from a physical standpoint?

I would like to know the link between the physical layout of NOR and NAND flash cells and the concept of blocks and pages. I would also like to know the exact reason for why erasure only happens in ...