Questions tagged [nand]

Use this tag when referring to any circuit that uses NAND gate / NAND logic, or for asking questions relating to NAND gates.

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File system to use with NAND Flash and 32 bit microcontroller

I am searching for a file system, suitable for NAND flash memory chips. Currently I use a Micron 256MB SPI NAND flash memory where I write and read raw sensors data but without a file system and ...
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141 views

Is there a need for a third transistor in a NAND gate?

I was attempting to create my "own" NAND-gate S/R latch using NPN transistors (I know there are ICs available for that) From my own knowledge of how transistors work, I came up with this circuit for ...
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206 views

Which pins are required when reading and writing NAND flash?

I plan on reading and probably writing NAND flash on some embedded devices or USB flash drives. I did not come across many examples for in circuit reading though I'd give that a try at first if ...
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1answer
109 views

Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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34 views

Method to realize any function with 2 input NAND/NOR gate

I'm preparing for a competitive exam where often these type of questions are asked Find the minimum number of 2 input NAND gates required to implement the function F(A, B, C, D) = AB + ACD + BC’ ...
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1answer
167 views

How to find NAND logic with the help of full adder?

Obtain a NAND logic diagram of a single full-adder from the Boolean functions: C= xy+xz+yz S= C’(x+y+z)+xyz I didn't understand the question. What do I have to do here? Do I have to simplify the ...
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48 views

How can I make this symmetric non-overlapping clock using digital Logic components?

How can I make a (dead-time) non overlapping symmetric clock like this with digital components such as inverters and NAND gates with 7 separate phases? The first photo is doctored to show what I want ...
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1answer
64 views

What NAND gate chips should I use to create a simple computer

I have been reading the bool 'The Elements of Computing Systems' and I have designed a circuit for the computer that will use 1232 NAND gates, which assuming that there are 4 on a chip, is 308 chips. ...
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65 views

Nand gate is not working

I am trying to use a nand gate from a 4093BE chip with a digital sensor which is supposed to output 5 V when an obstruction is detected and 0 when not. I am setting both inputs of gate to the output ...
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2answers
127 views

Circuit using only NAND gates

I am starting to get beyond frustrated with gates and breadboards now in general because of this simple circuit (which is literally experiment #1 in my digital logic class). Using only NAND gates, ...
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1answer
57 views

Wear leveling and supply of voltage

Does anyone know if a NAND flash device (e.g. microSD) has to be continuously supplied with energy for its wear leveling algorithms work as designed? Or, if it doesn't matter if the device is (safely) ...
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96 views

Acquire a "TIC" signal from a power meter

I'm trying to acquire the tic signal of a french power meter. From the datasheet available here of the TIC signal we can find out that the signal is (page 7/38): 6 Vrms +/- 10% at 50 kHz It comes ...
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1answer
62 views

How can i simulate this circuit to match with the truth table?

How can I simulate this NAND logic circuit to match the truth table?]2
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69 views

Writing unused areas of a page on a NAND flash

I'm working on a project based on the ESP32 that uses a NAND chip from the GD5F1 family (link to the datasheet). Sorry for the long question, but it's a bit convoluted, and it's driving me nuts for ...
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1answer
81 views

Alternative for adder out of NAND-gates

Recently I was experimenting with the NAND-gate representation of an adder circuit and tried to implemenent it without crossing wires. So I got this: The carry is negated, but when chaining two of ...
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1answer
187 views

Using NAND gates to construct OR/AND gates

I have this Boolean equation B'*C'*D' + A*C*D + C*D*E' and I was just wondering how to use nand gates to express this equation. With the schematic the inputs are NAND1 it is B'*C'*D' NAND ...
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77 views

Gate level implementation of JK flip flop using nand gates does not toggle

I have implemented Verilog code for a JK flip flop using gate level (nand gates). I have done the simulation in Questasim. The design diagram is attached below. <...
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1answer
447 views

How to build PIPO register

Ive got problem with simulating 8-bit register. Ive built register using eight D flip - flop. Every flip-flop was made with 5 NAND gates + 2 NAND gates for Preset. My problem is that register doesnt ...
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2answers
431 views

Using only NAND and NOT gates to represent a logic function that isn't an SOP/POS?

I understand that I should repreatedly use deMorgan's theorem until I am left only with NAND/NOT gates. This is easy when the starting function is an SOP/POS. However when it isn't, I get confused as ...
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1answer
304 views

TTL NAND logic circuit

how can find the maximum fan-out of the TTL-NAND gate using LTSpice ? i tried to solve problem by hand, but the problem how to find fan-out using ltspice