Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [nios-ii]

Nios II is a 32-bit embedded-processor architecture designed specifically for and implemented as a soft-core processor in the Altera family of CPLDs and FPGAs.

-2
votes
1answer
133 views

How do I fix “Nios2 software build tools for eclipse” build errors? [closed]

I have a Quartus Cyclone3 project with NIOS2 processor. I have noticed 3 errors while building the eclipse project, though I am pretty sure it should be working well. Description: make[1]: [public....
1
vote
1answer
88 views

FPGA NIOS II and RS-485

I am doing my first steps in designing an FPGA project with NIOS and RS-485 interface. I have looked through a bunch of tutorials and books, but haven't found useful info about how to add RS-485 ...
0
votes
0answers
216 views

How to #include files in other folders in Eclipse IDE?

Here is the directory structure of a project I have downloaded: The problem is that when I compile I keep getting fatal error message that say that the specific header file does not exist. For ...
0
votes
1answer
84 views

Can Nios II read addresses in increments of 1 or only increments of 4?

There is some confusion here. I think that the Nios II having 32 bit data bus. Therefore, it is not capable of individual byte addressing. Therefore, the address bus increases as 0, 4, 8 e.t.c and not ...
1
vote
1answer
294 views

How does one read a FIFO outside Qsys system using Nios II?

There is a FIFO block that has Avalon interface compatible with Qsys that can be used in Qsys systems. However, in my case there is an external block that generates data that is to be read by a Nios ...
4
votes
2answers
568 views

Busy-wait sleep function has incorrect timing on NIOS CPU

I have a Qsys system which includes a NIOS II/e CPU (which is the only master on the bus) and a 36kB chunk of 32-bit internal RAM. The RAM is configured to have the minimum read latency (which is 1 ...
1
vote
1answer
131 views

How to select line to a 1:4 demux in verliog from a NIOS II softprocessor

I am new to verilog. I'm using this 1:4 demux as described on this webpage (code supplied). 1:4 Demux verilog code My question is in relation to the select line. I have a soft processor NIOS II on ...
0
votes
1answer
1k views

verilog - altera fpga “error pin x has multiple drivers due to the non-tri-state driver”

I have a 32 bit parellel IO interface (PIO) defined in a NIOS II soft processor. It is for a 32 pin connector on a board. I instantiate the NIOS in a top level verilog module called ...
1
vote
1answer
70 views

fpga multiplexor - select line controlled by a soft processor

I have 5 pins coming into an FPGA (inputs). I have two different sets of 5 output pins. I want to select which set of output pins that I connect the input pins to. What kind of multiplexer is this ...
-2
votes
2answers
182 views

Can you call verilog code from a c program running on a soft processor on an FPGA

I have a soft NIOS II processor instantiated on an Altera FPGA. I have 4 JTAG pins connected from the FPGA to a FTDI chip (lets call them A1, A2, A3, A4). I have the JTAG pins from 2 MCUs connected to ...
0
votes
2answers
806 views

Can I run my Nios II from program in SRAM or SDRAM, how?

Is there a "standard" (Altera supported) method to run my Nios II from off chip memory like SRAM or SDRAM? Since the design is in prototype stages, it means that I am using JTAG for configuration and ...
-1
votes
1answer
347 views

How much RAM do I have for dynamic memory allocation in my Nios II [closed]

The program may be stored in on chip memory or off chip memory but like any processor, the processor RAM will be on chip. All dynamic memory allocation shall be carried out using this RAM. How do I ...
0
votes
1answer
43 views

Is there a way to have visibility of certain part of Nios II system memory for debug purpose?

To know what value exists at address X one may simply read it using IORD and then send it via JTAG UART to the PC. However, to simplify debug process, is there a way to have visibility of certain ...
0
votes
0answers
28 views

How to know what files to #include in a Nios II application?

In the hello world application created by the Nios II Eclipse IDE, it put in the #include "sys/alt_stdio.h". I am not sure why it is not just stdio.h and where does sys/ come from. In any case, as I ...
0
votes
1answer
102 views

Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?

I have tried Quartus 16.0 and 14.1. Both of them generate Nios II system that looks very awful as shown in the figure below. Is there any way to make it look better like the previous version as shown ...