Questions tagged [nios-ii]

Nios II is a 32-bit embedded-processor architecture designed specifically for and implemented as a soft-core processor in the Altera family of CPLDs and FPGAs.

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Quartus Prime Nios II software build tools error "Failed to execute: wsl dos2unix create-this-bsp"

I am using Quartus Prime Lite 21.1 and am trying to use the Nios II software build tools for Eclipse. When I try to create a project I get "Failed to execute: wsl dos2unix create-this-bsp; ./...
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Concatenating 2 memory block 32x64 to 32x128?

I'm building a simple basic system on NIOS II, practicing SoC. I wrote a memory block 32x64 as below: ...
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nios2-app-generate-makefile: command not found

I had Quartus version 18.1 (the last free version without requirement of WSL) but I found that it contains a bug which could cause an error I got during flashing program to FPGA so I tried to install ...
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How do I know if Nios II IORD is getting data from peripheral or cache?

For a Nios II system that has cache enabled, how do I know if the IORD is getting data from the actual peripheral or just reading the last value from cache? As far as I know, cache conflicts of this ...
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Nios2 - GDB Server Timeout

I am programming an Intel Nios2 softcore processor using VS Code and the available command line tools (Ubuntu Linux 18.04.6, Quartus 18.1). The FPGA is an Intel MAX10 device. Everything works fine ...
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How can I correct these Verilog syntax and declaration errors?

I am currently working on an Arduino to NIOS II Compiler that I am using on GitHub. I have provided a link to the compiler here: https://github.com/dimag0g/nios_duino. The issue I am having is that I ...
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I want to find out how many Nios processors are on the board that I am linked with using JTAG, how to do this?

I just want to test how many Nios II exist inside the Qsys system and if they are in reset or executing code. Can this be done via the Nios II terminal?
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Persistent RAM variables in NIOS II

I would like to define a C variable in RAM which can survive a CPU reset in NIOS II IDE. Something like __persistent in PIC world or ...
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Can Nios II custom instruction feature be used to create SIMD type instructions?

Nios II is all about customizing, the essence of a softcore. Custom instruction is an interesting feature of the Nios II. Custom instruction involves 2 inputs dataa and datab. Does this mean that it ...
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How do I fix "Nios2 software build tools for eclipse" build errors? [closed]

I have a Quartus Cyclone3 project with NIOS2 processor. I have noticed 3 errors while building the eclipse project, though I am pretty sure it should be working well. Description: make[1]: [public....
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FPGA NIOS II and RS-485

I am doing my first steps in designing an FPGA project with NIOS and RS-485 interface. I have looked through a bunch of tutorials and books, but haven't found useful info about how to add RS-485 ...
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How to #include files in other folders in Eclipse IDE?

Here is the directory structure of a project I have downloaded: The problem is that when I compile I keep getting fatal error message that say that the specific header file does not exist. For ...
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Can Nios II read addresses in increments of 1 or only increments of 4?

There is some confusion here. I think that the Nios II having 32 bit data bus. Therefore, it is not capable of individual byte addressing. Therefore, the address bus increases as 0, 4, 8 e.t.c and not ...
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How does one read a FIFO outside Qsys system using Nios II?

There is a FIFO block that has Avalon interface compatible with Qsys that can be used in Qsys systems. However, in my case there is an external block that generates data that is to be read by a Nios ...
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Busy-wait sleep function has incorrect timing on NIOS CPU

I have a Qsys system which includes a NIOS II/e CPU (which is the only master on the bus) and a 36kB chunk of 32-bit internal RAM. The RAM is configured to have the minimum read latency (which is 1 ...
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How to select line to a 1:4 demux in verliog from a NIOS II softprocessor

I am new to verilog. I'm using this 1:4 demux as described on this webpage (code supplied). 1:4 Demux verilog code My question is in relation to the select line. I have a soft processor NIOS II on ...
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verilog - altera fpga "error pin x has multiple drivers due to the non-tri-state driver"

I have a 32 bit parellel IO interface (PIO) defined in a NIOS II soft processor. It is for a 32 pin connector on a board. I instantiate the NIOS in a top level verilog module called ...
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fpga multiplexor - select line controlled by a soft processor

I have 5 pins coming into an FPGA (inputs). I have two different sets of 5 output pins. I want to select which set of output pins that I connect the input pins to. What kind of multiplexer is this ...
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Can you call verilog code from a c program running on a soft processor on an FPGA

I have a soft NIOS II processor instantiated on an Altera FPGA. I have 4 JTAG pins connected from the FPGA to a FTDI chip (lets call them A1, A2, A3, A4). I have the JTAG pins from 2 MCUs connected to ...
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Can I run my Nios II from program in SRAM or SDRAM, how?

Is there a "standard" (Altera supported) method to run my Nios II from off chip memory like SRAM or SDRAM? Since the design is in prototype stages, it means that I am using JTAG for configuration and ...
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How much RAM do I have for dynamic memory allocation in my Nios II [closed]

The program may be stored in on chip memory or off chip memory but like any processor, the processor RAM will be on chip. All dynamic memory allocation shall be carried out using this RAM. How do I ...
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Is there a way to have visibility of certain part of Nios II system memory for debug purpose?

To know what value exists at address X one may simply read it using IORD and then send it via JTAG UART to the PC. However, to simplify debug process, is there a way to have visibility of certain ...
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How to know what files to #include in a Nios II application?

In the hello world application created by the Nios II Eclipse IDE, it put in the #include "sys/alt_stdio.h". I am not sure why it is not just stdio.h and where does sys/ come from. In any case, as I ...
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Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?

I have tried Quartus 16.0 and 14.1. Both of them generate Nios II system that looks very awful as shown in the figure below. Is there any way to make it look better like the previous version as shown ...
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