Questions tagged [nmos]

A n-channel metal-oxide semiconductor (nMOS) transistor has n-type carriers in the channel. A positive voltage on the gate turns inverts the substrate (PWell) creating the channel and turning the device on. The term may also be used to describe logic circuits built around nMOS transistors.

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44 views

Additional V+ pin on ALD1106

I'm working with ALD1106 as part of a circuit I'm testing, but looking at the datasheet for the part, I'm confused by the addition of the V+ pin. It doesn't look like it's tied to anything in the pin ...
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Incorporating ALD1106 SPICE model in LTspice

I'm trying to incorporate a SPICE model of an NMOS IC, the ALD1106. I've used it before in class, but it's been so long that I've forgotten how to incorporate the files into LTspice in order to ...
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1answer
34 views

Deriving PU / PD given a sketch of a PMOS

For the PMOS given below I can derive the function f, such that f inverted in its variables corresponds to the expression of PMOS(f) and f inverted equals NMOS(f). For this specific problem I have ...
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Why would a Intel 8080 chip be destroyed if +12 V is connected before -5 V?

The Intel 8080 is a classic microprocessor released in 1974, fabricated using an enhancement-mode NMOS process, and shows various unique characteristics related to this process, such as the ...
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29 views

Find W/L and Vt of NMOS

I'm simply trying to find Vt and W/L for a given practice exam problem shown below: The solution is given as: Initially, I was trying to use the equation as shown in line 1 of the solution to ...
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58 views

Why nMOS transistors use 'Head' current source and pMOS transistors use 'Tail' current source as their load?

Here I am taking an example of common source configuration(refer figure). Generally head current source is used as load with nMOS and tail cuurent source with pMOS. Why can't be this other way around? ...
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4answers
104 views

high side switch using NMOS

I'd like to dim an ordinary 3-pin PC fan with a 3.3V-PWM at its 12V power supply pin. As I also need to measure the tachometer signal within a 3.3V logic level circuitry I'd like to switch the fan on ...
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63 views

2N7002 MOSFET gate voltage internally being pulled high, potentially dead

I am using the circuit below to switch a bi-latching relay once a wire is disconnected, i.e. to not switch as long as a voltage is present on the wire. After assembling on a PCB, on which there are ...
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48 views

Mosfet on or off

When do we say that a nMOS or pMOS is "on" or "off"? Are there any voltages across terminals we should be looking for?
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70 views

Mosfet Threshold Voltage

from MOS theory we know that, in case of a P substrate, a Gate-Bulk voltage higher than a certain threshold value creates an inversion layer, in this case made of negative charges. This is also ...
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1answer
102 views

Am I applying the KCL the right way? [closed]

Applying KCL at the node where I have drawn the currents in order to find Vin/Vs, I am not getting the correct answer which however I did obtain using the Voltage Divider. My question is, am I using ...
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20 views

Where do the electrons come from in nmos channel formation? [duplicate]

For a NMOS, when gate potential is increased from 0 to say 0.1V, the holes in substrate feel repulsion and moves away leaving negative ions behind. But what exactly happens when the gate potential ...
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32 views

Effective resistance of a NMOS

How do we calculate effective resistance of a NMOS, operating in linear region across drain and source?
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56 views

voltage divider driving PMOS with slow turn-off time

I have a voltage divider that is driving the gate of a high side PMOS switch. The voltage divider turns the PMOS on once the NMOS is turned on by a 5v logic controller. The PMOS turns on ...
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2answers
36 views

Contact on substrate of a MOSFET

Why do we want to have an ohmic contact on a substrate terminal of mosfet? What would happen if we used schottky contact instead?
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1answer
65 views

NMOS find relations between input and output voltage

Can I ask for DC analysis of the circuit to find relations between input and output voltage as shown in the picture ?? I know how to handle with MOSFET but I havent' done anything with NMOS.
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40 views

Voltage drop at gate of pmos (or nmos)

Sorry if this question has been asked before, I've tried looking through google and Stack Exchange and I can't seem to find the answer. Resistors on the gate (R3 on the picture) are usually in the K ...
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74 views

Mosfet pinchoff, why the n-channel moves towards source?

Suppose we have an NMOS transistor with \$V_{GS}\$ > \$V_T\$. When \$V_{DS}\$ is 0, the channel depth is uniform along the transistor. However, when we increase \$V_{DS}\$, the channel becomes deeper ...
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MOSFET switching on

I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
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2answers
82 views

Basic questions about output impedance of a logic inverter using an NMOS

I have drawn below an NMOS logic inverter and its equivalent circuit for HIGH state: 1- Why is this gate said to have high output impedance at HIGH state? Is that because of the open switch or ...
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41 views

Sourcing the correct N-Channel MOSFET

I'm new to using MOSFETs and I need to source one for a personal project of mine. I'm using an N-Channel FET to pull down a 12v (5mA) logic/signal line from logic level (3.3v). I've used an FQP30N06L ...
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Understanding PMOS's and NMOS's

The problem says solve assuming VI = 0, +2.5V, and -2.5V. I know that if VI = -2.5V the MOSFET's are in cutoff and that VDS = 0. and IDP and IDN will = 0, but would V0 also = 0? If VI = 0 the ...
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1answer
74 views

NMOS High Side switch circuit solving

I'm trying to get my head around the circuit theory behind the high side NMOS switch, here is the shematics: My question is not about whether this is a good or a bad way to make a high side switch (I ...
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how to fix output voltage of an NMOS switch with changing load characteristic?

In an NMOS low side switch the output voltage at drain depends on the operating point decided from the Id-Vds curve and load line. According to my understanding, for a low side switch with Vds ...
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130 views

What is the effect on propagation delay when we have a CMOS circuit with multiple transistors connected in series?

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of ...
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87 views

nanoPower comparator driving MOSFET not providing expected output

I built the following circuit to charge a large capacitor from a low power source before switching the load: simulate this circuit – Schematic created using CircuitLab MAX9064, MCH3484, ...
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55 views

Trying to have NMOSs in parallel while passing current through only one at a time

If I wanted to have a bias current I1 going through M1 or M2 and I want M1 to alternate between on off (M1 on/M2 off, M1 off/M2 on) would this work? I simulated this with spice and for the first ...
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168 views

ltspice: simple nmos circuit

I built up a circuit which did not work as expected. I reduced the problem to this circuit: I expect to have a current of ~2.4 A at gate voltages below 10 V, but actually the transistor does not ...
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47 views

differential amplifier and ac imput

hello im studying the differential amplifier from Sedra Smith and i have problem with the ac mode when the signal is differential (vid/2 and -vid/2) I know that in Nmos transistor the current flows ...
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CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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81 views

NMOS current flowing equally in both directions in SPICE simulation

I am trying to characterize this nmos on Xyce simulator (and trying to change its present Vthreshold) and am first DC sweeping the gate and measuring the current through the nmos. I run into this ...
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1answer
73 views

Suitable NMOS with 3.3V gate voltage to switch 12V 500mA

I've got a circuit board with a D2PAK NMOS pad that I need to find a mosfet that will work with a raspberry pi's 3.3V GPIO. This is the current one I'm using and it isn't working well. https://www....
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High voltage switching using N-FET

This is my first time designing a High voltage switch, as come up with some interesting thing that I want to ask about. My application needs to short out a signal line to HIGH, with a 3v3 signal from ...
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1answer
92 views

Working of NMOS as a capacitor

I came across instances where NMOS was used as a capacitor in analog circuits. This is done by shorting the drain and source. The drain/source acts as one terminal of the capacitor while gate acts as ...
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1answer
51 views

Simple NMOS simulation error. High voltage drop across the nmos when trying to make a MOSFET switch

I have this simple NMOS configuration in ltSpice. I would imagine that when V2 (Vg) goes high, Vds would go close to zero. But this simulation suggests that there is a very high voltage drop across ...
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1answer
127 views

Why does the PWM signals amplitude drop once connected to low-side n-mosfet switch?

I am applying a 3.3 V pwm signal to a circuit similar to the following (Credit: Olin Lathrop): I am using an IRLR024N N-MOSFET, which switches if i connect the gate to the 3V3 pin of my ...
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234 views

TSMC model for lt spice simulation [closed]

From where to download the tsmc model file for nmos(slow,fast,typical) and pmos (slow,fast,typical)?
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Simulating process variations

How to simulate Drain current vs Drain source voltage characteristics of a NMOS with respect to process variations in LT Spice?
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193 views

Difference between body, bulk and substrate?

I have a pretty fundamental question related MOSFET devices. I am confused about whether the terms body, bulk and substrate are all just names for the same thing or are there actually some differences ...
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67 views

My transistor used in a transistor amplifier does not get turned off with PWM based input

I am working on a project; driving a DC MOTOR using an NMOS MOSFET amplifier and Arduino PWM signal. My problem is my transistor amplfiler is always on when I vary the PWM input value from 0 to 255. ...
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1answer
74 views

MOSFET goes into saturation mode much later

I am using IRLML6346 NMOS in LTSpice. Its threshold voltage is Vt = 0.95V. I plotted the graph of Vds(voltage between drain and source) vs Ids(Current from drain to source) for different values of Vgs(...
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63 views

Common Source with Active Load

I'm trying to design this circuit using gm/Id method. I am already able to achieve the desired GBWP and Gain (this is just a simple example so I'm just trying to achieve both) but I'm having trouble ...
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1answer
55 views

Can I use TXB0104B bidirectional level shifters on the Intel 8085 NMOS CPU buses?

I want to connect an old Intel 8085 CPU to an FPGA board. The basic issue is that the 8085 works at 5V while the FPGA will not accept any voltage avobe 3.3V so I decided to use the TXB0104 / TXB0108 ...
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1answer
104 views

NMOS/PMOS Transit Frequency

I found this video which shows how to plot the transit frequency in Cadence Virtuoso. But on another site, instead of using c_gg, the capacitance used was c_gs+c_gd for the ft equation. Which is ...
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2answers
125 views

Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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1answer
56 views

Inversion Region

If one transistor in a circuit (say common source with active load) operate at the strong inversion region, should the rest of the transistor also operate on that same region? Or will it depend?
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81 views

Power NMOS used as voltage switch

I've designed a PCB schematic that uses a MOS device to switch one of the higher power rails. I've looked through the datasheets many times, and believe it should work, according to the Current-...
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2answers
2k views

Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
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1answer
84 views

Advantages/Disadvantages of high/low transconductance efficiency (gm/Id) of NMOS/PMOS

From here, it's said that a higher gm/Id results in lower current consumption (which is usually preferred in low power operation) But what other effects does a high gm/Id have? Will it have other ...
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115 views

NMOS/PMOS Saturation

If I recall correctly, saturation occurs if \$V_{GS}>V_{TH}\$ and \$V_{DS}>V_{Dsat}\$ for NMOS. But is there an upper limit for the voltage? Like, when does a transistor not saturate after ...