Questions tagged [nmos]

A n-channel metal-oxide semiconductor (nMOS) transistor has n-type carriers in the channel. A positive voltage on the gate turns inverts the substrate (PWell) creating the channel and turning the device on. The term may also be used to describe logic circuits built around nMOS transistors.

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Mimimum time required for an NMOS transistor to operate as a switch?

How do I calculate the minimum time required for an NMOS transistor to work properly as a switch i.e. in the triode region? When the time period is very narrow, the switch might not turn on and our ...
7 votes
2 answers
273 views

What problem is solved by using a PMOS for reverse polarity protection instead of an NMOS?

Many resources suggest the use of a PMOS for reverse polarity protection instead of a diode, as it decreases losses. However, the characterstics of an NMOS are better than a PMOS, so why is using it ...
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1 answer
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Variation of MOSFETs with same W/L ratio

In MOSFET devices (let's say NMOS for this example), I know that the drain current has a formula: $$Id=\frac{\mu nC_{ox} }{2}\cdot \frac{W}{L}(V_{GS}-V_{th})^2(1+\lambda V_{DS})$$ For this circuit: I ...
1 vote
1 answer
36 views

Will the saturation current through one of these NMOS circuits always be greater than the other?

Is there a definitive way to know for all cases if an NMOS would have a greater saturation current if a resistor R is connected to 1) the drain side or 2) the source side? The assumption is that the ...
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29 views

How can I properly terminate an unused gate driver channel?

I have a circuit where I need only one MOSFET to be controlled but I have a dual channel gate driver capable of driving both high and low side MOSFET. I only need the low side channel for the ...
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1 answer
27 views

No DC convergence issue

I am simulating a circuit consists of a clock, a NMOS, and a D flipflop. I wonder why it gave me the error no DC convergence? How should I fix it?
2 votes
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ADS simulation error when inputting a clock in to a D flip-flop through an NMOS switch

A NMOS gate controls when the clock signal is fed into the clock of the D flip-flop. Below is the NMOS gate schematic and simulation. As we can see, the Vsquare only goes through the NMOS when the ...
1 vote
1 answer
48 views

What is N-diffusion in NMOS?

A NMOS contains source, drain, and gate. Under the source and drain contains N+ implantations and under the gate is a polysilicon layer with the P substrate beneath it: But I heard from a VLSI ...
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5 votes
4 answers
327 views

Low-side NMOS switch circuit

I built this circuit trying to learn how to drive a single HY3912W MOSFET. In the simulator, it acts as I expect. I built it. When I applied 6V to VAG and 5V for 1-second pulse to PWM every time the ...
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1 answer
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Optocoupler + MOSFET PWM amplifier timing issue

I want to drive a 12V, 1.5A valve from a microprocessor and also provide some isolation. The MCU outputs 3.3V logic, and I have this output going into a common source amp & also have a resistor in ...
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1 answer
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How does an NMOS transistor enter the triode region?

in my book it states that a transistor is in the triode mode when the gate to drain voltage is greater than the threshold voltage or equivalently when the drain to source voltage is less than the ...
3 votes
1 answer
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NMOS level 8 Ltspice model of 2SK4177

After downloading a model from https://www.onsemi.com/design/resources/technical-documentation?rpn=2SK4177, I deleted everything apart from what was between .MODEL and ), so I ended up with a xxx.txt ...
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1 answer
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N-MOSFET cannot fully turn off when using with voltage divider

I am using an N-channel MOSFET to control 12 V for my voltage divider. The output voltage of the voltage divider is connected to a 24-bit ADC module (ADS1220) for calculating back the resistance of ...
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-1 votes
1 answer
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Ensuring N-MOS is in triode region (high side switching)

I'm confused as how to use the n-MOS as a high side switch. I understand that the Vgs should be higher than Vdd enough to drive the FET into triode region (whether by means of a charge pump or gate ...
1 vote
1 answer
101 views

High side n-MOS driver without charge pump

I couldn't find details of this circuit configuration in an internet search. Most online results are about P-MOSFET in high side path or N-channel MOSFET with charge-pump/IC based driver. simulate ...
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NMOS IV characteristics turned out to be different with same configuration

I am ploting the IV characteristics of the NMOS. Here I sweep the Vgate and the VDS. note that the Vdc=-Vg has a minus sign, so Vg is actually positive. The only difference between the 2 setup is that ...
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Why is that the nmos and pmos in parallel "compensate each other"?

Why is that the nmos and pmos in parallel "compensate each other"? I use the simulation and found both current through nmos and pmos goes up if voltage across drain and source goes up.
7 votes
2 answers
911 views

Why do we need transmission gate for XOR (transistor level design)?

The following image shows a 6-transistor XOR circuit. But I don't know why the last 2 gates are needed at all, the circuit can be simplified to: Is there anything that prevents us from using the ...
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0 answers
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NMOS in ADS for proper simulation

How do I simulate a proper NMOS in ADS? I just given the width and length of the NMOS. what else are the parameters I need to provide?
1 vote
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92 views

Calculating capacitance in a MOS capacitor

A \$MOS\$ capacitor with \$t_{ox}=10nm\$ has an \$n^{+}\$ polysilicon gate electrode and an \$n\$-type substrate with doping concentration \$ N_D=10^{15}/cm^3\$ . Given: \$V_T=kT/q=26mV\$, \$\...
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2 answers
90 views

Could we use holes in an NMOS?

In an NMOS we have a p-substrate, and we use a positive voltage to attract negative charge "to the top". But could we have used negative charge to attract holes instead and gotten a "...
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3 answers
103 views

Water level indicator using CMOS inverter

I want to build the below circuit. The circuit has three levels to indicate water. low->o/p LED. Medium->O/P LED. High->O/P LED + Buzzer. Each level has two types of MOSFET; they work as CMOS ...
10 votes
5 answers
320 views

MOSFET failure in a high power AC-DC SMPS buck converter

I've made a AC-DC step down buck converter that converts 220 VAC to a variable 45 to 70 VDC at 5 to 10 A to charge a Li-Ion battery. I'm currently using ESP32 to drive a MOSFET driver (IR2110) to ...
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-1 votes
2 answers
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How do you go from gate level to transistor level?

Is there a good method to go from circuit at gate level or truth table to transistor level, other than trial and error? I have an example here to illustate what I am asking. We have the function \$X=(...
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How does the CMOS Schmitt trigger work

I have some questions on how the schmitt trigger works. Assuming we start with low Vin hence Vout is high. It means that M1 is ON thus the source of M2 is conducting Vdd hence M2 is On as well. ...
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1 vote
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Why choose pmos over nmos

In the attached schematic, there are two branches. The branch on the left has a pmos + nmos transistor. The branch on the right has two nmos transistors. The sizes of the devices were selected such ...
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2 answers
68 views

Characterizing "quadratic current" in an NMOS

I'm designing an integrated circuit where a series of NMOS with their sources tied to GND and their drains tied together work as parallel current sources. The total added current \$I_D\$ that I'd like ...
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1 answer
158 views

N-Channel MOSFET with source not connected

I recently saw a circuit that left the NMOS's source open without connecting to any terminal. Gate: A pull-up 10 kΩ resistor to 3.3 V. Drain: A pull-up 10 kΩ resistor to 3.3 V. Source: Nothing ...
-1 votes
2 answers
246 views

NMOS as a switch [closed]

I'm doing some simulation with nmos transistor, which supposed to act like a switch according to this picture: but after doing the simulation, I get these results: I don't understand why the output ...
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1 answer
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PMOS/NMOS current direction and digital logic

What happens when the PMOS source is connected to negative Vcc (-Vcc). What I understand is that when the gate voltage is <=0 then the drain-source is connected. Normally I would expect current to ...
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1 answer
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Is an NMOS device symmetrical with regard to its D and S pins? [duplicate]

Can D and S be swapped? (Assuming the body is not internally connected to S.) The structure of a MOSFET is totally symmetric. Even the LTspice simulation shows that it can be swapped. Does this ...
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1 vote
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How is common source NMOS stage with active current load realized in practice?

In a well known book about CMOS circuit design (Design of Analog CMOS Integrated Circuits) I found this example about a cascode stage with current source load. The basic idea is, to replace the drain ...
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1 vote
1 answer
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What are the limitations of AC coupling a MOSFET gate?

I came up with this AC coupled half bridge for high positive and negative voltage output with logic level control that I cannot find in any resources about (probably due to wrong search terms): It ...
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NMOS Cascode Logic

I have following problem and I ask you ,if possible, any help to resolve it. Size the following circuit so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load ...
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0 answers
43 views

Using NMOSFET for driving negative voltage

I want to use NMOSFEts for driving negative voltage. Is it possible to use it?
1 vote
2 answers
287 views

How to determine which terminal of a MOSFET is source, drain or gate [duplicate]

I am a student and for my next exam, as part of the tasks, I need to identify which terminals (pins) of P and N type mosfet are gate, source and drain. I have an example photo here, but if possible, I ...
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1 answer
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How to do NMOS modeling analysis in Spice

Here is my circuit in Spice: I want to do a simple analysis of the NMOS like this: What kind of command should I use?
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Analyzing circuit that cascades a pseudo NMOS inverter with a CMOS inverter

I have simulated this circuit in LTSPICE and it seems that the output is only High for A = 0 and B = 0. In other words, the circuit behaves similar to a NOR gate. However, I'm having trouble analyzing ...
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To turn a ratioed circuit into non-ratioed circuit, what should be the transistor sizes for proper operation of this circuit?

The circuit is at the bottom. I know it is a ratioed circuit however, how can I convert it to a non-ratioed circuit without adding two more PMOS transistors between Vdd and the other PMOSs. Also, what ...
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0 votes
2 answers
49 views

Separating power ground from control ground to exceed NMOS threshold voltage

I'm a novice circuit designer looking to create a high voltage source follower NMOS circuit. I originally planned to use a Teensy digital I/O pin as the gate control signal, so when the Teensy ...
3 votes
2 answers
328 views

Intrinsic gain of NMOS

In Razabi's Design of Analog CMOS Integrated Circuits textbook, the example 3.2 asks for the small signal voltage gain of the circuit below: He explains that since the current source I1 introduces an ...
2 votes
3 answers
303 views

D2PAK 2-pin NMOS?

I was looking up high-voltage NMOSs on DigiKey and found this entry for model STB12NM60N. However, it appears to be a two-pin NMOS (at least, I'm not sure how that tab connects to anything). Based on ...
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1 answer
98 views

Power switch PMOS controlled by button or Microcontroller (or both, with an OR circuit)

I´m trying to design an analog circuit to use a push button to turn on an MCU and then use it the same push button to change modes. A "one push button circuit". To achieve that, I used a ...
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1 answer
660 views

N-MOSFET and NPN latching switch

I've seen many latching circuits through searching and reading some simple circuits. Most use NPN+PNP combination, some bistable ones use two NPNs, some use DPDT relays. Is the following circuit going ...
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1 answer
112 views

Driving a Peltier Module via N-channel MOSFET H-Bridge

I'm working on a circuit to control a heating/cooling element (Peltier module) using an H-bridge. I'm using FDP8447L for that purpose. My Peltier is rated for 6 amps current and 15.4 Volts. The gate ...
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1 answer
85 views

Will this work for power path?

My goal is to disconnect the battery while the device is connected to USB Input. However when the device is disconnected from USB power, the battery will be connected to the system load. I am using ...
1 vote
3 answers
104 views

LED indicator controlled by MOSFET

I was just looking at a reference design and I can't see how this simple circuit makes any sense: It uses an EVERLIGHT LED and an NTZD3154N dual-transistor: I couldn't find the operation point of ...
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1 vote
1 answer
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finding inverting vs non inverting functions

So Im learning cmos systems and Im struggling with the pmos and nmos part of it. So for example given F=minterms(m0,m1,m2...) I can do the kmap and get the function no problem but how do I know if ...
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1 answer
58 views

VTC curve of cmos when Id does not saturate [closed]

For transistors, if the Id does not saturate at the saturation region (nmos: Vds>Vsg-Vt, pmos: Vsd>Vgs-|Vt|), but follow a linear relationship. How will the inverter VTC curve change? I am ...
1 vote
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CMOS Transmission Gate Body Bias in 74HC4052

Page 2 of the 74HC4052 data sheet shows a diagram of a transmission gate. I'm curious about the way the body of the NMOS transistors is biased. It looks like when the t-gate is off, the body is ...
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