Questions tagged [nmos]

A n-channel metal-oxide semiconductor (nMOS) transistor has n-type carriers in the channel. A positive voltage on the gate turns inverts the substrate (PWell) creating the channel and turning the device on. The term may also be used to describe logic circuits built around nMOS transistors.

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84 views

Am i applying the KCL the right way?

Applying KCl at the node where I have drawn the currents in order to find Vin/Vs, I am not getting the correct answer which however I did obtain using the Voltage Divider. My question is, am I using ...
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Where do the electrons come from in nmos channel formation? [duplicate]

For a NMOS, when gate potential is increased from 0 to say 0.1V, the holes in substrate feel repulsion and moves away leaving negative ions behind. But what exactly happens when the gate potential ...
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25 views

Effective resistance of a NMOS

How do we calculate effective resistance of a NMOS, operating in linear region across drain and source?
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54 views

voltage divider driving PMOS with slow turn-off time

I have a voltage divider that is driving the gate of a high side PMOS switch. The voltage divider turns the PMOS on once the NMOS is turned on by a 5v logic controller. The PMOS turns on ...
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36 views

Contact on substrate of a MOSFET

Why do we want to have an ohmic contact on a substrate terminal of mosfet? What would happen if we used schottky contact instead?
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64 views

NMOS find relations between input and output voltage

Can I ask for DC analysis of the circuit to find relations between input and output voltage as shown in the picture ?? I know how to handle with MOSFET but I havent' done anything with NMOS.
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Voltage drop at gate of pmos (or nmos)

Sorry if this question has been asked before, I've tried looking through google and Stack Exchange and I can't seem to find the answer. Resistors on the gate (R3 on the picture) are usually in the K ...
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58 views

Mosfet pinchoff, why the n-channel moves towards source?

Suppose we have an NMOS transistor with VGS> VT. When VDS is 0, the channel depth is uniform along the transistor. However, when we increase VDS, the channel becames deeper near the source and ...
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MOSFET switching on

I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
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Basic questions about output impedance of a logic inverter using an NMOS

I have drawn below an NMOS logic inverter and its equivalent circuit for HIGH state: 1- Why is this gate said to have high output impedance at HIGH state? Is that because of the open switch or ...
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Sourcing the correct N-Channel MOSFET

I'm new to using MOSFETs and I need to source one for a personal project of mine. I'm using an N-Channel FET to pull down a 12v (5mA) logic/signal line from logic level (3.3v). I've used an FQP30N06L ...
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Understanding PMOS's and NMOS's

The problem says solve assuming VI = 0, +2.5V, and -2.5V. I know that if VI = -2.5V the MOSFET's are in cutoff and that VDS = 0. and IDP and IDN will = 0, but would V0 also = 0? If VI = 0 the ...
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NMOS High Side switch circuit solving

I'm trying to get my head around the circuit theory behind the high side NMOS switch, here is the shematics: My question is not about whether this is a good or a bad way to make a high side switch (I ...
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how to fix output voltage of an NMOS switch with changing load characteristic?

In an NMOS low side switch the output voltage at drain depends on the operating point decided from the Id-Vds curve and load line. According to my understanding, for a low side switch with Vds ...
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73 views

What is the effect on propagation delay when we have a CMOS circuit with multiple transistors connected in series?

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of ...
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nanoPower comparator driving MOSFET not providing expected output

I built the following circuit to charge a large capacitor from a low power source before switching the load: simulate this circuit – Schematic created using CircuitLab MAX9064, MCH3484, ...
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55 views

Trying to have NMOSs in parallel while passing current through only one at a time

If I wanted to have a bias current I1 going through M1 or M2 and I want M1 to alternate between on off (M1 on/M2 off, M1 off/M2 on) would this work? I simulated this with spice and for the first ...
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ltspice: simple nmos circuit

I built up a circuit which did not work as expected. I reduced the problem to this circuit: I expect to have a current of ~2.4 A at gate voltages below 10 V, but actually the transistor does not ...
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differential amplifier and ac imput

hello im studying the differential amplifier from Sedra Smith and i have problem with the ac mode when the signal is differential (vid/2 and -vid/2) I know that in Nmos transistor the current flows ...
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CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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NMOS current flowing equally in both directions in SPICE simulation

I am trying to characterize this nmos on Xyce simulator (and trying to change its present Vthreshold) and am first DC sweeping the gate and measuring the current through the nmos. I run into this ...
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67 views

Suitable NMOS with 3.3V gate voltage to switch 12V 500mA

I've got a circuit board with a D2PAK NMOS pad that I need to find a mosfet that will work with a raspberry pi's 3.3V GPIO. This is the current one I'm using and it isn't working well. https://www....
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64 views

High voltage switching using N-FET

This is my first time designing a High voltage switch, as come up with some interesting thing that I want to ask about. My application needs to short out a signal line to HIGH, with a 3v3 signal from ...
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76 views

Working of NMOS as a capacitor

I came across instances where NMOS was used as a capacitor in analog circuits. This is done by shorting the drain and source. The drain/source acts as one terminal of the capacitor while gate acts as ...
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Simple NMOS simulation error. High voltage drop across the nmos when trying to make a MOSFET switch

I have this simple NMOS configuration in ltSpice. I would imagine that when V2 (Vg) goes high, Vds would go close to zero. But this simulation suggests that there is a very high voltage drop across ...
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115 views

Why does the PWM signals amplitude drop once connected to low-side n-mosfet switch?

I am applying a 3.3 V pwm signal to a circuit similar to the following (Credit: Olin Lathrop): I am using an IRLR024N N-MOSFET, which switches if i connect the gate to the 3V3 pin of my ...
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TSMC model for lt spice simulation [closed]

From where to download the tsmc model file for nmos(slow,fast,typical) and pmos (slow,fast,typical)?
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Simulating process variations

How to simulate Drain current vs Drain source voltage characteristics of a NMOS with respect to process variations in LT Spice?
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Difference between body, bulk and substrate?

I have a pretty fundamental question related MOSFET devices. I am confused about whether the terms body, bulk and substrate are all just names for the same thing or are there actually some differences ...
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63 views

My transistor used in a transistor amplifier does not get turned off with PWM based input

I am working on a project; driving a DC MOTOR using an NMOS MOSFET amplifier and Arduino PWM signal. My problem is my transistor amplfiler is always on when I vary the PWM input value from 0 to 255. ...
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MOSFET goes into saturation mode much later

I am using IRLML6346 NMOS in LTSpice. Its threshold voltage is Vt = 0.95V. I plotted the graph of Vds(voltage between drain and source) vs Ids(Current from drain to source) for different values of Vgs(...
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Common Source with Active Load

I'm trying to design this circuit using gm/Id method. I am already able to achieve the desired GBWP and Gain (this is just a simple example so I'm just trying to achieve both) but I'm having trouble ...
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Can I use TXB0104B bidirectional level shifters on the Intel 8085 NMOS CPU buses?

I want to connect an old Intel 8085 CPU to an FPGA board. The basic issue is that the 8085 works at 5V while the FPGA will not accept any voltage avobe 3.3V so I decided to use the TXB0104 / TXB0108 ...
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NMOS/PMOS Transit Frequency

I found this video which shows how to plot the transit frequency in Cadence Virtuoso. But on another site, instead of using c_gg, the capacitance used was c_gs+c_gd for the ft equation. Which is ...
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Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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52 views

Inversion Region

If one transistor in a circuit (say common source with active load) operate at the strong inversion region, should the rest of the transistor also operate on that same region? Or will it depend?
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Power NMOS used as voltage switch

I've designed a PCB schematic that uses a MOS device to switch one of the higher power rails. I've looked through the datasheets many times, and believe it should work, according to the Current-...
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Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
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Advantages/Disadvantages of high/low transconductance efficiency (gm/Id) of NMOS/PMOS

From here, it's said that a higher gm/Id results in lower current consumption (which is usually preferred in low power operation) But what other effects does a high gm/Id have? Will it have other ...
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107 views

NMOS/PMOS Saturation

If I recall correctly, saturation occurs if \$V_{GS}>V_{TH}\$ and \$V_{DS}>V_{Dsat}\$ for NMOS. But is there an upper limit for the voltage? Like, when does a transistor not saturate after ...
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103 views

Weird Current Mirror

I just encountered this circuit and I'm a bit confused by it I see that it's an NMOS current mirror. At first I thought it's a cascode current mirror due to M3 on the right but it isn't. I have two ...
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Nmos trigerring in 4-20mA converter

Here is the circuit I am trying to understand: It comes from the following application note from LT: https://www.analog.com/media/en/technical-documentation/technical-articles/D61_EN-Convert.pdf I ...
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NMOS bidirectional variable resistor: How to increase body diode barrier potential?

I want to use an NMOS as a variable input resistor to an inverting amplifier. The source is connected to virtual ground and the drain is connected to the input. I need to accomodate both positive and ...
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Maximum mid-band gain of s.s. model MOSFET amplifier?

Schematics I need to find the maximum possible gain for this NMOS cascode circuit. Here is the s.s. model: Work I used nodal-matrix analysis (basis is KCL) to find the gain (\$A_v\$): $$ \...
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55 views

MOSFET Drain vs Source Pads

I know this has been asked a few times already, but if we disregard the body diode, or say we tie the body to a low enough voltage that it wouldn't forward bias those diodes, then are modern FETs ...
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173 views

Why does a MOSFET enter saturation?

From all my browsing, it has become clear that as drain-source voltage increases, we eventually reach saturation. Mathematically, Vds>Vgs-Vt is the condition we look at. But when I try to understand ...
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92 views

Ambiguous symbol [duplicate]

Does anybody know what this symbol presents?
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Schematic for input protection with NMOS? Does this really work?

I was reading an old schematic and found this and sketched it up; (see box in image "Some kind of protection") The closest thing to this schematic that I've been able to find, that could have briefly ...
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Mosfet biasing doubt

What will be the gain of circuit 1) We dont include channel length modulation? 2) we include channel length modulation? If we include channel length modulation will the gain be 1? as vds should ...
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243 views

why is the feedback or gate resistance RG necessary?

Here the large feedback resistance RG interposed between gate and drain of the NMOS (usually in the megohm range) forces the dc voltage at the gate to be equal to that at the drain (because IG = 0). ...