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Questions tagged [nmos]

A n-channel metal-oxide semiconductor (nMOS) transistor has n-type carriers in the channel. A positive voltage on the gate turns inverts the substrate (PWell) creating the channel and turning the device on. The term may also be used to describe logic circuits built around nMOS transistors.

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TSMC model for lt spice simulation [on hold]

From where to download the tsmc model file for nmos(slow,fast,typical) and pmos (slow,fast,typical)?
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18 views

Simulating process variations

How to simulate Drain current vs Drain source voltage characteristics of a NMOS with respect to process variations in LT Spice?
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17 views

Difference between body, bulk and substrate?

I have a pretty fundamental question related MOSFET devices. I am confused about whether the terms body, bulk and substrate are all just names for the same thing or are there actually some differences ...
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42 views

My transistor used in a transistor amplifier does not get turned off with PWM based input

I am working on a project; driving a DC MOTOR using an NMOS MOSFET amplifier and Arduino PWM signal. My problem is my transistor amplfiler is always on when I vary the PWM input value from 0 to 255. ...
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1answer
38 views

MOSFET goes into saturation mode much later

I am using IRLML6346 NMOS in LTSpice. Its threshold voltage is Vt = 0.95V. I plotted the graph of Vds(voltage between drain and source) vs Ids(Current from drain to source) for different values of Vgs(...
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0answers
38 views

2N7000 Level Shifter: High Voltage Peak on Low Voltage Side

On the internet I saw, that a lot of people use the 2N7000 to realize a level shifter from 5V to 3V3 and vice versa. Firing up the simulator of my choice I saw, that there is a capacitance somewhere, ...
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18 views

Common Source with Active Load

I'm trying to design this circuit using gm/Id method. I am already able to achieve the desired GBWP and Gain (this is just a simple example so I'm just trying to achieve both) but I'm having trouble ...
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1answer
32 views

Can I use TXB0104B bidirectional level shifters on the Intel 8085 NMOS CPU buses?

I want to connect an old Intel 8085 CPU to an FPGA board. The basic issue is that the 8085 works at 5V while the FPGA will not accept any voltage avobe 3.3V so I decided to use the TXB0104 / TXB0108 ...
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1answer
29 views

NMOS/PMOS Transit Frequency

I found this video which shows how to plot the transit frequency in Cadence Virtuoso. But on another site, instead of using c_gg, the capacitance used was c_gs+c_gd for the ft equation. Which is ...
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2answers
51 views

Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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1answer
35 views

Inversion Region

If one transistor in a circuit (say common source with active load) operate at the strong inversion region, should the rest of the transistor also operate on that same region? Or will it depend?
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5answers
72 views

Power NMOS used as voltage switch

I've designed a PCB schematic that uses a MOS device to switch one of the higher power rails. I've looked through the datasheets many times, and believe it should work, according to the Current-...
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2answers
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Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
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1answer
29 views

Advantages/Disadvantages of high/low transconductance efficiency (gm/Id) of NMOS/PMOS

From here, it's said that a higher gm/Id results in lower current consumption (which is usually preferred in low power operation) But what other effects does a high gm/Id have? Will it have other ...
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34 views

NMOS problem consisting of Vtn, Vgs, Vds

Given a Vtn of 2.1 Volts and a desired Vds(V drain) of 5 Volts, How would I come up with the R and Vgs values? I know the Vgs must be greater than the Vtn for the NMOS to turn on so do I just pick a ...
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Clarifications on Intrinsic Gain

I found this here while searching for questions regarding intrinsic gain but I'm still quite confused and the links given were dead. My questions are: Is intrinsic gain the maximum gain of a ...
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1answer
38 views

NMOS/PMOS Saturation

If I recall correctly, saturation occurs if \$V_{GS}>V_{TH}\$ and \$V_{DS}>V_{Dsat}\$ for NMOS. But is there an upper limit for the voltage? Like, when does a transistor not saturate after ...
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2answers
87 views

Weird Current Mirror

I just encountered this circuit and I'm a bit confused by it I see that it's an NMOS current mirror. At first I thought it's a cascode current mirror due to M3 on the right but it isn't. I have two ...
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A question on MOSFETS with gates tied together

I was randomly reading about a fact that when the gate of one n-channel MOSFET is connected to the gate of another, one NMOS must be in linear region of operation and the other in saturation. Also, ...
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2answers
34 views

Nmos trigerring in 4-20mA converter

Here is the circuit I am trying to understand: It comes from the following application note from LT: https://www.analog.com/media/en/technical-documentation/technical-articles/D61_EN-Convert.pdf I ...
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0answers
39 views

NMOS bidirectional variable resistor: How to increase body diode barrier potential?

I want to use an NMOS as a variable input resistor to an inverting amplifier. The source is connected to virtual ground and the drain is connected to the input. I need to accomodate both positive and ...
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0answers
35 views

Maximum mid-band gain of s.s. model MOSFET amplifier?

Schematics I need to find the maximum possible gain for this NMOS cascode circuit. Here is the s.s. model: Work I used nodal-matrix analysis (basis is KCL) to find the gain (\$A_v\$): $$ \...
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0answers
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How to improve this circuit to open / close 24V power rail?

I have thought to use the following circuit to control the power of a subcircuit. The control is done through a GPIO pin of a microcontroller (ATMEGA328P). I would like to know if you see any serious ...
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2answers
48 views

MOSFET Drain vs Source Pads

I know this has been asked a few times already, but if we disregard the body diode, or say we tie the body to a low enough voltage that it wouldn't forward bias those diodes, then are modern FETs ...
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1answer
101 views

Why does a MOSFET enter saturation?

From all my browsing, it has become clear that as drain-source voltage increases, we eventually reach saturation. Mathematically, Vds>Vgs-Vt is the condition we look at. But when I try to understand ...
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3answers
77 views

Ambiguous symbol [duplicate]

Does anybody know what this symbol presents?
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1answer
79 views

Schematic for input protection with NMOS? Does this really work?

I was reading an old schematic and found this and sketched it up; (see box in image "Some kind of protection") The closest thing to this schematic that I've been able to find, that could have briefly ...
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2answers
54 views

Mosfet biasing doubt

What will be the gain of circuit 1) We dont include channel length modulation? 2) we include channel length modulation? If we include channel length modulation will the gain be 1? as vds should ...
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4answers
103 views

why is the feedback or gate resistance RG necessary?

Here the large feedback resistance RG interposed between gate and drain of the NMOS (usually in the megohm range) forces the dc voltage at the gate to be equal to that at the drain (because IG = 0). ...
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2answers
72 views

How does a common gate NPN mosfet turn on if the gate is grounded? [closed]

For a NMOS to turn on the Gate to Source potential diff has to be greater than the threshold voltage. But if the gate is grounded in the CG Mode, plus for a NMOS MOS the threshold voltage is positive, ...
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1answer
99 views

Why is the input voltage of transistors in the CMOS circuit set to Vdd when calculating the equivalent resistance?

When deriving the equivalent resistance formula of NMOS inverter the graph which is used in derivation is as shown: $$R_{eq} = \frac{1}{-V_{dd}/2} \int_{V_{dd}}^{V_{dd}/2} \frac{V}{I_{Dsat}(1+\...
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0answers
29 views

determine the cutoff frequency of a nMOS in common gate with gate resistance

I have to determine the upper cutoff frequency of this circuit. I absolutely mustn't use the laplace domain because it's too time consuming so not compatible with the time I have at the exam. A rapid ...
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234 views

How can I design a 12V DC UPS circuit using NMOS?

I have an NMOS with me so I tried to design this 12 V DC UPS circuit after looking at another similar PMOS circuit, but when I open the dc switch, the output is 18kV!! What is the problem with this ...
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3answers
562 views

output resistance of current mirror

I am being asked to find the output resistance of the current mirror below. the correct answer is supposed to be R_out = 103k ohms. but when am simulating the circuit, I get R_out = 3.82k ohms. Can ...
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0answers
34 views

finding two drain currents

below I have the following problem along with the circuit's picture My analysis is as follows: for G and D open \begin{equation} I_{D1}=I_{D2}\hspace{10mm}therefore\hspace{10mm}V_{ov1}=\:V_{ov2} \...
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1answer
86 views

Cannot simulate my model on LTSpice

I'm having trouble trying to simulate my NMOS (FDG6301N) on LTSpice. I have a permanent error telling me ...
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1answer
64 views

Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached
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2answers
61 views

How to amplify the output of an on NMOS, connected to zero source voltage?

I am simulating a 3 transistor based XNOR cell using HSPICE. The circuit is shown in the picture. technology = 45nm Vdd=1.1v |Vth|=0.62v In the case of A=1 and B=1, the output is charged through ...
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0answers
26 views

NMOS varactor Simulation Help?

I am trying to simulate a pair of NMOS transistors as varactors (BSD connected). However, am not getting any resonance at the particular frequency of interest. When I am simulating it, it is giving a ...
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1answer
93 views

High-side gate driver not working under load high current

I have been trying to implement a current limiting circuit using a high power NMOS and high side gate driver. My idea is to adjust the PWM duty-cycle of the gate driver to give an limited (average) ...
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1answer
233 views

MOSFET pinch-off [duplicate]

I have difficulties understanding what happens in MOS-FET-pinch-off: Take an N-MOSFET: Near the source the gate-bulk voltage is high enough to form an inversion layer. So we have electrons as ...
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103 views

NMOS Gate RC Filter Values

I am designing a Reverse Polarity Protection circuit for a project by using an n-channel MOSFET. A basic schematic is shown here. I've added an RC filter so that the voltage on the Gate pin changes ...
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1answer
53 views

RC snubber on Mosfet (smps) max C

I am designing a SMPS from TI http://www.ti.com/lit/df/tidrgc2/tidrgc2.pdf We replaced the Mosfet fro schematic with STL11N65M5 that has a Coss of 18pf So I am designing a RC snubber across it and I ...
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1answer
31 views

Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
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0answers
67 views

Problem with negative resistance

simulate this circuit – Schematic created using CircuitLab Differential Pair with a current-mirror source. Requirments: Ad=30dB Dont use directly a current source Specifications Vt = 1,4 ...
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1answer
30 views

Does the AC analysis on LT spice find the voltage and current due to both DC and AC sources?

Does the AC analysis on LT spice find the voltage and current due to both DC and AC sources? Or must i do an op point analysis and a DC analysis? Im being asked to plot the voltage across Rs as a ...
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1answer
117 views

Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?

Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs. For example, could not we just put the green construction in the place of red ...
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1answer
117 views

Are these resistors in series?

We had this question as a part of a small signal analysis question on the Final. This circuit I drew below is the DC analysis which is the first step pre-AC analysis which will have a totally ...
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4answers
312 views

What is the use of pull-down networks in CMOS gates?

Below you can see the basic CMOS inverter. What I don't understand about this particular design is the purpose of the n-channel mosfet which is the part referred as pull-down network. What if we ...
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1answer
34 views

Small signal analysis of 2nmos

To introduce myself I am a first year EE student and an exam on AC circuits is comming up. Whilst practising I noticed one question I couldn't solve. No way I tried managed to get me the answer (which ...