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Challenges in Bandwidth in Common mode Choke Modeling

I'm currently working on characterizing a common mode choke (CMC). However, I'm encountering difficulties aligning the bandwidth of my model with the measured results. Specifically, when I attempt to ...
Alaska's user avatar
  • 101
0 votes
1 answer
36 views

Identifying and designing coils for generating parallel magnetic fields with smooth gradients

What is this coil called (see image) (blue line is field, blue circle is clockwise oriented coil, red circle is counter-clockwise oriented coil), and are there any tools that help design it? ...
user1402154's user avatar
8 votes
6 answers
3k views

STM32 for loop slows down code too much

I am using an STM32 STM32F103C8T6 running at 48 MHz using ADC DMA and I find that using a for loop for manipulating arrays is much slower than multiple lines of ...
Sujoy Bhattacharya's user avatar
0 votes
2 answers
147 views

Do HDL synthesizers "optimize code", more or less as compilers do?

I'm implementing a pipelined CPU in SystemVerilog. I need to propagate datapath signals from one pipeline stage to the next but, of course, not all stages produce the same number of signals. To keep ...
Dan's user avatar
  • 145
0 votes
0 answers
41 views

What are the advantages of implementing an optimization algorithm for PID tuning compared to classical methods?

I am new to studying algorithms, so I am wondering what are the advantages of using an algorithm such as Genetic Algorithm or PSO to tune the PID parameters compared to classical methods, such as ...
Fawn M's user avatar
  • 11
0 votes
1 answer
84 views

Laser diode control without PD

I'm currently looking for a new light source for a system. The laser diode seems to be an excellent candidate. However, for the specific wavelength I need (488 nm), diodes with an integrated ...
msch's user avatar
  • 83
0 votes
1 answer
92 views

Access individual bits of a variable

I'm making a code on a PIC16F628A running at 4 MHz that receives the serial bitstream of a 433 MHz remote. The catch here is that I'm forced to do some rather questionable stuff because the pin ...
fpp's user avatar
  • 183
1 vote
0 answers
57 views

Entire Complex Function for dynamical systems

I am working on my master Thesis and I was going through the 1966 Thesis by K. P. Sriram. Here, the author computes the switching curves for minimum time control of some "famous" systems ...
dodo's user avatar
  • 11
1 vote
1 answer
42 views

How to compare these parameters through a cost function?

I am comparing three filter designs based on different criteria. Basically my question is about what is like the best way to compute like a number, or figure of merit to evaluate this criteria. ...
Granger Obliviate's user avatar
0 votes
1 answer
144 views

Performance metrics for a VHDL/Verilog RTL design

Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. ...
Gaslight Deceive Subvert's user avatar
-4 votes
3 answers
273 views

Can a digital designer beat synthesis tools? [closed]

Here are two equivalent ways of writing an 8-bit parity generator in VHDL 2008: ...
Gaslight Deceive Subvert's user avatar
-4 votes
1 answer
124 views

How to find minimum number of NAND gates for a given Boolean Expression by Using Genetic Alogorith(How to write a Code ) [closed]

I have been trying to write a code using gentic algorithm to find minimum number of NAND gates,but i have no idea of how to take a chromosome or case to find nand gates,and how to find fitness value ...
trendy19's user avatar
0 votes
2 answers
287 views

Using transistors to boost MOSFET gate voltage alternatives [closed]

I'm working with a micro controller based on CMOS logic. So I want to drive a load that is connected to the P-MOSFET low side. To make sure that the gate is fully saturated, I want to boost the 5 V to ...
Oliver's user avatar
  • 39
1 vote
2 answers
50 views

Time optimum controller

I have a question regarding time optimization that I would be very grateful if you could guide me on it. The question is moving a car/mass with nonlinear forces acting on it from point A to point B ...
mehrdad 's user avatar
0 votes
1 answer
126 views

Optimal LED circuit design [closed]

I have a personal project. I must create a circuit with 20 LED (20 mA, 2.0 V) on a battery car supply (12 V). So my question is, which mode is optimal? I designed two schematics: 4x LEDs in series ...
SkePsis's user avatar
  • 67
1 vote
1 answer
316 views

Lower idle current - battery powered ESP32 circuit

I am building a Li-ion powered circuit to power a remote night light. The mA values were measured with a cheap multimeter, I guess at least the deep sleep current of the ESP32 is actually lower. The ...
codeleger's user avatar
0 votes
1 answer
103 views

How to I optimize this LED circuit?

The Project This part is pretty simple: I'm building a stunt lightsaber up from scratch. The led is held in a heatsink housing inside a 1 inch (internal diameter) aluminum tube. The heatsink is rated ...
Jasmine's user avatar
  • 111
1 vote
1 answer
54 views

Is it mandatory to sign-extend when adding two different-sized buses?

I am trying to optimize a critical path in my design. The bottle-neck of the path is a 32-bit ADDER between a 32-bit bus and a sign-extended 16-bit bus. At first, when I didn't realize it was signed, ...
Tomerikoo's user avatar
  • 111
0 votes
1 answer
229 views

FSM state assignment techniques, which one should I use?

I'm currently studying finite-state machines at my university and the topic of state assignment optimization came up today. Apparently there are several technique for finding the correct state ...
G. Ajello's user avatar
-1 votes
1 answer
364 views

How does propagation relate to switching time of a circuit?

I have this circuit: I know how to measure the propagation delay between a certain input and output. In my homework, I am required to optimize the area of each transistor. One point that occurs to ...
Mirage's user avatar
  • 1
1 vote
2 answers
520 views

Frequency-dependent behavior of a resistor in time domain simulation

I know for a fact that to take into account frequency-dependent behavior in time domain simulation, equivalent electrical networks that reproduce the same frequency behavior are used, as it happens, ...
Wallflower's user avatar
1 vote
2 answers
129 views

How to hash map known values to smaller data width?

Story: I have an input bus of 17b = 131 072 values. An output bus of 10b = 1024 values. Among all the 131 072, only 20 000 values are used and known in advance. I'd like to map all those 20 000 values ...
None's user avatar
  • 372
1 vote
1 answer
446 views

Lattice Diamond — How to identify which parts of design take most of FPGA resources?

I have a Lattice FPGA-targeted design which already takes approximately 95% of the SLICEs available on the device; pretty close to the chip capacity. Unfortunately, I need to add some more logic to it,...
firegurafiku's user avatar
3 votes
1 answer
3k views

.step and .list param function for real components in LTSpice

I know that LTSpice can compute simulation in .step and .list param functions. However, those lists are ideal (not real). Is there a means to use the .step and .list param function for real components ...
Ady's user avatar
  • 83
0 votes
0 answers
158 views

TVC PID Controller how to adjust angle and thrust?

Hi there I wanted to simulate a rocket landing like for example the falcon 9. I was able to write myself an simulation in which on every loop turn I adjust the angle and thrust. Now this is for school ...
SebNik's user avatar
  • 109
13 votes
6 answers
2k views

Tips for optimizing through-hole soldering

I make and sell low voltage, mostly digital, retrocomputing expansion boards as a hobby/hustle. I use all through-hole components partly because of the retro aesthetic and partly because I find ...
Sam Washburn's user avatar
1 vote
1 answer
358 views

C++ AVR big code size & excess unused symbols in build file

I'm developing the program for the AVR microcontroller in C++. I have created a class that contains 8 methods(with constructors) but used only 3. Class code: ...
manueld4722623's user avatar
2 votes
1 answer
262 views

C++ AVR microcontroller optimization problem

I'm faced with a weird problem. I'm developing a program for AVR. Microcontroller ATtiny85. Frequency 1 MHz. Programmer ...
user448's user avatar
  • 21
2 votes
2 answers
180 views

How to safely connect unused opamp stable for gain of +2

Please refer to AD828 or any other bipolar op-amp not unity gain stable. Which of the two below cases is better? Any other suggestion? Simulation suggests the second, but I need to understand if the ...
Gianluca G's user avatar
2 votes
1 answer
156 views

Singular interval condition for Multi input in Optimal control

The definition of singulr interval is shown in Figure. I've struggled with this problem. I think the solution of this prob is "because if the E_j matrix is not singular, it means the System is ...
Damien's user avatar
  • 21
2 votes
0 answers
65 views

Need help understanding notation in mathematical optimization equation?

I have been reading the research paper ["Distributed Joint Power, Association and Flight Control for Massive-MIMO self-Organizing Flying Drones"][1](Paper is from IEEE so it might be stuck behind a ...
Gabe Skidmore's user avatar
0 votes
3 answers
362 views

Optimization kills the switch statement that I need to use in a function

Optimization kills the switch statement that I need to use in a function Hi all, how are you?. I'm doing a project with a STM32F103C6 (it has 32KB flash) and I had to activate optimization options to ...
vram's user avatar
  • 158
0 votes
1 answer
100 views

Optimizing Multilevel circuit Logic with SDCs

I am reading "Principles of Modern Digital Design" on chapter 3.10, but I am confused on a certain part. It says that you can reduce multilvel circuit logic using SDCs. Suppose you have the ...
pewpew_beepboop's user avatar
0 votes
1 answer
699 views

Best way to optimize verilog cpu?

I wrote a riscv core in verilog which works fine, but is slow. It can't go faster than 50mhz when synthesizing in Xilinx ise for spartan 6. I have however seen similar cores be able to go to 100mhz or ...
user avatar
1 vote
2 answers
356 views

VHDL: Kan sequence of if/else be optimized?

I am new to VHDL and I try to find all places where I can replace if/else statements with cases of inlined OR/AND operations to get more things executed in parallel instead of sequence. Now I have ...
Stephan Møller's user avatar
1 vote
1 answer
65 views

Find higher voltage among several voltages without MCU or ADC

I have 13 sensors with voltage outputs, each sensor can provide a voltage up to 3.3 volt, so I have 13 voltage lines. My goal is to somehow sort these voltages without using any MCU or ADC chip for ...
ElectronicLover's user avatar
0 votes
0 answers
36 views

Formally determining the minimum number of poles needed to realize some suggested switching arrangement

Many times, when designing passive switching circuits, one has the following engineering problem: We know we want to have some number of switches, each with some number of throws. For each possible ...
Mike Battaglia's user avatar
2 votes
1 answer
234 views

Finding coefficients for a PID controller that minimize the integral of the squared error (ISE)

The problem The problem is to find the coefficients for the P, I and D terms of a PID controller used to regulate the object that minimize the the integral of the squared error (ISE): $$Q = \int_0^\...
user24139's user avatar
16 votes
2 answers
2k views

Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
Hugo Sereno Ferreira's user avatar
0 votes
0 answers
109 views

Preferred resistor (E series) value optimiser

Is there a tool to find the closest optimum preferred resistor values given a list of constraints? For example I'm designing a filter but only have a few odd resistor and capacitor values to choose ...
Alessi 42's user avatar
0 votes
2 answers
307 views

Prevent compiler optimization for memory access in reflashable memory area

I am working with an embedded software in which part of the software(some CONST config values) are reflashable, without modifying the application software. Consider the following code: ...
stenvar's user avatar
  • 741
4 votes
1 answer
260 views

Compiler optimization prevents code from running

I was trying to upload a simple code to my board Tiva C EK-TM4C123GXL but it didn't work. I found out that when I turn the optimizer off, the code works fine. This is the code for blinking the on-...
Gamal Othman's user avatar
1 vote
2 answers
199 views

Altium Designer: Not assigning all the sub-parts of a device

I've been banging my head against this one for a while now and can't seem to find and answer anywhere. I have a multi-channel design that uses a a quad comparator as the base part. However in the ...
Jean Rubillon's user avatar
1 vote
2 answers
168 views

Optimizing magnetic field force of a coil

For a personal project, I've done a redesign of Samy Kamkar's MagSpoof project. Basically, it is possible to use an electromagnet, h-bridge, and microcontroller to trick a magnetic card reader into ...
willem.hill's user avatar
0 votes
1 answer
250 views

Optimization voltage divider measurement

How to design a voltage divider to optimize the measurement error? Intuitively I would take the same ratio $$\frac{load}{divider} = \frac{divider}{measurement}$$ As follow: the voltage is roughly ...
Rémi Baudoux's user avatar
4 votes
3 answers
481 views

How to optimize a binary circuit?

I'm currently in the situation in which I need to optimize a binary circuit by reducing its number of gates. We regard a circuit simply as a directed acyclic graph with some input wires and some ...
Daniel's user avatar
  • 141
1 vote
1 answer
89 views

DC Power Supply Output Caps: Electrical Advantage to using many smaller capacitors instead of few large?

Question: What is the electrical advantage to paralleling smaller capacitors to reach a given capacitance, rather than using fewer smaller capacitors on the output of a DC power supply? For example, ...
Jim's user avatar
  • 1,657
0 votes
1 answer
124 views

2^4 finite field multiplication in VHDL

I am currently trying to optimize a 4-bit finite field multiplication modulo X^4 + X^3 + 1 that I've made in VHDL. I did a 16x16 array containing all the results of ...
Cedric's user avatar
  • 25
0 votes
1 answer
286 views

Optimization of Vivado synthesis

I am currently using Vivado to develop several FPGA designs, and I am wondering if the components numbers given during Synthesis are optimal. I mean, are there some ways to optimize the synthesis, in ...
Cedric's user avatar
  • 25
0 votes
1 answer
1k views

Connect 3 circuits to one switch

I am building some electronic circuits with some arduino in it to animate LED-strip. The device is powered by 3 USB cables, because as I am using 270 RGB LEDs I can have 5A running trough the cables,...
Breci's user avatar
  • 3