Questions tagged [optimization]
The optimization tag has no usage guidance.
90
questions
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1answer
72 views
C++ AVR big code size & excess unused symbols in build file
I'm developing the program for the AVR microcontroller in C++.
I have created a class that contains 8 methods(with constructors) but used only 3.
Class code:
...
2
votes
1answer
86 views
C++ AVR microcontroller optimization problem
I'm faced with a weird problem. I'm developing a program for AVR.
Microcontroller ATtiny85.
Frequency 1 MHz.
Programmer ...
2
votes
2answers
63 views
How to safely connect unused opamp stable for gain of +2
Please refer to AD828 or any other bipolar op-amp not unity gain stable.
Which of the two below cases is better? Any other suggestion?
Simulation suggests the second, but I need to understand if the ...
2
votes
1answer
36 views
Singular interval condition for Multi input in Optimal control
The definition of singulr interval is shown in Figure.
I've struggled with this problem.
I think the solution of this prob
is "because if the E_j matrix is not singular, it means the System is ...
2
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0answers
57 views
Need help understanding notation in mathematical optimization equation?
I have been reading the research paper ["Distributed Joint Power, Association and Flight Control for Massive-MIMO self-Organizing Flying Drones"][1](Paper is from IEEE so it might be stuck behind a ...
0
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3answers
102 views
Optimization kills the switch statement that I need to use in a function
Optimization kills the switch statement that I need to use in a function
Hi all, how are you?. I'm doing a project with a STM32F103C6 (it has 32KB flash) and I had to activate optimization options to ...
0
votes
1answer
57 views
Optimizing Multilevel circuit Logic with SDCs
I am reading "Principles of Modern Digital Design" on chapter 3.10, but I am confused on a certain part. It says that you can reduce multilvel circuit logic using SDCs.
Suppose you have the ...
0
votes
1answer
79 views
Best way to optimize verilog cpu?
I wrote a riscv core in verilog which works fine, but is slow. It can't go faster than 50mhz when synthesizing in Xilinx ise for spartan 6. I have however seen similar cores be able to go to 100mhz or ...
0
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0answers
25 views
Gradient based optimization for microwave filter design
In S. Amari's paper - Synthesis of cross-coupled resonator filters using an analytical gradient-based optimization technique(2000), for reducing a filter's unnecessary cross-couplings,
the matrix \$[...
1
vote
2answers
58 views
VHDL: Kan sequence of if/else be optimized?
I am new to VHDL and I try to find all places where I can replace if/else statements with cases of inlined OR/AND operations to get more things executed in parallel instead of sequence.
Now I have ...
1
vote
1answer
52 views
Find higher voltage among several voltages without MCU or ADC
I have 13 sensors with voltage outputs, each sensor can provide a voltage up to 3.3 volt, so I have 13 voltage lines. My goal is to somehow sort these voltages without using any MCU or ADC chip for ...
0
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0answers
30 views
Formally determining the minimum number of poles needed to realize some suggested switching arrangement
Many times, when designing passive switching circuits, one has the following engineering problem:
We know we want to have some number of switches, each with some number of throws.
For each possible ...
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0answers
21 views
Particle Swarm Optimization for PI Tuning?
How can I use Particle Swarm Optimization to tune more than one PI controllers at a time and how can I design the objective function base on this?
2
votes
1answer
64 views
Finding coefficients for a PID controller that minimize the integral of the squared error (ISE)
The problem
The problem is to find the coefficients for the P, I and D terms of a PID controller used to regulate the object that minimize the the integral of the squared error (ISE):
$$Q = \int_0^\...
16
votes
2answers
2k views
Why is this Verilog RAM modification better in terms of resource usage?
I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
0
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0answers
50 views
Preferred resistor (E series) value optimiser
Is there a tool to find the closest optimum preferred resistor values given a list of constraints?
For example I'm designing a filter but only have a few odd resistor and capacitor values to choose ...
0
votes
2answers
116 views
Prevent compiler optimization for memory access in reflashable memory area
I am working with an embedded software in which part of the software(some CONST
config values) are reflashable, without modifying the application software. Consider the following code:
...
4
votes
1answer
163 views
Compiler optimization prevents code from running
I was trying to upload a simple code to my board Tiva C EK-TM4C123GXL but it didn't work. I found out that when I turn the optimizer off, the code works fine. This is the code for blinking the on-...
0
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2answers
63 views
Altium Designer: Not assigning all the sub-parts of a device
I've been banging my head against this one for a while now and can't seem to find and answer anywhere.
I have a multi-channel design that uses a a quad comparator as the base part. However in the ...
1
vote
2answers
78 views
Optimizing magnetic field force of a coil
For a personal project, I've done a redesign of Samy Kamkar's MagSpoof project. Basically, it is possible to use an electromagnet, h-bridge, and microcontroller to trick a magnetic card reader into ...
0
votes
1answer
156 views
Optimization voltage divider measurement
How to design a voltage divider to optimize the measurement error?
Intuitively I would take the same ratio $$\frac{load}{divider} = \frac{divider}{measurement}$$
As follow: the voltage is roughly ...
2
votes
1answer
242 views
How to optimize a binary circuit?
I'm currently in the situation in which I need to optimize a binary circuit by reducing its number of gates.
We regard a circuit simply as a directed acyclic graph with some input wires and some ...
1
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1answer
76 views
DC Power Supply Output Caps: Electrical Advantage to using many smaller capacitors instead of few large?
Question: What is the electrical advantage to paralleling smaller capacitors to reach a given capacitance, rather than using fewer smaller capacitors on the output of a DC power supply?
For example, ...
0
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1answer
72 views
2^4 finite field multiplication in VHDL
I am currently trying to optimize a 4-bit finite field multiplication modulo X^4 + X^3 + 1 that I've made in VHDL. I did a 16x16 array containing all the results of ...
0
votes
1answer
189 views
Optimization of Vivado synthesis
I am currently using Vivado to develop several FPGA designs, and I am wondering if the components numbers given during Synthesis are optimal. I mean, are there some ways to optimize the synthesis, in ...
0
votes
1answer
733 views
Connect 3 circuits to one switch
I am building some electronic circuits with some arduino in it to animate LED-strip.
The device is powered by 3 USB cables, because as I am using 270 RGB LEDs I can have 5A running trough the cables,...
0
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0answers
27 views
How much more hardware for Keerthi's' SMO compared to Platts SMO?
Not sure if this is the correct forum to ask this question. Please let me know if it is not. It would be great if anyone can point out if there is any forum where it may be accepted.
This question ...
2
votes
2answers
2k views
ltspice matlab optimization
Has anybody used ltspiceIV in a optimization process using Matlab? I need feedback because I am running my circuit in transient analysis, and when I found the optimal point of my optimization, I ran ...
10
votes
7answers
1k views
Simplifying many window comparators
I have 8 thermistors and I must make sure that each of them is inside a temperature window. They all have the same window and I don't care which or how many are inside the valid range, I just need to ...
6
votes
2answers
931 views
Minimizing(optimizing) digital logic circuit with multiplexer(s)
(this by the way was an exam question)
For \$F = \sum m(2, 3, 5, 7, 11, 13)\$, I am trying to implement a digital logic circuit using only the following:
2:1 MUX (cost: 12, and must use at least one ...
0
votes
1answer
61 views
Is there an advantage to my sequential circuit optimization?
I'm trying to create a snake game on a Xilinx Artix7 FPGA, and one of the things I want to check is if the snake has collided with itself. I need to perform this check between game updates to know by ...
2
votes
0answers
1k views
Speed up Vivado Implementation
In Vivado, implementation of my projects can take a while especially if I use debug cores. What can I do to make implementation faster? I tried the "RuntimeOptimized" constraint and it made no ...
2
votes
3answers
338 views
Design to replace several jumper on a dense PCB
I'm working on the design of a board which include a lot of Jumpers (around 40). They are used in order to provide a possibility to connect or disconnect parts of the schematics. Signals are all ...
2
votes
2answers
160 views
How to partially drive a load with respective impact on my electricity meter?
I want to optimize the use of my photo-voltaic production by redirecting the remaining unused energy to electric heaters in winter, or something else in summer (given that fans are inductive loads and ...
1
vote
1answer
273 views
How to predict the output of a solar panel depending upon weather conditions for real time hardware simulation?
I want to build a system for smart grid which can optimize the grid power, load and battery charging to reduce my costs for grid power. For the optimization problem, I must know the current date to ...
3
votes
3answers
851 views
Optimizing Resistor Values for Comparator Reference
Curious if there is a general rule for optimizing total resistance values in a voltage divider reference in a comparator circuit. Guessing it ultimately comes down to whether maximizing accuracy or ...
1
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0answers
73 views
Optimal design of electrical grid [closed]
After all that has been learned about electricity - if the grid and removing financial considerations and adoption feasibility. Imagine you're constructing for Mars or some post apocalyptic ...
3
votes
1answer
137 views
Supercompilation for electronic design
I'm reading Advanced FPGA Design and the first example, one of simply raising a number to the 3rd power, quickly diverges into various quite clever optimizations to make the valuation faster.
Now, ...
1
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0answers
2k views
Implement a 3-input function using only two 2-input LUTs
This is my homework: "Given the function \$f(x_1, x_2,x_3) = \sum (2,3,4,6,7)\$ Show how it can be realized using two 2-input LUTs. Give the truth table implemented in each LUT."
At the beginning it ...
0
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4answers
2k views
Code Optimization of IF Statements?
Considering the design limitation of hardware (clock speed, memory, etc…), is there any better way to write IF statements more efficiently in C language (e.g. run on Arduino), more specifically the ...
0
votes
2answers
91 views
Stochastic optimal control different in finance and engineering [closed]
What is the different between stochastic optimal control approach in finance and engineering?
Why methodes used in finance approach like Ito calculus are not used in engineering?
6
votes
3answers
903 views
SPI chip select optimisation
I am designing an SPI system with one master and two slaves. In a normal SPI system, the master needs 2 outputs to control the slaves' chip select lines. I want to use only one output to drive both ...
2
votes
1answer
286 views
XC32 optimizes vaiable used for register reading
I am facing a problem with XC32 compiler's optimization. Whenever I write a function to read something from register, XC32 optimizes (read: Removes) the variable which holds the return value.
I have ...
0
votes
2answers
59 views
Optimization of component values in LPF
I'm designing a 2nd order low-pass Butterworth filter using a Sallen-Key topology (for reminder) :
simulate this circuit – Schematic created using CircuitLab
Now, I am trying to find the ...
1
vote
4answers
3k views
How to control the driving frequency when working with high power ultrasonic transducers
I would like to know the simplest solution to dynamically tune the driving frequency of an ultrasonic transducer to its resonance frequency.
My amplifier has a power meter that I can read an optimize ...
2
votes
1answer
273 views
Optimally convert (small) boolean expressions into NOR form by hand
Is there a way to easily convert a boolean expression with only few variables into a NOR form?
Let's take the half-adder as an example:
...
7
votes
3answers
6k views
Most efficient way of creating a bool array in C - AVR
I'm using an Atmega32 to read various sensors using its ADC.
Using digital logic and a few multiplexers, I've multiplexed the entirety of PORTA, using PA0:6 for address and PA7 as the input. ...
2
votes
0answers
339 views
Exclude certain module from optimization in Xilinx ISE 14.4
I'm synthesizing a quite large design in Xilinx ISE 14.4 and would like to exclude certain modules from optimization. Is that possible?
The design I'm synthesizing is the LEON3 microprocessor. I have ...
2
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0answers
184 views
Operator synthesis VHDL, numeric_std.vhd
if i include the library numeric_std.vhd
(the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
0
votes
2answers
3k views
Xilinx ISE Synthesis taking too long
I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly.
Therefore, I tried to move to the ...
