Questions tagged [parasitic-capacitance]
Capacitance that arises from the physical layout of the circuit and the placement of components. Particularly notable when the addition of capacitance is undesirable.
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What is the resistance seen by the three parasitic capacitances of the transistor
I'm looking for a general expression for the resistance seen by the three main parasitic capacitances of the transistor (Cπ, Cμ, Co) can anyone recommended me a reference book that have the full ...
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How can I reduce the parasitic inductance of a metal film resistance
One example of a common resistor is metal film resistor, which has a high ESL. What are the practical steps to reduce ESL, other than to increase the area of the conductor and reducing the length of ...
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Cgs is ignored when computing load capacitance of CMOS inverter
I was reading the Microelectronic Circuits by Sedra and came across the content about computing equivalent load capacitence for CMOS inverter. Cgs is not shown on the image below and is not included ...
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Is there a static capacitance between the metals in coaxial cables and other metals in the environment (or at infinity)?
In a coaxial cable, we are familiar with the capacitance per unit length between the two metal conductors, which is given by C=(2pi epsilon)/log(r/R). However, in my circuit design, the static mutual ...
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Why do many mosfet models exclude Cds in parasitic capacitances?
Why do many models of MOSFET parasitic capacitances not include \$ C_{ds} \$?
(the image taken from this site)
In integrated circuits, MOS transistors usually have four terminals. If we consider ...
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PCB track widths for optimized layout for operational amplifiers
When designing a PCB track, its width, length, and stack-up can introduce inherent inductance and capacitance. These parasitic elements can significantly impact the performance of sensitive circuits, ...
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Food for thought: Which person has truth in this discussion on capacity and AC? [closed]
I have stumbled upon interesting discussion in the commentary section regarding safety of electrical engineering in home environment.
person1: AC voltage 'flows' even through insulator, fact.
person2:...
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Gain bandwidth calculation of two stage op-amp
I want to design a two stage single ended OTA without using a Miller compensation capacitance.
Every source that I have examined gives a design example with a compensation capacitance.
Hence, they ...
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Is it possible to match impedance "with lower parasitic capacitance", or is parasitic capacitance itself a part of impedance
Parasitic capacitance makes the signal rise and fall slower, so I want it be as small as possible, but when I try to adjust parameters in Altium Designer (e.g. trace gap of a differential pair) for a ...
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Investigating the effect of PCB layout parasitic in an op-amp amplifier by simulation
Would you please let me know what components I should add to my schematic as result of PCB parasitic to make my simulation more accurate?
As an example, the following image shows an amplifier ...
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How to reduce on-resistance and parasitic capacitance effects of my MUX setup?
I am designing a mux board to mux a flashing setup. Both UART and SPI lines are on 1.8V logic. The Mux chips have ~4-8ohms on-resistance and 1.7pF on-capacitance. Few questions:
Would I need buffers ...
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Behavior of parasitic capacitance of MOSFET at off-state
I'm totally a rookie to power electronics. I'm currently interested in the behavior of parasitic capacitance from MOSFET at off-state (especially for Cds). The most of the literature or videos in ...
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Replacing MOS parasitic cap with external cap. Why does it differ from internal?
This is a circuit which has parasitic capacitors:
...
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MOSFET parasitic turn-on
I'm simulating a circuit which uses a high-voltage SiC N-channel FET to discharge a large voltage (something close to the breakdown voltage of the FET, 1.7 kV). The power supply for the circuit is a 1 ...
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Relationship between value of the totem pole output of the gate driver and the speed of turning ON of the MOSFET
We are using LT1243 gate driver for turning ON a MOSFET:
if you see the datasheet of the LT1243, then we will know it has a high totem pole output of 1 A.
which means that driver will drive a current ...
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How does moving an input signal node closer to the output node reduce parasitic capacitance
So I have been studying about logic gates designed using the CMOS family and in my professors notes it says "Move NMOSFET-B closer to output node, without changing the functionality , to reduce ...
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Crystal oscillator load capacitance voltage rating
I am using this crystal oscillator in my design.I know how to calculate the load capacitor.
The XTAL is connected to this microprocessor.
May I know how to select the voltage rating of the load ...
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How are RF filters constructed?
I want to know what filter circuits look like in the RF (MHz-GHz) frequency range. Are they just like low frequency LC filters, but with appropriately adjusted component values?
For example the VLF-80+...
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Can parasitic capacitances be decoupled?
I was working with some IC that has a bus that is really sensitive to trace capacitance and cannot be loaded with more than 8.5 pF.
I have to bifurcate the trace to an ADC because I need to see what ...
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Why does series-NMOS gate drive current affect the load, and how do I avoid it?
TL;DR: With two nMOSFETs in series, why does the load experience current spikes during switching times of one transistor even when the other is off - and how can I avoid it?
Consider the following ...
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What are techniques to fix/compensate parasitic effects that occur at very high frequencies in passive electronic components on circuit level?
There are of course equivalent circuit models for modeling practical passive components using idealized elementary circuit models that reflect the parasitic effects that occur at high frequencies , ...
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How to extract parasitic capacitance caused by PCB layout? [closed]
I'm working on a precision DC measurement PCB design based on the capacitance-integration method. The key element integration capacitor is quite precise. However, due to my specific PCB layout design, ...
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MOSFET in LTSpice not operating properly in saturation and cutoff
I am attempting to simulate the following circuit. The MOSFET does not completely go off and the sin wave still leaks through the circuit even in the off state. Moreover, the output signal's amplitude ...
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Comparator IC IN+ changing after voltage divider
I have a battery that is charged to about 6.85V, this is the "batteryvoltage" input. Due to the voltage divider on IN+ I read 1.7V at the comparator. But when I plug in a separate wired 12V ...
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Why is drain-source parasitic capacitance(Cds) omitted in JFET datasheets?
I've checked several datasheets on JFETs and I cannot find drain-source parasitic capacitance. They either include only Cgs and Cdg or they only include Ciss or Crss. Here are a few high frequency ...
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Estimating distributed capacitance from frequency sweep
I have a top/bottom spiral planar coil with the following frequency response. Is it correct to assume that the distributed capacitance is the sum of the capacitance values calculated over all the ...
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Need help with validation of the design of a capacitance sensor array for soil moisture measurement
Product Description
The device is a soil moisture sensing and analysis device that uses capacitance sensing technology to help manage soil moisture in your garden. One probe set at the bottom of the ...
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Does the electrical parameters of a packaged transistor change from bare die transistors?
When comparing the electrical parameters of the MOSFET/Transistors, do they change when the package type changes? Are the parasitic parameters of the packaged MOSFET and bare die MOSFET change.
It is ...
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How to extract parasitic capacitance of an oscilloscope?
Can someone please explain the procedure to extract the parasitic capacitance of an oscilloscope? I have seen that the contribution of probe capacitance is 3.9 pF. The scope is a Tektronix 3 series ...
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Parasitic capacitance of high-speed comparator
I simulated an LM119 high-speed comparator and built one on a breadboard.
May I ask how to increase the frequency of the square wave produced by adjusting the resistor's values instead of reducing the ...
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Crosstalk: How is the victim node voltage increasing through the leakage current?
Can someone explain how this circuit is working? How is the victim node voltage increasing through the leakage current?
Here is the image for more context:
(Source: Team VLSI - Crosstalk Noise and ...
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How do I stabilize the pulse widths of the 4029 Binary Counter?
I am working with a CD4029BE on a breadboard. The connections are as follows:
VDD to +12VDC
VSS to ground
The clock input receives a 3Hz 0 to +12V clock pulse
J1-J4 are shorted together, and then ...
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SPICE and Maxwell capacitance matrix
From this link I understand the definitions of a Maxwell matrix and a SPICE matrix
Maxwell and Spice Matrices - ANSYS
However, what is the meaning of a negative main-diagonal entry in a SPICE matrix? ...
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Parasitic capacitance in PCB high speed traces
I am learning high speed pcb designing and the parasitic capacitance is making few things difficult to comprehend. I understand how because of parasitic inductance cross talk emi and signal integrity ...
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Potential problems when using a high resistance voltage-divider
I want to design a circuit, that allows me to measure the voltage across a piezoelectric transducer.
The transducer itself has an impedance |Z| of 500 Ohms up to ~20 kOhms.
The voltage to measure ...
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PCB and breadboard parasitic capacitance
I am getting different bandwidth measurements from my breadboard and PCB (for the same circuit with exact same component values). The cut-off frequency I measure on the breadboard is slightly higher ...
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Where do these parasitic capacitances appear?
So here:
I assume each transistor has some sort of parasitic capacitance and that adds up into the non inverting terminal of the op amp? Why do those parasitic capacitances appear and how can i ...
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Unsure about the correct application of Miller's Theorem
Sorry for the long post but I figured it would be easier to include pictures and all relevant calculations so that there wouldn't be any confusion.
I have a circuit for which I'm trying to analyse and ...
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Typical parasitics values of thick film SMD resistor
I'm looking for values of parasitics for SMD thick thilm resistors (the cheap and readily available). Values of the following model
Closest I found is this application note from Vishay, but it is for ...
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What happens to parasitic capacitance and inductance in a superconductor?
Do the parasitics also become [more] ideal? Or are all changes solely due to the perfect conduction?
If not, how are the parasitics affected?
Such basic information seems necessary to engineer any ...
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Transformer's capacitance
Our main purpose is create the transfer function of a transformer, and we want that for a resonance frequency higher than 1 MHz for our LLC transformer in an LED project.
https://www.omicron-lab.com/...
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Problem with parasitic capacitor in feedback path in inverting circuit
I want to meet following conditions:
Gain: 27.74 dB
Input source resistance: 6800 Ohm
Bandwidth: 15Khz (I actually need to have a flat response until 10khz and I do not care about the rest of it)
I ...
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What happens when you reverse bias a NMOS with separate body terminal?
I am trying to create a current limiting circuit with minimal output capacitance.
I'm trying to build a circuit that optimises low parasitic output capacitance over linearity.
I used a SST215 DMOS ...
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Mitigating parasitic turn-on of MOSFET
UPDATE
Thanks Aaron and jp314 for your comments.
We just probed some more and I think jp314 is right.
We found that the high side driver was skipping some pulses. The pink pulse train is from the ...
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Thin Film Resistors, Deposition On One Side, Parasitic Capacitance if Resistor is placed such that Deposition next to PCB Ground Plane
I have a question for all high frequency and RF electrical engineers.
Thin film resistors have a vapor deposition of resistive material on one face of the component. Let's presume that the resistor ...
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Wouldn't using two MOSFETs in push-pull configuration to drive a single MOSFET be counter-productive?
I'm trying to make a buck converter that uses a P-MOS for high-side switching using an STM32's PWM signal.
I can't figure out why it would be useful to drive the MOSFET using a push-pull MOSFET gate ...
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capacitance at inverting op-amp input of unity gain inverting amplifier
[This question is related to another question. That other question asks why a particular op-amp behaves the way it does. I think there are many reasons, many of which are outlined in the answers to ...
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How would parasitic capacitance changes happen in a crystal oscillator?
This article about crystal oscillators talks about the trade-offs of different crystal load capacitance values (crystal load capacitance parameter, not load capacitor values)
It says “a crystal with a ...
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Why are parasitic capacitances the main factor for limiting high frequency performance of active devices such as transistors? [closed]
According to the Wikipedia article, the reason for the limit of frequencies in which transistors operate is the parasitic capacitance. But I don't understand why this is so.
Wikipedia article:
...
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MOSFET diffusion to substrate capacitance
in order to eliminate body effect one way is to connect the substrate to source when the well is for a single device (PMOS with a well in a CMOS for example) , but i read that it increases the source ...