Questions tagged [pcb-layers]

Printed Circuit Boards (PCBs) are composed of a sandwich of alternating layers of insulating substrate and conducting copper layers. The copper layers are etched to form connecting tracks between components as well as earth/ground or power planes. The simplest PCB has one substrate layer and one copper layer. Generally only the copper layers are counted. A complex PCB might have seven layers.

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PCB design: How small can vias be made?

Working with very limited space (In Altium) and need to place vias to make routes between the red solder castellation plates on the top layer to the respective connector pins on the bottom layer, both ...
eutectic_codswallop's user avatar
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Gerber X1 to Gerber X2 [duplicate]

I have gerber files from a client. Their extensions are: .fph, .fpl, .pho, .rep, .drl, .lst, .dxf. Of these, I know .drl are the drill files and .dxf is the mechanical drawing. Also, there is a .fph ...
Rohit Kulkarni's user avatar
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What is the optimal layering strategy of top layer and bottom layer for low-density board design?

I'm designing a board tasked with reading power meter information via SPI and displaying it on-screen. I aim to adhere to the layering principles advocated by Fedol Academy, which involve four layers. ...
Alirezaagha30's user avatar
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How to link GND vias to the GND plane

I know that it's possible for the GND vias to connect to the GND signal layer in a 4 layer stack. How do I achieve this?
9_daytona's user avatar
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Clearances issues during routing

I am designing a 4-layer PCB in Altium, and I have defined my clearance rules for my high-voltage board (100 V) in the rules section, but the Altium software has a default clearance rule of minimum 0....
Andr7's user avatar
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PCB design - Routing without a schematic

I am using Altium CircuitMaker to design a PCB. I'm wondering if there's a way to make my PCB design without a schematic. My idea is to simply make a PCB with just pads and populate it myself with the ...
Vagabond4761's user avatar
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Keysight ADS layout error "port pin not connected to conductive part of design"

I just designed a distributed element BPF using ADS and now I'm trying to put it into the layout to do an EM simulation. I created my distributed circuit using the dimensions of my components, then ...
TheBelgianWaffl _ Gaming's user avatar
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Ghost line/barrier showing in Altium deginer

I am having a problem where there's an area (line) that appears only while running traces and on the draftsman document. the ghost line/region does not show up on any of the layers, I toggled all the ...
queTak's user avatar
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How to place light guide film cuts as part of layer PCB

How can I go about doing something like this in fusion/ eagle? https://www.pannam.com/wp-content/uploads/2017/08/Implementing-LGF.pdf and https://www.snaptron.com/2021/03/how-to-place-metal-dome-...
Wes Ellgass's user avatar
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Altium: Exclude entire layer from Clearance Rule

I'm designing a PCB in Altium Designer. I've defined Clearance Rules for certain nets. When I run the DRC (Design Rule Check) I get errors that the Clearance between the Keepout and the Pad doesn't ...
puncher's user avatar
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Return current via

I have a 4 layer board. Layer 1 (Top): SIGNAL + GND plane Layer 2: whole GND plane (no tracks) Layer 3: whole power plane (no tracks) Layer 4: (Bottom): SIGNAL + GND plane After putting vias ...
Alatriste's user avatar
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How to decide number of layers?

I am new to PCB design and I want to understand to understand how many layers to choose. I just know more layers helps to make the routing easy but I don't understand what is power plane, ground plane ...
Andr7's user avatar
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Review of PCB RF Design

I designed a 4 layer RF board with the NRF24L01+. When I got the boards in to test I was not able to establish a radio link with some other NRF24L01+ modules. I have attached my schematic and board ...
M.Schindler's user avatar
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4 Layer PCB Stackup - Ground and Power on the inner layers or outer layers?

I am designing a 4 layer board (2 signal, ground, and power), and is there any reason not to have top layer power plane, middle layers signals, and bottom layer a ground plane? I am concerned about ...
user1045680's user avatar
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PCB Design Question - Power Plane or Fat Traces for High Current

I have designed my first pcb (4 layer) and I have a question about power planes versus power traces. I am using KiCad 7. I have tested the circuitry on a proto-board. I have a high current section (12-...
user1045680's user avatar
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Power plane vs polygon pours

This question is being asked from perspective of Altium but applies to other PCB CAD programs as well. So we can have two type of dedicated copper areas for power on a PCB plane. One is a polygon pour....
quantum231's user avatar
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For a 6 layer PCB, what difference does it make if we use a CPCPC vs a PCPCP? (C is for core and P for prepeg)

I am working on a 6 layer PCB for motor control applicatin using Altium and the stackup being used is as follows: Sig GND1 PWR Sig GND2 Sig I am little confused regarding the correct order of core and ...
Umair Ali's user avatar
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Power layer filled with many different voltages

I have a board with 4 layrs: signal, GND, power, signal. I have a couple different voltages starting from a USB charger input until the very end to a BLE module: Input before current measurement ...
Gambanishu Habbeba's user avatar
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5 answers
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Is there any disadvantage in making a ground plane and a power plane in a 4 layer PCB?

I have read a lot of posts, forums, and application notes about why it's a bad idea to separate ground or power in mixed analog and digital circuits, so I've made a 4 layer PCB with full GND and VCC ...
santiago deliotte's user avatar
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Altium Layer Stackup - Not Loading Sierra Circuits Layer Stackup Export

First post. I am trying to load an exported XML file from Sierra Circuits: When I go to my Layer Stackup page in my project, then I go to File>Load Stackup From File... And it does not show any ...
Lin Crawford's user avatar
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route on inner or outer layers for SPI clocks signals etc?

What is better for (for example) an SPI clock signal: to be routed on the inner layers (more ground, avoid EMC issue) or on the outer layer? (Avoid changing layers and impedance mismatch and any ...
mr dude's user avatar
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PCB stencil layer for cutout

I ordered a multiple PCBs which all arrived fine. I never included a stencil because of the high cost for it compared to the PCBs. Now I combined a few board designs to fit on a single stencil, so I ...
RektByMemes's user avatar
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How does a copper pour work in Kicad?

In my project, I have a label in the schematic as Vcc. When I created my backside copper pour in PCBnew, I gave it the Vcc net. Thus, when joining a Vcc pad on the frontside layer, via a via to the ...
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Kicad PCB Layout: Nets not visible in different layers

I am trying to do a copper pour on one of the layers on my PCB and for some reason, the nets are not visible to any other layer except the top layer. I have tried to do a copper pour on the top layer ...
Bilal Afzal's user avatar
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Logic of splitting planes in Altium of different "voltage areas"

If I understand correctly there is a concept of whole areas on a single plane for different voltages (as shown below). They made an area on another layer an area for 12 V nets and on the same layer. ...
lub2354's user avatar
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Putting caps, resistors, etc on back side of board

Assuming I am ok with the extra cost of having parts assembled on the backside of my PCB, does it make sense to basically place all the main parts on the top side and then strategically place all the ...
Kevin McQuown's user avatar
2 votes
0 answers
153 views

Adding a Chassis Ground at the Midpoint of a PCB

The PCB I designed is 6-layer. I will create a chassis ground in the form of a frame surrounding the mounting holes and add a Y capacitor between and to the signal GND. And I will surround this ...
Electronx's user avatar
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Using vias with power and ground planes in altium designer 20.2.4 cross error

I'm making a pcb with a 4 layer stackup. The top layer and the bottom layer are used for signal and component routing. The 2 layer is GND (analog and digital planes) and the 3rd layer is Power (analog ...
santiago deliotte's user avatar
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1 answer
56 views

6-layer stack up: Optimal core/prepreg thinkness and coupling to GND

I'm designing my first 6-layer board using a SIG|GND|SIG+PWR|SIG+PWR|GND|SIG stack up. This is often claimed to be the best stack up online and in literature ...
Tim's user avatar
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How to correctly design ground planes simple circuit PCB's?

I'm a little new to PCB design and could use some help figuring out the best way to make this very simply PCB that I plan to connect to the back of a custom led light sign that I'm making. The circuit ...
KidWithComputer's user avatar
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Altium aluminium base layer stackup

I need to design the aluminium base pcb , i dont know how to set the layer stack for aluminum layer in altium , attahed the sample image of layer stack of single layer I set the top copper layer , ...
Marimuthu C 's user avatar
1 vote
2 answers
125 views

Modifying Gerber file

I am using the X-NUCLEO-NFC02A1 development board for one of my projects. But I want to make a few modifications to that board design. So I tried to download the Gerber file from the manufacturer's ...
Isuru Bhathiya's user avatar
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0 answers
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PCB Review (ATmega32U4 + Bosch BNO055 IMU sensor)

So I'm very new to PCB design and would like to get feedback on the layout I've done. I've attached the layers for the board which is a 4-layer stack-up. I'm working with some space constraints too so ...
Yeo's user avatar
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1 answer
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4 Layer PCB layout with microcontroller and IMU

I'm trying to design a 4-layer PCB board and would like to check if the following layout will perform well. By well, I mean if it will perform optimally. Factors such as Low EMI and noise coupling etc....
Yeo's user avatar
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1 answer
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How can I set a clearance in my polygons? Because there is an error of short circuit between poly of GND or 5V and my vias

I tried to solve these errors using blind and buried vias, but the errors persist. I want when I repour the poly, it creates a clearance between the vias and poly. Or another solutions for the error. ...
Vladimir Villamizar's user avatar
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265 views

What is the black stuff on the PCB below remote control buttons?

The picture:- You can see the pads with labels like "K7", "K8", "K9" e.t.c. So two related questions are:- What is the black stuff (it's loosely conductive)? Can I ...
Paul Uszak's user avatar
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1 vote
1 answer
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Drilled vs micro vias

I understand there are regular PTH vias drilled once all layers are stacked together then plated (e.g. the Thru 1:9 via on the left of the image below) There are also Blind vias which are drilled into ...
MRB's user avatar
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Altium hatched polygon not covering whole PCB on one layer

I have a two layer PCB on which I want to use hatched polygons on top and bottom layers. For some reason the hatched GND polygon on the bottom layer is not covering the whole layer. PCB Layout Bottom ...
Lyoner's user avatar
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3V3 polygon has a GND vias layer in it

So i dumbly overlooked an error before sending the PCB into production. So my question here is, is there a chance to fix this manually once i get the PCB or is contacting manufacturer is the only ...
narusik's user avatar
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2 votes
2 answers
82 views

Is that good application paralleling power copper pours on PCB for heat dissipation and connect with via?

I am using isolated SMPS power module in my PCB layout. I found good examples about layout here. https://www.powerctc.com/en/node/5139. I have completed routing the isolated SMPS power module from the ...
Electronx's user avatar
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1 vote
2 answers
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Effective dielectric constant in multilayer PCB design

Top => copper PP1 => RO4350B L2 => copper PP2 => FR4 L3 => copper PP3 => 185HR L4 => copper This is my PCB stackup. In the top layer, I have a 50 Ω controlled RF trace. The ...
karthik's user avatar
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3 answers
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The pads for a switch on my ODROID-XU4 are destroyed. Can it be saved?

I have an issue with a switch which selects if the ODROID-XU4 shall use the eMMC or the SD card. As you can see, as I tried to fix it, I destroyed the pads. Only one pad is still intact (eMMC.)
alesko's user avatar
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How to change close spacing in a PCB?

I am designing a board with an STM32F103C8T6 processor. I watched some videos by PhilsLab to learn how to work with KiCad. After I watched some more videos to learn how to make my board look more ...
Y-E-Quit's user avatar
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2 votes
2 answers
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6 layer PCB stack up and routing strategy

I have a couple of questions about the stack up and routing strategy in a 6 layer PCB. I'm in the situation where all the important chips are on the top layer, so all the important tracks start and ...
Federico Massimi's user avatar
2 votes
1 answer
183 views

What should be the recommended PCB thickness for a circuit involving mains voltage, with 4 layers?

The PCB manufacturer has asked if they can use thickness of 1.6mm, but my total stack-up thickness is 1.8mm. This is the current stack up What additional considerations should I take into account to ...
S_D's user avatar
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1 answer
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Ground pour vs vias to ground plane in 4 layer PCB?

I am designing a fairly simple PCB with 4 layers and some IC-s. The layers are: Top: Components + signals In1: GND In2: +3.3V Bot: Some signals There is an IC with a lot of GND pins, and currently I ...
Gabi's user avatar
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Altium Designer - Polygon pour clearance across all layers in multi-layer PCB

I'm using Altium Designer to design a 4-layer PCB. In the power supply region (230 VAC power lines to an AC-DC converter), I'm routing exclusively on the bottom layer, and have added a rule to ...
DrCeeVee's user avatar
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243 views

Where to connect two GND layers together?

I have a 4 layer PCB. The stackup is as follows: SIG + PWR | GND | GND | SIG + PWR Now I want to connect both GND planes with each other. EasyEDA Pro has this feature called "suture vias". ...
Cem Pamir Bana's user avatar
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Does separating DGND and AGND with two different layers for each make any sense?

In my last question I found out that having two different layers for Ground and Analog Ground may induce capacitive coupling. Now I want to ask more generally if the idea I had is worse than ...
Cem Pamir Bana's user avatar
1 vote
1 answer
115 views

Tracing to see if IC is TM1650 or something else

I am tying to determine where the PCB traces are going in order to figure out if this is using the TM1650 or something else. Most of these (this is from a pool pump) uses the TM1650 but there are some ...
StealthRT's user avatar
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