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Questions tagged [pci]

The Peripheral Component Interface (PCI), a parallel master-slave bus, was the dominant bus to connect computer peripheral cards in personal computers and servers. It was mostly superseeded by the very different PCI express (PCIe) interface.

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Origin and underlying sense of the term "Posted" in PCIe

When PCI Express replaced the operation of reading directly from a PCI peripheral card over a bus, directly addressing its I/O ports, or performing a configuration cycle on it directly, with instead a ...
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Do extra PCIe lanes improve latency?

If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster. But if you never need ...
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32 UART on a single system

I need to add 32 serial ports to an SBC, for my tests I'm using a raspberry CM4, but it could also be a similar SBC. I'm trying to figure out what solution is best for having 32 serial ports on my ...
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Can a PCI bus master access a device mapped in cpu memory space

If a PCI bus master can access memory space just as cpu can, can it put an address on the memory bus of the cpu that actually triggers a memory mapped I/O device to respond to that address. (As if the ...
John greg's user avatar
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Does PCI require bus transaction routing

Does pci require routing mechanism in those 2 cases The two devices are on the same PCI bus and aren't seperated by a bridge. They aren't on the same PCI bus. I don't think it requires a routing ...
John greg's user avatar
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PCIe Domain, Bus, Device, Function limits

I am new to PCIe. I would like to understand 256 (bus), 32 (device), 8 (function). I am trying to visualise these PCIe slots on a motherboard. I am used to desktop motherboards where we have one ...
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How are BAR registers handled between end points in PCI Express?

I have a question related to the PCI Express protocol. I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process. I know the ...
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Remapping a PCI(e) device when another core is accessing the device

According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)? If not, ...
Abhishek Anand's user avatar
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What does "No receivers detected" mean for Configuration Link Status?

I'm trying to bringup PCIe, and stuck when trying to link up. Configuration Link Status is 00, which means "No receivers detected", as this document says ...
Chen Li's user avatar
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Why is a PCI card treated as two loads on the PCI bus?

In PCI bus introduction materials, especially when talking about the load capacity of the PCI bus, it's often stated that a PCI card inserted into the PCI slot is actually acting as two loads on the ...
bruin's user avatar
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Do PCI Express devices' interrupts always go through a PIC or an APIC?

My Question is PCI/PCIe interrupt path to CPU is through a PIC or an APIC? https://people.freebsd.org/~jhb/papers/bsdcan/2007/...
Franc's user avatar
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Detect power/run status of PC in hardware

This may well be a daft question and/or a failure to google effectively (and apologies if this would be a better fit on SuperUser or somewhere else?) but is it possible, in low-level hardware, to ...
John U's user avatar
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PCIe PRST pin functionality at M2 connector (B) with SATA device (reboot detection)

M2 connector type (key B) support PCIe ×2, SATA, USB 2.0 and 3.0, audio, UIM, HSIC, SSIC, I2C and SMBus. I want to use SATA interface with my device, but I need to detect the reboot of the host ...
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What limit the pci-e splitting on this case?

I am trying to understand the PCI-E principles but I miss something. The reason why I need to understand that is because I working on a project that involve a lot of SATA HDD to be connected to one ...
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Backwards compatibility of PCIe AC coupling capacitors

The PCIe base spec mentions that platforms operating only at 2.5GT/s or 5GT/s may use AC coupling capacitors in the 75nF-265nF and that platforms supporting 8GT/s and above must use 176nF-265nF. ...
user2005848's user avatar
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What value to use for Byte Count field in PCI Express (PCIe) IO read completion?

In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read. A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
EquipDev's user avatar
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Does my PCIe platform support CLKREQ#?

I succeeded entering ASPM L1.1 and L1.2 for my device. After entering ASPM L1.1 or L1.2 and trying to initiate to exit from Host side, I saw some hosts that are: • Able to initiate an exit from ASPM ...
Omer G's user avatar
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PCIE Gen 2 Intra-Pair Skew

I am about to make a revision of a PCB that has 60 mills of Intra-Pair Skew in PCI-E (Gen 2) RX differential pair: Considering the capacitors the skew is ~50 mills: this is the relevant part of the ...
Firas Abd El Gani's user avatar
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Unable to Identify VL805 device

I have designed a PCIE to USB3 converter device that is based to VIA LABS VL805 Q6 Chip. My problem that I can't recognize the VL805 chip in Linux, using the command "lspci": here is the ...
Firas Abd El Gani's user avatar
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The detail of External PCIe cabling specification?

As searching on the Internet, I found that the PCI group has released the "PCIe External cabling specifications". But I can not download the document because I am not a member of the PCI ...
Dong Vo Thanh's user avatar
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How does a motherboard convert the input voltage to the 12V of the PCI? [closed]

Has it a DC/DC converter inside? Are the 12V guaranteed to be 12.0V sharp?
EnnioEvo's user avatar
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What happens if the PCI voltage in input to a GPU is different from external power supply voltage?

In particular if there is a difference of one or two volts between the two inputs? Is it safe?
EnnioEvo's user avatar
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How does a PCIe device know that its 4K configuration space is mapped to memory address?

PCIe spec defines 3 address spaces: Memory IO Configuration I can configure the BAR register to specify the memory address range that a PCIe device will claim. ...
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Testing PCI Card [closed]

I have two questions I will try to be detailed as I can here. I have a PCI Wifi card I want to know if it works or not. I do NOT have a computer in which to test this on. The model #F5D7000 is a ...
Wizardof87 1987's user avatar
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What is "shadow" configuration space?

In a github project I saw a feature as follows: Support for writing to custom shadow configuration space. I know what PCI config space is but what is a "shadow configuration space"? I google'd but ...
Joe Toe's user avatar
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What is the maximum number of devices a single PCI bus can handle?

During system initilization software enumerates the different buses, devices and functions with the help of two I/O Ports (CONFIG_ADDRESS 0xCF8, CONFIG_DATA 0xCFC) and two configuration cycle types. ...
blackdog's user avatar
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PCI based system debuging

I've came across some products that help you troubleshoot a computer that won't POST, with listening and capturing traffic on PCI bus during system startup. They essentially know the normal procedure,...
Solid State's user avatar
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How exactly does CPU set C/BE lines on a PCI bus?

In the PCI bus spec, when in the address phase of a transaction, there are extra bits for specifying the type of transaction (called C/BE). These lines are also re-used during the data phase of the ...
Mahkoe's user avatar
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PCI card electromechanical specification

I am making an old PCI (5V) form factor card for a product, and am having a hard time finding any sort of reliable drawing showing the official dimensions of the gold fingers, key cutouts, and their ...
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Understanding pci address in lspci/dmesg

When looking for the pci devices on the host machine, I have seen something like this in lspci: ...
matryx's user avatar
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What are the advantages of this gold finger shape?

Some PCBs, like the PCI card specification have gold fingers which start very narrow near the bottom edge, and gain their usual width much higher, where the actual contact is expected to be made. What ...
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VME64 vs PCI Bus for vibrating environment

I have to select between VME64 bus and PCI bus and one of the important decision metric is concerned with the connector types used in these buses. My application is in a vibrating environment. I ...
alt-rose's user avatar
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Bus mastering VS Bus arbitration [closed]

If there are multiple bus masters possible in a bus architecture then is it certain that 'Bus arbitration' will take place before a master gets hold of the bus control or is it possible that bus ...
alt-rose's user avatar
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Decoding Signals from an Unknown Port on Spectrometer

We have a Thermo-Nicolet Nexus 670 FT-IR Spectrophotometer, made in the USA around 2000. It was the work horse of the infrared spectroscopy community. The instrument sends out signals to a proprietary ...
user1596683's user avatar
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Is it posible that two devices plugged in different PCI slots share single PCI bus

Let's assume we have two network cards, Foo and Bar plugged in slots 5 and 4 on motherboard, with some BDF id assigned, for example: Foo => 09:00.0 Bar => 02:00.0 That's the usual scenario. But is ...
Outshined's user avatar
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Understand the Primary/Secondary/Subordinate Bus number in PCI/PCIe Bridge

I am new to the PCIe world. I am learning the enumeration and configuration of PCIe hierarchy. Some quote from here: For PCI-PCI bridges to pass PCI I/O, PCI Memory or PCI Configuration address ...
smwikipedia's user avatar
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Why are PCIe Config Writes non-posted?

In PCIe, why are config writes non-posted? Why can't they be like mem_wr which are posted?
user7656686's user avatar
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What limits the number of buses, devices and functions on a PCI bus?

I am learning the PCI/PCIe bus. I learned that: A PCI hierarchy can support at most 256 buses. A PCI bus can support at most 32 devices. A PCI device can have at most 8 functions. I checked the ...
smwikipedia's user avatar
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