Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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Can a PCIe Bridge connect to multiple downstream devices using different functions?
My understanding of PCIe bridges is as follows:
A PCIe bridge appears as 1 device on the upstream bus, creates a new bus downstream of it, and whatever connects to the downstream side will appear as ...
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Can someone explain to me why the math for PCIe bandwidth doesn't add up?
Since PCIe g1 x1 is based off PCI 32/66 bandwidth of 2133.33 Mb (...
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PCIe connector overhang
There are precise mechanical requirements for PCIe cards. Along the top edge, there's a 1mm strip where copper and components are not allowed. If you're designing a PCIe card, and have connectors and ...
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Do extra PCIe lanes improve latency?
If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster.
But if you never need ...
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PCIe Clock Buffer Daisy Chain
I have a PCIe clock buffer with 4 outputs that I would like to use for more than 4 PCIe devices. My question is can I daisy chain the buffers such that one buffer output is the input to the next ...
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What is the typical NVME SSD abrubt shutdown reaction time for a CC.SHN event until power loss?
The NVME standard under "7.6.2 Shutdown" defines the procedure for an abrupt shutdown event:
...
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Why does PCIe still hold on to 'transfers/second' instead of bits/second or symbols/second?
I think it is kinda all covered in the title. To my (incomplete) knowledge, PCIe is the only modern bus that still expresses its rate in transfers per second. Is there, apart from 'tradition' any ...
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Are PCIe and USB 3.0 the same interface?
I know the title may sound provocative, but I was looking for a PCI hub, and found solutions like these:
I noticed that on the PCIe side, there is actually only one adapter (which looks passive) with ...
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PCIe mode in chip-to-chip communication
In my understanding, the most common PCIe usage is in computer systems which involves a processor host communicating with various endpoints through the PCIe tree topology. In this scenario, we will ...
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OCULink connector pin configuration for Root port and endpoint
We are using an OCUlink connector for the PCIe x4 interface in one of our new design which should support both root port and endpoint. We have a few queries to clarify on the same.
When our board is ...
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PCIe Data Transfer Rate vs Fundamental Frequency
The PCIe Gen 3 standard states that the link works at 8GT/s, while the fundamental frequency of the LVDS signals is maximum 4GHz. To my understanding PCIe doesn't use any sort of DDR technology, so ...
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Phase 2 equalization for downstream port in PCIe
Could you please clarify the following?
In phase 2 equalization, upstream port evaluates downstream port transmitter. In these process first upstream port sends preset values to down stream port. Then ...
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PCIe Gen4: inter-pair skew: any limits?
For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either:
2 TX differential pairs (of different ...
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3.3V in PCIe connector
What is the 3.3V used for in PCIe edge connect?
I have a PCIe connector that has 3.3V and another one that does not have the 3.3V and both are working fine which brings me to wonder why the 3.3V is ...
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PCIe "RefClk" impedance requirements?
I'm designing a very heavy impedance-requiremented PCB, with PCIe v2.
I know TX and RX diffpairs have strict differential ...
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Impedance-critical diff-pair routing
I need to route PCIe RX and TX diffpairs:
I can't change the bottom connector (fits into M.2 KeyE socket), neither the top (M.2 KeyM socket).
Normally, how shall I wire these diffpairs?
It seems I ...
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Frequency of PCIe differential pairs (RX, TX, CLOCK)
I'm planning to design a board for PCIe (v2).
For all impedance matching considerations, there is rule-of-thumb: if you can decrease the trace lengths below 1/10 of the wavelength, you're probably ...
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Designing M.2 socket for SSD
I'm designing a card adaptor which converts from M.2 Key E type to M.2 Key M type (to insert an NVMe SSD into a port designed originally for Wifi cards).
I found some reference design for the M.2 KeyM ...
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Is PCIe IO address space meaningless for ARM-based system?
According to here, the PCI Express TLP (Transaction Layer Packet) can target 4 different address spaces.
My question is about the IO and memory address spaces.
As we know, the PCI specification was ...
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PCI Express Lane Reversal for REFCLK
PCI Express supports lane reversal for the lanes.
Can REFCLK+ and REFCLK- also be swapped? That is, connect REFCLK+ from one device to REFCLK- on the other?
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Reverse PCIe bifurcation possible (two x4 into one x8)? [closed]
I'm just curious if this is possible in real world applications and if it is, what is it called? Reverse PCIe bifurcation?
Context: We know an example of PCIe bifurcation is converting an x8 into two ...
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M2 Key E - can it host an NVMe SSD?
I found an SBC which has an M2 socket for WiFi cards. It's keying is E.
I couldn't decide whether I can plug an M2 NVMe SSD into this socket.
Key E normally has PCIe x2, which is not as fast as PCIe ...
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Trying to replace laptop's dGPU with eGPU. Is it possible?
I try to replace GT 840 dPGU with eGPU on V3-572PG mainboard for which I have circuit and boardview.
I'd desoldered dGPU. Then after study of boardview I could easy match pins from dGPU socket to pins ...
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What are these PCIe connectors that are slightly larger than SFF-8653 8i?
I have some computer motherboards that ware evidently a special-order for the ASRock Rack because the vendor does not have the model listed on their website, and when I contacted them they said they ...
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PCIe bus bandwidth
Calculate the bandwidth of a PCIe link with 8 lanes, 8b/10b encoding and 2.5 GHz frequency.
I tried the following formula but I am not sure of its correctness:
BW = lane data rate × encoding × no. of ...
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Can I connect one PCIE_CLKREQ# pin from SoC to two different devices?
In my design, I'm using VL805 USB 3.0 Host Controller which takes 1 lane of PCIe and outputs 4 ports of USB3.2 Gen 1.
The platform which I'm building is based on AMD V3000 CPU.
My question is, if ...
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What is the maximum height (thickness) per slot for a finished (soldered/populated) PCI express card?
The main question is:
Defined by maximum allowable height from the surface of the PCB on both sides (soldered pins and components), or whatever metric experts think would be most useful in decoding an ...
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What do I have to transmit to get digital audio out of a PCIe lane?
I want to get audio out of the PCIe lane and I can't find any chip made solely for this purpose (if you have a suggestion please tell me).
I took it upon myself to design and build it, but I don't ...
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PCIe Present pin working principle
I have a doubt about the PCIe present pin working principle, As shown in the below image which is taken from PCI_Express_CEM_r3.0 Specification, How the Hot-plug control logic will detect the PCIe ...
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Performance difference when comparing PCIe DMA vs. MMIO for same data access size
Some PCIe devices can map their own device memory region fully to contiguous host physical memory address space through a feature called PCIe Resizable BAR (base address register), which makes it ...
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PCIe Domain,Bus,Device,Function limits
I am new to PCIe, I would like to understand 256(Bus), 32(Device), 8(Functions). I am trying to visualise these ...
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Why don't WD NVMe SSDs have PCIe AC coupling capacitors?
I see no coupling capacitors on PCIE TX lanes.
Is it Safe to Remove Coupling Capacitors?
Or
Is it possible to make capacitors into the chip?
Add more photos：
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Will PCIe Host issue configuration read / write type of transaction other than the enumeration phase?
With my limited understanding, the PCIe end point and it's feature capability will be discovered by the host during enumeration phase. Hence, I believe most of the configuration type of write and read ...
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Is compliance testing necessary for PCIE3.0 if the SOC and Wi-Fi chipset is on the same board?
In my product, PCIe is just used for data transmission between SOC and Wi-Fi chipset. It's not used for any other purpose. Is compliance testing necessary for this scenario?
What type of SI ...
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Linking WiFi MCU to Ethernet PHY via PCIe
I'm trying to link this Ethernet PHY to this WiFi 6 MCU via PCIe to make a single port router.
Can I directly connect these two, or do I need some kind of host CPU with two PCIe slots to link them?
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PCIe to FPGA IC
My company is looking to replace an old design that uses the now obsolete PEX 8311 to go from PCIe to a very custom optical protocol (through an FPGA). My initial plan was to use an FPGA with ...
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How does using an RS232 splitter affect the data transfer speed?
I am converting digital data into an analog signal through the RS232 PCIE card I added to my PC. I have a desire to collect data from up 8 different RS232 connections and I am looking into using an ...
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How are BAR registers handled between end points in PCI Express?
I have a question related to the PCI Express protocol.
I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process.
I know the ...
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Can I use a 250 nF instead of a 200 nF SMD ceramic capacitor?
Im trying to fix a broken GPU that has a missing 200 nF SMD ceramic capacitor. I found a similar one on a motherboard that has a capacitance of 250 nF. Is it possible to transfer it to fix the GPU?
At ...
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Pinout question: Is this just a PCIe x8 slot in a proprietary card position?
Can anyone tell if this is just a normal PCIe x8 slot in a funny position, or is it also an unusual (incompatible) pinout?
The differential pairs and the number of pins look about right but I thought ...
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Remapping a PCI(e) device when another core is accessing the device
According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)?
If not, ...
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mPCIE & mSATA 's coupling capacitors
What I am doing is making mPCI-E and mSATA work together in one slot on my Xilinx FPGA. PCIE always only have coupling capacitors on the TX sides(RX sides's capacitors is on the Endpoint Devices), ...
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Mini-PCIe Signal Voltage Levels
Can PERST, CLKREQ, WAKE#, and SMBUS operate at 1.8 V? What I am designing is a mini-PCIe slot compatible with a WWAN card, but this WWAN card can only operate at 1.8 V.
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Studying the PCIe/CXL/CCIX internals at home
Could anybody recommend me a good starting point for self-studying the PCIe internals?
I imagine some kind of an FPGA-based course, covering PCIe endpoint, root complex and switching functionalities. ...
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PCIe power requirements and total capacitance
I'm going straight to the point. In the PCIe CEM specification, regarding to +12V supply, they appear different maximum values of the allowed capacitance depending of the power of the card (10,25 or ...
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What is the purpose of these strange patterns in i/o port panel of GPU card? [closed]
Ref: https://www.techspot.com/article/1988-anatomy-graphics-card/
The left side pattern seems to get it attached to Graphics card slot- but not sure why those flanges are required.
Absolutely no ...
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How to interface two Raspberry Pi CM4 modules and a SOM CN9130 module
I am working on project that requires two Raspberry Pi CM4 modules and a SOM CN9130 module to communicate each other with a data speed of 1GBPS.
Both modules have Ethernet and support the PCIe bus.
...
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Do PCI Express devices' interrupts always go through a PIC or an APIC?
My Question is PCI/PCIe interrupt path to CPU is through a PIC or an APIC?
https://people.freebsd.org/~jhb/papers/bsdcan/2007/...
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Serial Interfaces - Why USB and PCIe require PHY while e.g. SPI does not require?
I'm trying to understand the reason why USB and PCIe (considering a single lane) can achieve higher data rates than e.g. SPI, I2C, UART.
The reason may be the better handling of signal impairments at ...
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PCIe End-Point configuration for communication with Root Complex
I have an ambiguity regarding the PCIe initial configuration which is performed by the root complex (RC) on the end-points (EP).
Both devices have their own base address registers (BARs). The RC ...
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