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Questions tagged [pcie]

PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.

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37 views

PCIe gen3 over a FMC connector

I am thinking to connect PCIe devices to my FPGA board via FMC connector (using a PCIe to FMC adapter). Will I get full PCIe bandwidth for those devices on the FMC connector? Not considering FPGA ...
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14 views

Is an IOMMU a part of the PCIe or the other way around?

AFAIK, the PCI is just another bus that can serve as the parent bus for others like USB but is nevertheless capable of just being a standalone bus without any bridges as well. Also the PCIE comes with ...
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What is the role of the ROOT COMPLEX in a microprocessor system (PCI Express)

I have been learning about the Linux kernel and the most common bus type i always encounter is the PCI bus. As an electronics Engineer, i decided to look at how this bus works as it seems to be the ...
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43 views

How to choose a right user interface in PCIe DMA subsystem (AXI Memory Map / AXI Streaming)

Looking at the PCIe DMA solution offered by different FPGA vendors, there are 2 main user-interface options: 1) AXI Memory Map (Altera use Avalon-MM) 2) AXI Streaming (Altera use Avalon-ST) Using ...
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48 views

How exactly does CPU set C/BE lines on a PCI bus?

In the PCI bus spec, when in the address phase of a transaction, there are extra bits for specifying the type of transaction (called C/BE). These lines are also re-used during the data phase of the ...
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45 views

Multi-channels DMA Subsystem for PCI Express

Say i have a PCIe Gen2 x4 link running in a DMA subsystem. May I know when do we need multi-channels DMA configuration? For example, FPGA vendor like Xilinx offer up to 4-read & 4-write data ...
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2answers
33 views

How to inteprepret jumper confiuration guide on PCB?

So I have a M.2 to mPCIe adapter board that unfortunately I don't have any documentation for. The purpose of the board is to allow for a 4g M.2 modem to connect to a PC with a mPCIe slot. Presumably ...
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1answer
69 views

How many pins does a PCI x4 connection needs in a FPGA?

I am new to the FPGA world. Reading the specs for variuos FPGAs I see there are lots of transceivers. I have a number of PCIe x.4 devices. How many pins and/or transceivers do I need to connect to one ...
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3answers
45 views

Multiple PCIe Functions in Real User Applications (EP mode)

According to PCIe specification, a PCIe device may contain a collection of up to 8 functions. If a PCIe is configured to a specific endpoint, under what circumtances does it need multiple functions? ...
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59 views

PCI-e jtag interface [closed]

I am looking for information on JTAG interface on PCI-e 1x connector. Do anyone has an informaton how to program it? I would like to use it to program microcontrollers and FPGAs.
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57 views

Question about PCI-E gold finger fanout

I'm planning a PCB project with PCI-E connector. After looking some docs about PCI-E. I find one problem about the fanout the PCI-E gold fingers, the X16 pinout defines as below (part of whole 164 ...
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1answer
37 views

Requirements for measuring PCIe 2.5GT eye diagram

What is suitable equipment for measuring an eye diagram of PCIe differential pairs. I would like to evaluate the signal integrity of a PCI lane RX/TX/CLK 2.5GT. What is the recommended minimum ...
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1answer
43 views

Understanding pci address in lspci/dmesg

When looking for the pci devices on the host machine, I have seen something like this in lspci: ...
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1answer
120 views

Minimum requirements to interact with PCI Express

I have a relatively simple project (from the user point of view) in mind. I want to develop a very simple PCI Express (x1) card that users can put into their system and toggle some GPIO's from a GUI ...
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122 views

What is the function of CLKREQ and PEWAKE when those are used in PCIE?

I could understand The CLKREQ# signal is used by the L1 PM Substates mechanism. And PEWAKE signal is used to wake up the ROOT COMPLEX(RC) during the sleep mode. And these two signals are bidirectional ...
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1answer
67 views

Requirements for PCIe Bifurcation on SBC

I'm looking for clarification on what actually needs to happen in order for a device to support PCIe bifurcation. Some forums say it's motherboard dependent, making me think it's not tied to the ...
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1answer
72 views

Does anybody have PCIe (3.0) aka PCI Express module card edge connector technical drawing? [duplicate]

I was searching through the internet to find PCI Express card edge connector footprints / technical drawings / pin spacing / layout of the module cards that you stick in these connectors you can find ...
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96 views

How to check (6 pin) PCI-E power rail on a pc powersupply?

Could anyone tell me if and how i might verify whether or not a PCI-Express 6 pin power lead on a PC is outputting correct voltage(s) ? A while back, I decided to try to refurbish a graphics card ...
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1answer
88 views

M.2 PCIe x2 and SATA connections and key/notch with SATA/PCIe x4 SSDs

For my current project I am adding an M.2 slot for additional storage. Even though SATA data throughput is more than sufficient I would like to support both SATA and PCIe based SSDs, as I dont know ...
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1answer
35 views

What are the options of PCIe dev boards these days? [closed]

do you know if there is any fpga PCIe dev board that would support adding/removing pcie capabilities and examining tlps?
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0answers
55 views

Powered riser safety for dual PSU, GPU system [closed]

I am very much a novice w/ electronics. I'm trying to evaluate these risers for use in a system where I need to add additional GPUs and a 2nd PSU (the first PSU is 1600W and maxed out w/ 4 GPUs, the ...
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1answer
67 views

PCIe - EqualizationPhase

In linux, do lscpi command: we can see LnkSta2: EqualizationComplete-, EqualizationPhase1- Sometimes the EqualizationPhase1 is EqualizationPhase1+. Can you ...
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51 views

6-Pin Battery Connector to 2 Wire Terminal Connection

I have a 16V 6-Pin battery. I am trying to get it so that I am going from a 6-pin connection to a 2 wire connection. I have been unable to find any adapter online so I went ahead and cut off the ...
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41 views

Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM ...
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2answers
161 views

Data Rate, Bandwidth and Data transfer Rate - PCIe

I was talking with my senior regarding PCIe speeds. I am not sure if what I was saying was right. Please correct me and help me understand. He asked what is PCIe gen3 data rate. I said 8GT/s. He ...
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1answer
93 views

PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
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249 views

FPGA configuration time and PCI Express

I'm designing a PCI Express board with an Artix-7 from Xilinx. I'm reading through the PCIe block description and on page 199 it says: Section 6.6 of PCI Express Base Specification, rev 1.1 states “...
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1answer
67 views

PIO communication in PCIE

I want to communicate with SPARTAN 6 FPGA through PCIE for data transfer using Programmed IO (PIO) method.I am confused with following questions. 1)What is the role of BAR reg in PIO design(while ...
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3answers
122 views

USB cable characteristic impedance

Does differential impedance between D+ and D- not only depends on separation between and wire gauge of D+ and D-, dielectric constant of the insulation, but also the GND wire and shielding? I want to ...
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1answer
720 views

Understand the Primary/Secondary/Subordinate Bus number in PCI/PCIe Bridge

I am new to the PCIe world. I am learning the enumeration and configuration of PCIe hierarchy. Some quote from here: For PCI-PCI bridges to pass PCI I/O, PCI Memory or PCI Configuration address ...
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0answers
42 views

When is a PCIE endpoint/card powered?

At what point in host boot process, does a PCIE endpoint get powered ? Is it powered as soon as the host/PC starts booting or when it starts the enumeration process ? References would be appreciated....
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1answer
217 views

Can anyone make a device that uses pcie?

As the title suggests, can anyone make a custom board that connects via a pcie connector? Do you need to purchase the rights/license to use it or is it all open to the public? For example my use ...
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1answer
216 views

Max power draw on voltage rails of mini PCIe Card

I am designing a custom mini PCIe card. What is the max power I can draw from the 1v5 rail, and the 3v3 rail?
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1answer
340 views

USB Camera to GPU Memory Directly

There may be several points in this question which may not make sense to a knowledgeable person, so I do thank you for your understanding in advance. For a computer vision project I wish to process ...
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1answer
71 views

Designing an PCIe ethernet NIC with built in ethernet switch

I am trying to design a ethernet network card that will plug into a PCIe slot and have 2 etherenet ports visible to the user that are connected by a unmanaged layer 2 switch. My architecture ...
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1answer
235 views

Avalon-ST PCIe root port in an FPGA

A buddy of mine and I have a project in which we have to implement a PCI Express rootport. I haven't read the entire specification, nor do I have the Mindshare book that everyone recommends, but I ...
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1answer
775 views

Does this PCIe routing look ok?

It is the first time for me to design a PCB with a PCIe bus. My first design failed, the bus is not working! Tom helped me in this question and instructed me how to correctly route a high speed bus - ...
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1answer
135 views

Ethernet controller not recognized on PCIe bus

I designed a carrier board for this SOM: https://wiki.solid-run.com/doku.php?id=products:ibx:documents As I need a second Ethernet port I added an Intel I217 Ethernet controller. Unfortunately it ...
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1answer
132 views

Why are PCIe Config Writes non-posted?

In PCIe, why are config writes non-posted? Why can't they be like mem_wr which are posted?
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1answer
186 views

PCB Design - Mini Pcie Express to Thunderbolt 1 2/Mini Display

What I want to achieve is to connect a Mini Pcie Express device to a thunderbolt (1 / 2) port. I have looked around and such connector does not seem to exist, so as a computer engineer I went looking ...
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2answers
1k views

PCI-E throughput calculation

could someone please do for me the calculation of total throughput of PCI-E? The best material I could find was a Xilinx pdf that mentioned 2.5Gbps as reference value and somewhat awkward formula that ...
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1answer
93 views

Help identifying a possible connector for these unterminated contacts on my HP Stream 14 motherbard

I'm trying to identify the appropriate connector for this bundle of unterminated contacts, from my HP Stream 14 motherboard. I'm talking about the red circled part of the motherboard: Here's a close ...
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1answer
441 views

Are there any pci-e controllers that take like a SPI signal, or USB and then lets me hookup a pci-e x1 card to it?

I am wondering if such a thing exists, as I could really use one to hookup to a SoC I am designing a board around, as it would allow me to take like a pci-e tv controller, pci-e ethernet card, pci-e ...
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1answer
232 views

What are the part numbers for PCI-E 8-pin and 6-pin power connectors?

https://upload.wikimedia.org/wikipedia/commons/a/af/PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg I believe they are Molex Mini-Fit series but I can't find the exact match. Thanks. ...
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1answer
641 views

What is the usable area (for connectors) of a PCI Express card bracket?

I have a number of awkwardly shaped connectors that I need to cram into a single PCI Express slot metal bracket without any of them colliding with the host PC case's metalwork. The connectors are a ...
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0answers
617 views

PCIe loopback testing

I have a design using PCIe 4 lanes that interface between 2 CCAs and will be connected through a connector/flex connection. In the event that the mate to either CCA is not available, I want to know ...
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2answers
259 views

PCI-e. Using raisers to turn 1x and 16x to two 8x

I am doing a supper-budget-ghetto computer project. Just wanted to ask a theoretical question: could spliced up risers be used to turn one 1x and one 16x slot to two 8x slots? I think they share a ...
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1answer
3k views

Why is there a little nose on the PCIe connector?

PCI express cards have an edge connector with a little notch in it to prevent the card from moving if the socket is longer than the connector. Additionally, the printed circuit board has a protrusion ...
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1answer
416 views

MXM to PCIe connector - help in understanding some of the MXM pins

I am trying to build a board to bridge the MXM slot in my laptop with a PCIe riser. Have just started working out which pins from the MXM slot should connect to which pin on a PCIe slot. I have put my ...
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1answer
2k views

What is the difference between full duplex and dual simplex? [closed]

What is the difference between full duplex and dual simplex? I can not really distinguish the difference. Is it the fact that in full duplex, data can be exchanged simultaneously in both channels ...