Skip to main content

Questions tagged [pcie]

PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.

Filter by
Sorted by
Tagged with
-1 votes
0 answers
29 views

Feeding data stream to FPGA using PCIe [closed]

I am trying to use PCIe with ultrascale+ device and feed the fpga with data stream and send it to another device using PCIe over SFP+ optical cable. However, I don't know how to feed data to the fpga (...
B.jawaher's user avatar
2 votes
1 answer
290 views

PCIe digest explanation

In the PCIe standard they wrote the TLP messages may have digest section. What is the digest of a TLP message described in the PCIe standard?
Hitab's user avatar
  • 95
7 votes
2 answers
961 views

PCIe implementation

I was reading about the PCIe stadard, it was mentioned about PCIe PHY, Switched, RootComplex and Bridges that make the PCIe fabric. I'm trying to connect the dots between the physical hardware and the ...
Hitab's user avatar
  • 95
0 votes
0 answers
21 views

CPU to Switch SGMII port with PCIE 2.5Gb

I can't seem to find a 2.5 Gbps Ethernet controller that could be a bridge between the SGMII+ port and PCIe. this is what I want to do: I don't want to use PHY (from the copper 2.5G to 2.5G SGMII) ...
Knowledge's user avatar
  • 441
0 votes
1 answer
33 views

Origin and underlying sense of the term "Posted" in PCIe

When PCI Express replaced the operation of reading directly from a PCI peripheral card over a bus, directly addressing its I/O ports, or performing a configuration cycle on it directly, with instead a ...
BobH's user avatar
  • 11
3 votes
4 answers
3k views

How many lanes of PCIe does Thunderbolt 4 use?

Searching shows that Thunderbolt 4 uses 4 lanes of PCIe 3.0; each lane should contain 3 twisted pairs, two for communication (TX and RX) and one for reference clock. The pinout of Thunderbolt 4 is ...
AlexGenesis's user avatar
3 votes
0 answers
73 views

Designing a U.2 to M.2 NVMe adapter

I'm considering designing my own U.2 to M.2 converter card to make use of the four U.2 (PCIe 3.0 x4) connectors on my motherboard. Commercial products are available for doing this type of conversion, ...
Polynomial's user avatar
  • 10.8k
0 votes
3 answers
200 views

Why can't software capture PCIE packets?

I found this question in Stackoverflow and the answers say: I don't believe so -- from a software viewpoint, PCI-E is quite well disguised to look like (fast) PCI. As far as I know, nearly the only ...
user1783484's user avatar
0 votes
0 answers
51 views

What is the effect of disabling the scrambling on PCIe link stability?

In PCIe base specification document, it is mentioned that Disabling scrambling is intended to help simplify test and debug equipment... I am implementing my own custom gen2 PCIe IP in Verilog and I ...
Im Groot's user avatar
  • 402
0 votes
2 answers
194 views

Problems in understanding PCIe blocks in Xilinx Vivado for Versal devices

AR 1215986 was mentioned on page 7 of PG344, Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide. In this AR, the author mentioned several components, namely: PCIe PHY GT QUAD ...
bruin's user avatar
  • 465
0 votes
0 answers
119 views

PCIe hotplug hardware schematics reference design

I was going through this link, this was very wonderful Does PCIe hotplug actually work in practice? Following the above link, I had a question below: I am looking for a "PCIe hotplug hardware ...
user1081342's user avatar
2 votes
2 answers
234 views

Can a PCIe Bridge connect to multiple downstream devices using different functions?

My understanding of PCIe bridges is as follows: A PCIe bridge appears as 1 device on the upstream bus, creates a new bus downstream of it, and whatever connects to the downstream side will appear as ...
shafe's user avatar
  • 363
2 votes
1 answer
742 views

Can someone explain to me why the math for PCIe bandwidth doesn't add up?

Since PCIe g1 x1 is based off PCI 32/66 bandwidth of 2133.33 Mb (...
Tcll's user avatar
  • 123
0 votes
0 answers
37 views

PCIe connector overhang

There are precise mechanical requirements for PCIe cards. Along the top edge, there's a 1mm strip where copper and components are not allowed. If you're designing a PCIe card, and have connectors and ...
UStralian's user avatar
0 votes
2 answers
95 views

Do extra PCIe lanes improve latency?

If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster. But if you never need ...
Maestro's user avatar
  • 981
1 vote
2 answers
87 views

PCIe Clock Buffer Daisy Chain

I have a PCIe clock buffer with 4 outputs that I would like to use for more than 4 PCIe devices. My question is can I daisy chain the buffers such that one buffer output is the input to the next ...
ztan's user avatar
  • 145
1 vote
0 answers
140 views

What is the typical NVME SSD abrubt shutdown reaction time for a CC.SHN event until power loss?

The NVME standard under "7.6.2 Shutdown" defines the procedure for an abrupt shutdown event: ...
mnemocron's user avatar
0 votes
1 answer
109 views

Why does PCIe still hold on to 'transfers/second' instead of bits/second or symbols/second?

I think it is kinda all covered in the title. To my (incomplete) knowledge, PCIe is the only modern bus that still expresses its rate in transfers per second. Is there, apart from 'tradition' any ...
Joren Vaes's user avatar
  • 12.6k
17 votes
4 answers
5k views

Are PCIe and USB 3.0 the same interface?

I know the title may sound provocative, but I was looking for a PCI hub, and found solutions like these: I noticed that on the PCIe side, there is actually only one adapter (which looks passive) with ...
Federico Massimi's user avatar
1 vote
2 answers
171 views

PCIe mode in chip-to-chip communication

In my understanding, the most common PCIe usage is in computer systems which involves a processor host communicating with various endpoints through the PCIe tree topology. In this scenario, we will ...
Learner's user avatar
  • 185
0 votes
0 answers
632 views

OCULink connector pin configuration for Root port and endpoint

We are using an OCUlink connector for the PCIe x4 interface in one of our new design which should support both root port and endpoint. We have a few queries to clarify on the same. When our board is ...
Chitharanjan's user avatar
1 vote
1 answer
620 views

PCIe Data Transfer Rate vs Fundamental Frequency

The PCIe Gen 3 standard states that the link works at 8GT/s, while the fundamental frequency of the LVDS signals is maximum 4GHz. To my understanding PCIe doesn't use any sort of DDR technology, so ...
Connor Sousa's user avatar
2 votes
1 answer
2k views

PCIe Gen4: inter-pair skew: any limits?

For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either: 2 TX differential pairs (of different ...
Sandro's user avatar
  • 7,697
5 votes
1 answer
2k views

3.3V in PCIe connector

What is the 3.3V used for in PCIe edge connect? I have a PCIe connector that has 3.3V and another one that does not have the 3.3V and both are working fine which brings me to wonder why the 3.3V is ...
Shannon's user avatar
  • 379
0 votes
1 answer
833 views

PCIe "RefClk" impedance requirements?

I'm designing a very heavy impedance-requiremented PCB, with PCIe v2. I know TX and RX diffpairs have strict differential ...
Daniel's user avatar
  • 969
2 votes
2 answers
359 views

Impedance-critical diff-pair routing

I need to route PCIe RX and TX diffpairs: I can't change the bottom connector (fits into M.2 KeyE socket), neither the top (M.2 KeyM socket). Normally, how shall I wire these diffpairs? It seems I ...
Daniel's user avatar
  • 969
0 votes
2 answers
287 views

Frequency of PCIe differential pairs (RX, TX, CLOCK)

I'm planning to design a board for PCIe (v2). For all impedance matching considerations, there is rule-of-thumb: if you can decrease the trace lengths below 1/10 of the wavelength, you're probably ...
Daniel's user avatar
  • 969
0 votes
1 answer
3k views

Designing M.2 socket for SSD

I'm designing a card adaptor which converts from M.2 Key E type to M.2 Key M type (to insert an NVMe SSD into a port designed originally for Wifi cards). I found some reference design for the M.2 KeyM ...
Daniel's user avatar
  • 969
7 votes
2 answers
1k views

Is PCIe IO address space meaningless for ARM-based system?

According to here, the PCI Express TLP (Transaction Layer Packet) can target 4 different address spaces. My question is about the IO and memory address spaces. As we know, the PCI specification was ...
smwikipedia's user avatar
  • 1,192
2 votes
1 answer
690 views

PCI Express Lane Reversal for REFCLK

PCI Express supports lane reversal for the lanes. Can REFCLK+ and REFCLK- also be swapped? That is, connect REFCLK+ from one device to REFCLK- on the other?
Greg's user avatar
  • 23
2 votes
2 answers
425 views

Reverse PCIe bifurcation possible (two x4 into one x8)? [closed]

I'm just curious if this is possible in real world applications and if it is, what is it called? Reverse PCIe bifurcation? Context: We know an example of PCIe bifurcation is converting an x8 into two ...
karll's user avatar
  • 21
3 votes
2 answers
6k views

M.2 Key E - can it host an NVMe SSD?

I found an SBC which has an M.2 socket for WiFi cards. It's keying is E. I couldn't decide whether I can plug an M.2 NVMe SSD into this socket. Key E normally has PCIe x2, which is not as fast as ...
Daniel's user avatar
  • 969
1 vote
0 answers
168 views

Trying to replace laptop's dGPU with eGPU. Is it possible?

I try to replace GT 840 dPGU with eGPU on V3-572PG mainboard for which I have circuit and boardview. I'd desoldered dGPU. Then after study of boardview I could easy match pins from dGPU socket to pins ...
Daro's user avatar
  • 11
1 vote
0 answers
127 views

What are these PCIe connectors that are slightly larger than SFF-8653 8i?

I have some computer motherboards that ware evidently a special-order for the ASRock Rack because the vendor does not have the model listed on their website, and when I contacted them they said they ...
MikeSchinkel's user avatar
-1 votes
1 answer
146 views

PCIe bus bandwidth

Calculate the bandwidth of a PCIe link with 8 lanes, 8b/10b encoding and 2.5 GHz frequency. I tried the following formula but I am not sure of its correctness: BW = lane data rate × encoding × no. of ...
Mina Mounir Farid Gendi's user avatar
1 vote
0 answers
38 views

Can I connect one PCIE_CLKREQ# pin from SoC to two different devices?

In my design, I'm using VL805 USB 3.0 Host Controller which takes 1 lane of PCIe and outputs 4 ports of USB3.2 Gen 1. The platform which I'm building is based on AMD V3000 CPU. My question is, if ...
Firas Abd El Gani's user avatar
2 votes
1 answer
3k views

What is the maximum height (thickness) per slot for a finished (soldered/populated) PCI express card?

The main question is: Defined by maximum allowable height from the surface of the PCB on both sides (soldered pins and components), or whatever metric experts think would be most useful in decoding an ...
Rook's user avatar
  • 184
0 votes
1 answer
105 views

What do I have to transmit to get digital audio out of a PCIe lane?

I want to get audio out of the PCIe lane and I can't find any chip made solely for this purpose (if you have a suggestion please tell me). I took it upon myself to design and build it, but I don't ...
William Brown's user avatar
0 votes
1 answer
1k views

PCIe Present pin working principle

I have a doubt about the PCIe present pin working principle, As shown in the below image which is taken from PCI_Express_CEM_r3.0 Specification, How the Hot-plug control logic will detect the PCIe ...
Chitharanjan's user avatar
2 votes
1 answer
1k views

Performance difference when comparing PCIe DMA vs. MMIO for same data access size

Some PCIe devices can map their own device memory region fully to contiguous host physical memory address space through a feature called PCIe Resizable BAR (base address register), which makes it ...
hurryman2212's user avatar
0 votes
2 answers
406 views

PCIe Domain, Bus, Device, Function limits

I am new to PCIe. I would like to understand 256 (bus), 32 (device), 8 (function). I am trying to visualise these PCIe slots on a motherboard. I am used to desktop motherboards where we have one ...
Franc's user avatar
  • 93
2 votes
3 answers
999 views

Why don't WD NVMe SSDs have PCIe AC coupling capacitors?

I see no coupling capacitors on PCIE TX lanes. Is it Safe to Remove Coupling Capacitors? Or Is it possible to make capacitors into the chip? Add more photos:
Jue WANG's user avatar
1 vote
2 answers
280 views

Will PCIe Host issue configuration read / write type of transaction other than the enumeration phase?

With my limited understanding, the PCIe end point and it's feature capability will be discovered by the host during enumeration phase. Hence, I believe most of the configuration type of write and read ...
Learner's user avatar
  • 185
2 votes
0 answers
43 views

Is compliance testing necessary for PCIE3.0 if the SOC and Wi-Fi chipset is on the same board?

In my product, PCIe is just used for data transmission between SOC and Wi-Fi chipset. It's not used for any other purpose. Is compliance testing necessary for this scenario? What type of SI ...
Sai's user avatar
  • 29
1 vote
1 answer
146 views

Linking WiFi MCU to Ethernet PHY via PCIe

I'm trying to link this Ethernet PHY to this WiFi 6 MCU via PCIe to make a single port router. Can I directly connect these two, or do I need some kind of host CPU with two PCIe slots to link them? ...
cdubs's user avatar
  • 425
2 votes
1 answer
220 views

PCIe to FPGA IC

My company is looking to replace an old design that uses the now obsolete PEX 8311 to go from PCIe to a very custom optical protocol (through an FPGA). My initial plan was to use an FPGA with ...
sbell's user avatar
  • 1,661
1 vote
1 answer
387 views

How does using an RS232 splitter affect the data transfer speed?

I am converting digital data into an analog signal through the RS232 PCIE card I added to my PC. I have a desire to collect data from up 8 different RS232 connections and I am looking into using an ...
PositiveSlope's user avatar
7 votes
3 answers
3k views

How are BAR registers handled between end points in PCI Express?

I have a question related to the PCI Express protocol. I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process. I know the ...
Joseph Star's user avatar
6 votes
3 answers
2k views

Can I use a 250 nF instead of a 200 nF SMD ceramic capacitor?

Im trying to fix a broken GPU that has a missing 200 nF SMD ceramic capacitor. I found a similar one on a motherboard that has a capacitance of 250 nF. Is it possible to transfer it to fix the GPU? At ...
LuisCorner's user avatar
2 votes
1 answer
170 views

Pinout question: Is this just a PCIe x8 slot in a proprietary card position?

Can anyone tell if this is just a normal PCIe x8 slot in a funny position, or is it also an unusual (incompatible) pinout? The differential pairs and the number of pins look about right but I thought ...
KJ7LNW's user avatar
  • 2,056

1
2 3 4 5 6