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Questions tagged [pcie]

PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.

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How to convert PCI express to PCI-x [migrated]

I have a part that outputs PCI-x. My mother board only takes PCI-express. I was wondering if there is a way to convert PCI express to PCI-X?
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6-Pin Battery Connector to 2 Wire Terminal Connection

I have a 16V 6-Pin battery. I am trying to get it so that I am going from a 6-pin connection to a 2 wire connection. I have been unable to find any adapter online so I went ahead and cut off the ...
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Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM ...
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1answer
36 views

Data Rate, Bandwidth and Data transfer Rate - PCIe

I was talking with my senior regarding PCIe speeds. I am not sure if what I was saying was right. Please correct me and help me understand. He asked what is PCIe gen3 data rate. I said 8GT/s. He ...
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1answer
65 views

PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
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93 views

FPGA configuration time and PCI Express

I'm designing a PCI Express board with an Artix-7 from Xilinx. I'm reading through the PCIe block description and on page 199 it says: Section 6.6 of PCI Express Base Specification, rev 1.1 states “...
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22 views

PIO communication in PCIE

I want to communicate with SPARTAN 6 FPGA through PCIE for data transfer using Programmed IO (PIO) method.I am confused with following questions. 1)What is the role of BAR reg in PIO design(while ...
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2answers
72 views

USB cable characteristic impedance

Does differential impedance between D+ and D- not only depends on separation between and wire gauge of D+ and D-, dielectric constant of the insulation, but also the GND wire and shielding? I want to ...
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1answer
292 views

Understand the Primary/Secondary/Subordinate Bus number in PCI/PCIe Bridge

I am new to the PCIe world. I am learning the enumeration and configuration of PCIe hierarchy. Some quote from here: For PCI-PCI bridges to pass PCI I/O, PCI Memory or PCI Configuration address ...
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36 views

When is a PCIE endpoint/card powered?

At what point in host boot process, does a PCIE endpoint get powered ? Is it powered as soon as the host/PC starts booting or when it starts the enumeration process ? References would be appreciated....
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116 views

Can anyone make a device that uses pcie?

As the title suggests, can anyone make a custom board that connects via a pcie connector? Do you need to purchase the rights/license to use it or is it all open to the public? For example my use ...
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1answer
110 views

Max power draw on voltage rails of mini PCIe Card

I am designing a custom mini PCIe card. What is the max power I can draw from the 1v5 rail, and the 3v3 rail?
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216 views

USB Camera to GPU Memory Directly

There may be several points in this question which may not make sense to a knowledgeable person, so I do thank you for your understanding in advance. For a computer vision project I wish to process ...
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1answer
52 views

Designing an PCIe ethernet NIC with built in ethernet switch

I am trying to design a ethernet network card that will plug into a PCIe slot and have 2 etherenet ports visible to the user that are connected by a unmanaged layer 2 switch. My architecture ...
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1answer
180 views

Avalon-ST PCIe root port in an FPGA

A buddy of mine and I have a project in which we have to implement a PCI Express rootport. I haven't read the entire specification, nor do I have the Mindshare book that everyone recommends, but I ...
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1answer
662 views

Does this PCIe routing look ok?

It is the first time for me to design a PCB with a PCIe bus. My first design failed, the bus is not working! Tom helped me in this question and instructed me how to correctly route a high speed bus - ...
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1answer
114 views

Ethernet controller not recognized on PCIe bus

I designed a carrier board for this SOM: https://wiki.solid-run.com/doku.php?id=products:ibx:documents As I need a second Ethernet port I added an Intel I217 Ethernet controller. Unfortunately it ...
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82 views

Why are PCIe Config Writes non-posted?

In PCIe, why are config writes non-posted? Why can't they be like mem_wr which are posted?
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207 views

OCuLink pinout: how does BP TYPE singal work?

I need to use an OCuLink connection to carry a 4x PCIe link from a motherboard/adapter card (like this one https://www.supermicro.com/products/accessories/addon/AOC-SLG3-2E4T.cfm) to a custom board. ...
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113 views

PCB Design - Mini Pcie Express to Thunderbolt 1 2/Mini Display

What I want to achieve is to connect a Mini Pcie Express device to a thunderbolt (1 / 2) port. I have looked around and such connector does not seem to exist, so as a computer engineer I went looking ...
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2answers
765 views

PCI-E throughput calculation

could someone please do for me the calculation of total throughput of PCI-E? The best material I could find was a Xilinx pdf that mentioned 2.5Gbps as reference value and somewhat awkward formula that ...
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1answer
90 views

Help identifying a possible connector for these unterminated contacts on my HP Stream 14 motherbard

I'm trying to identify the appropriate connector for this bundle of unterminated contacts, from my HP Stream 14 motherboard. I'm talking about the red circled part of the motherboard: Here's a close ...
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1answer
382 views

Are there any pci-e controllers that take like a SPI signal, or USB and then lets me hookup a pci-e x1 card to it?

I am wondering if such a thing exists, as I could really use one to hookup to a SoC I am designing a board around, as it would allow me to take like a pci-e tv controller, pci-e ethernet card, pci-e ...
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142 views

What are the part numbers for PCI-E 8-pin and 6-pin power connectors?

https://upload.wikimedia.org/wikipedia/commons/a/af/PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg I believe they are Molex Mini-Fit series but I can't find the exact match. Thanks. ...
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1answer
396 views

What is the usable area (for connectors) of a PCI Express card bracket?

I have a number of awkwardly shaped connectors that I need to cram into a single PCI Express slot metal bracket without any of them colliding with the host PC case's metalwork. The connectors are a ...
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508 views

PCIe loopback testing

I have a design using PCIe 4 lanes that interface between 2 CCAs and will be connected through a connector/flex connection. In the event that the mate to either CCA is not available, I want to know ...
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217 views

PCI-e. Using raisers to turn 1x and 16x to two 8x

I am doing a supper-budget-ghetto computer project. Just wanted to ask a theoretical question: could spliced up risers be used to turn one 1x and one 16x slot to two 8x slots? I think they share a ...
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1answer
3k views

Why is there a little nose on the PCIe connector?

PCI express cards have an edge connector with a little notch in it to prevent the card from moving if the socket is longer than the connector. Additionally, the printed circuit board has a protrusion ...
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331 views

MXM to PCIe connector - help in understanding some of the MXM pins

I am trying to build a board to bridge the MXM slot in my laptop with a PCIe riser. Have just started working out which pins from the MXM slot should connect to which pin on a PCIe slot. I have put my ...
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1answer
1k views

What is the difference between full duplex and dual simplex? [closed]

What is the difference between full duplex and dual simplex? I can not really distinguish the difference. Is it the fact that in full duplex, data can be exchanged simultaneously in both channels ...
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1answer
232 views

USB 3.1 over PCIe board edge connector

I am designing a system with a carrier board that has all of active logic on one board and most connectors on a backplane board. The interface between the two boards is a x16 PCIe board edge connector....
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219 views

SPI flash bit-banging access over memory-mapped IO

I'm faced with a problem where we have an SPI NOR flash attached to an Intel I210 PCIe-ethernet adapter on a custom Cortex A9 based board. The SPI flash is normally used by the ethernet adapter to ...
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1answer
141 views

PCIE branching not detecting PCIe device [closed]

I am facing an issue with the PCIe in my circuit. The PCIe detection is not happening. We are using an imx6q processor board plugged into our carrier board . The processor board comes with option of ...
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371 views

Why DMI instead of a PCIe link

In some Intel chipsets the CPU is connected to the Platform Controller Hub (PCH) by a link called Direct Media Interface (DMI). Based on what I found when researching about it, It's a link very ...
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1answer
440 views

M.2, WiFi pins and bus

I am trying to gather some info about the M.2 connector. My end goal is to add Wifi capabilities (e.g. using an Intel Pro Wireless M.2 card) to a Computer On Module system (iMX6, raspberry pi cm3, ...
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2answers
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How to discern quality of a breakout board? other than proper soldering on back of board [closed]

I see three different breakout boards for a project I am doing yet I am not sure which one to pick. How would i know which is of higher quality? I do see a metal circle inserts in board two and ...
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PCIe Layout and Signal Routing

I'm looking to build a simple board that has a 16x PCIe connector, that seats a compatible PCIe video card. I can find the connectors and create a footprint, on the board. I can find and understand ...
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1answer
141 views

Anyone knows how X86 platform set the PCIe bifurcation at boot up?

I got a question about the PCIe bifurcation setting when booting up in X86 system. Normally, we can set the PCIe controller to be X16, two X8, or four X4 in the UEFI shell menu. However, there is an ...
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1answer
130 views

PCIe DMA transcation to multiple PC RAM slots from FPGA

An FPGA endpoint needs to needs to transfer large quantities of data to the host processor's RAM over DMA. So memory mapping to a single RAM might not be possible. Normally high end PCs or Servers ...
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2answers
506 views

How can I use an Nvidia GPU with an open-source embedded board? [closed]

Is it possible by any means or method, to use an Nvidia GPU with an (probably open-source) embedded board? If yes, how do I go about achieving that? I have a few ideas but I'm just a beginner, hence ...
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1answer
51 views

Chipsets that provides access to baseband bits [closed]

Are there any chipsets for high-speed wired connections like USB3.0, Ethernet or PCIe that provides access to the raw signals being transmitted and received along the wire? Kind of like how a software ...
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1answer
195 views

IS it posible to emulate firmware? [closed]

Currently, i've been trying to work on virtualizing a motherboard from an old Lucent BZ5000 equipment, my idea is to emulate the BIOS from that equipment on a modern PC and be able to connect ...
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1answer
533 views

PCIe link training

I got few questions about PCIe link training procedure. For Gen3, will the host and device link to each other with Gen1 speed first, and when link up, host will look for device's capability register ...
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1answer
797 views

Lane Reversal on PLX PCIe Switches

I'm currently designing a carrier board on which is integrated a PLX PEX 8750 PCIe switch connected to several PCIe connectors. The problem occurs when routing PCIe lanes, since I can't route them ...
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1answer
376 views

PCIe Channel Multiplexing

According to Wikipedia PCI Express 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane 985MBps * 8 = 7880MBps (63Gbps). If I am using a 10Gbps Ethernet NIC with PCIe 3.0 8x interface ...
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1answer
362 views

Pc lpt (parallel) port input pin, how much current does it draw

I need some help to understand what's going on with my project: I am building an cnc machine and i use the parallel port to communicate with it... I use the native port to drive the motors and ...
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1k views

PCI device address actually means slot address? And when does PCIe slot get its' address?

I'd like to clarify how the configuration address space in PCI and PCIe works. Namely, a PCI peripheral on a bus is addressed with device:function pair (the ...
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3answers
542 views

Generic name for Molex(tm) Mini-Fit Jr(tm)? Standard definition?

The PC industry uses a large variety of power connectors which were originally introduced by Molex, using their trademarked (and search-engine unfriendly) brand name "Molex Mini-Fit Jr". This started ...
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1answer
417 views

Confusion about “host bus controller” and “host bridge”

Below part is quoted from the book "Beyond BIOS". Each host bridge is represented in EFI as a device handle that contains a Device Path Protocol instance, and a protocol instance that abstracts ...
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1answer
320 views

Understanding PCIE and FPGA clock “magic”

I've been trying to understand how PCIE clocking works when it comes to connecting an FPGA to a PCIE slot in a motherboard. Looking at page 12 of this schematic for exampe: https://www.xilinx.com/...