Questions tagged [phy]
The phy tag has no usage guidance.
119
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End to end and Peer to peer transparent clock
In the datasheet of LAN9353, the description states that it supports "supports end-to-end and peer-to-peer transparent clocks"
Can someone tell me what is the meaning of this?
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What is the standard common mode voltage of Media Dependent Interface MDI[0:3]± signals?
I am working on the selection RJ45 connector for MDI interface between PHY and the link-partner.
I am planning to use this PHY for my SGMII interface application. From various online readings, I ...
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Normal Switch and LAN9353
I am reading about the different types of LAN Switches.
And I came across the LAN9353 device - Link
I want to understand the difference between a normal Gigabit Ethernet 3 port switch and this LAN9353 ...
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Ethernet Switch and QoS Support
I'm going through the Ethernet Switch IC - Link
In the first page, under highlights section, it is mentioned as switch is QoS support.
When I tried to research on what QoS means on this Link, I found ...
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Differential signalling [duplicate]
This is a similar question to one over here. Posting a new question here, assuming that my question was not clear in that.
Can we split a differential signal into 2?
Assume the below image:
I'm using ...
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3
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Splitting of a differential signal
Can the Ethernet Tx and Rx signals (Using all 4 pairs; RGMII interface) be split into 2 so as to connect to 2 RJ-45 connectors, but only 1 will be used at a time. In general, can we split any ...
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KSZ8081 PHY address configuration
I'm using this KSZ8081 PHY transceiver.
I'm unable to understand how to configure the PHYAD[0:2] pin and the B-CAST_OFF pin.
As far as I read, the PHY Broadcast address will always be "0" ...
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57
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Ethernet Switch configuration mode
I'm trying to understand the Ethernet Switch product.
On page 54,55, we can see that, the MAC signals, Like for MII and RMII interface, we can understand that the digital MAC port 3, can be configured ...
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RX_ER peripheral not used in RMII
I'm using this PHY and MAC in this Controller
The Controller does not have the ENET_RX_ER peripherals in the 100 pin package.
In that case, can we handle the RX_ER in RMII interface using a GPIO port ...
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60
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Media Independent Interface
I'm reading about the PHY, MAC and the MII interface.
I understand that the MDI interface from the RJ-45 to PHY will be 10Mbps, 100Mbps or even higher to 1Gbps.
But when this data signals move to the ...
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46
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Ethernet 100 BASE-TX Question
I'm using this Ethernet transceiver PHY to study the working of the RGMII interface.
I just want to understand 2 things.
1. What would be the output and input differential voltage levels on the pins 2,...
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Marvell 88E6097F switch and AR8033 PHY
I'm trying to design a 6-port Fiber switch. For this I chose the MARVELL 88E6097F which is an 8-port switche+3GE.
My problem is that the CPU (IMX8M-P) comes out from the SOM with a PHY (AR8033).
Is it ...
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2
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46
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Ethernet PHY - Buffer Type
I'm going through the datasheet of this PHY Transceiver LAN8701A
On Page 14, table 2.2, it is mentioned as buffer types.
This is the first time I'm coming across the table called buffer types.
Can ...
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Line coding - The purpose and advantages [closed]
I'm reading about the line codes and probably confusing them with combining data and clock.
I've read the answers to this question and a few others along with Wiki pages but unable to get a clear ...
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68
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Clock recovery circuit in 100base-t / 1000base-t
I'm trying to understand the ethernet interface.
My understanding is that Ethernet is an asynchronous interface since there is no explicit clock signal transmitted along with data.
So, when there is ...
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Why do we need to use a 100ohm differential probe to measure ethernet signals when there is not any standard?
I was going through the debugging techniques of ethernet signals and found that we can capture the ethernet signals using a 100ohm differential probe.
Why do we need to add 100ohms on the ...
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2
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218
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Media Independent Interface Signals
For the MII interface signals:
I read in Wikipedia - MII on the Tx and Rx signals.
But I am confused on why there are two clocks (for tx and rx)?
Are the directions mentioned for transmitter signals ...
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42
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Clock data recovery waveform
I've read that a CDR block recovers clock from the data stream. Clock Data Recovery
Can someone show me a waveform on how its done? Like the carrier wave and modulation wave in FM and AM techniques, ...
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67
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Gigabit Ethernet 1000BASE-T and Fast Ethernet 100BASE-T
I have this basic question.
Gigabit ethernet has two things - 1000BASE-T and 1000BASE-TX.
And Fast Ethernet has 100BASE-T.
Ethernet has 4 twisted pairs. Can someone tell me which are half duplex and ...
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2
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100 BASE Tx Ethernet question
I am going through this Wikipedia article - Fast Ethernet and got this below table.
Can someone please explain why there are 3 line codes : 4B5B, MLT3 and NRZ-I done? Why all 3 are done?
Also can ...
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Ethernet PHY design considerations
I've started to read about Ethernet PHYs and reading the documents and articles available on the web.
I've 2 questions:
I read that the IEEE 802.3 Standard specifies that the copper cables should be ...
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63
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What values should be checked for SGMII signal compatibility?
How can I verify the DC electrical compatibility of the SGMII signal between PHY and MAC (within FPGA)?
Here is the reference-design that I am working on. Page 40 is using a Marvel PHY that is ...
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KSZ9021 PHY Routing
I am using a KSZ9021 component. I would like to ask about PHY routing rules.
Between the MAC and the PHY, what are the length matching requirements for TXD0, TXD1, RXD0, RXD1, MDC, MDIO, and REFCLK?
...
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Connect 100Mbit GMAC to a 1Gbit GMAC VSC8211
I would like to connect a 100Mbit GMAC on the SAMe70 with a 1000BASE-SX Switch. What will happen if I connect VSC8211 to this device and then attach a 1000BASE-SX Switch?
Will the Autoneg on the ...
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203
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Ethernet switch IC ports in MAC and PHY mode
I come from analog/RF background and have limited knowledge in digital interfaces.
According to TI's articles about Ethernet PHY found here and here, single MAC to single PHY connection seems very ...
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158
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What does "PHY" refer to?
I have seen the abbreviation PHY beeing used for a handful of different things within the context of Ethernet:
a PHY is a type of Ethernet physical layer (eg. 100BASE-TX, 10BASE-T)
a PHY is an ...
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85
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Connect a GMAC to another GMAC
I am looking into the KSZ9893 3-port switch. It has two(2) ports 10/100/1000 PHY. And one(1) GMAC with RGMII/RMII/MII interface. When I check the schematic of the SAMA5D3 Evaluation board they connect ...
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FPGA-based SSD host controller without transceivers
Problem: I am looking for options to design a host controller for SSD (SATA or nVME) using transceiver-less FPGA.
Question: What are the current state-of-the-art practices of doing such designs?
My ...
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Crystal Oscillator for STM32F407 with LAN8720
I'm planning to build a custom board with STM32F407 chip for a system where I also need Ethernet connectivity.
I'm planning to connect this board to a LAN8720 with breakout board from Smart ...
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174
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How to connect Ethernet Magnetic/RJ45
I am connecting up my PHY to an RJ45 with magnetics and was wondering what I do with some pins on it.
Here is the circuit for the Rj45 w/ magnetics.
My questions are:
do I connect pin 10 to the ...
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1000Base-KX PHY
I am having trouble finding an Ethernet PHY that specifically advertises as being compliant with 1000Base-KX (to be sent over a VXP backplane, a single RX pair and a single TX pair).
I found a comment ...
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Capacitive coupling Ethernet on backplane
Sorry in advance I am fairly new to the electronics world and Ethernet signaling. I am a physics postgrad student doing some hardware work rather than an electronics engineering background.
I have to ...
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639
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Does "USB FS PHY / USB HS ULPI" imply double usb capabilities when using an external USB PHY?
Some microcontrollers, for example the common STM32 line, claim USB capabilities along these lines:
USB 2.0 OTG HS, that is, USB 2.0 FS/HS device/host/OTG controller, integrating the transceivers for ...
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ESD protection on 10/100/1000 ethernet
I am designing a PCB with an RJ45, discrete magnetics and an ethernet phy that can support 10/100/1000 speeds. I am considering the implementation of ESD/TVS diodes. For this I gathered the following:
...
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MDIO bus max fanout
I know that the maximum number of devices that can be connected via MDIO bus is 32. But how to determine the real maximum fanout of MDIO bus. I mean I have a PCB (6U size) that has AM335x SoC driving ...
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Ethernet Magnetics CT pin shorting issue and the fix
We have a design where a voltage mode 1GbE PHY is driving the magnetics and the link is intermittent. Upon inspection it turned out the CT pins on the primary side of magnetics are all shorted as ...
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How to connect a ENC28J60 or ENC424J600 to a KSZ8091 PHY and from PHY to an unmanged strapped configuration to a KSZ8863 or other switch
How would one go about connecting MAC chip to a PHY and then to a switch for dual ports for daisy chaining? Rather be a strapped configuration for use in unmanaged mode so no need for MCU software ...
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158
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Connection Ethernet MACs without using a PHY device
I am designing a board that utilizes an NXP LS1046a processor and multiple Kintex Ultrascale FPGAs. The plan is to connect the processors up to the three FPGAs via the 1Gbe links.
Since they are all ...
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669
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RTL8152B Ethernet PHY heating up
We are using RTL8152B ethernet to USB PHY for one of our projects, After debugging the board I found the IC to be abnormally warm even when there is no network traffic. I probed using the Multimeter ...
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Impedance/Termination of Marvell PHY
I'm trying to understand the proper way to design a PCB to interface a Xilinx 7-series FPGA with a Marvell 88E1512 Ethernet PHY, without simply copying the design from an existing schematic.
The ...
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Can several Ethernet PHYs cause damage to one another if they transmit on MDIO bus simultaneously?
I have 4 ethernet devices (1 PHY - AR8035; and 3 Dual PHYs - DP83849IFVS) on my custom PCB board. ICs are controlled by SoC AM335x via MDIO bus. Previous revisions of the board worked fine. New ...
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45
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What is the operating voltage of Media access controllers? [closed]
Do MAC and PHY operate on same voltage levels?
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299
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Ethernet 1Gbps - PCB stackup
I am planning a stackup for 2x Ethernet phys. The chip requires a few different supply voltage levels: I/O Power 3V3 (3 pins) and Analog Supplies: VDD2V5 (2 pins) and VDD1V0 (4 pins). Each pin has ...
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Receive Ethernet data to the FPGA [closed]
I have Lattice ECP3 Versa Evaluation Board.
My objective is to connect Ethernet to the FPGA and be able to receive data (and later to send data) successfully. I don't really care on what protocol I ...
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328
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PHY to PHY connection (KSZ9477S and DP83849IF)
I want to connect two phys on pcb through AC coupling (max path 150 mm), one PHY is KSZ9477S embedded PHY, other is DP83849IF PHY. The schematic is attached
At first the I made a direct connection ...
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123
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phy chip straping pins
as you can see options strapping pins are multiplexed with RXD# pins .. which are MII interface pins.
this will make the PCB have "stubs" (connected to MAC + pullup resistors) which is not good in ...
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DP83848C: DP83848 stops working after few month on field
In a product we designed, the LAN drive circuit(MII mode) is composed of LPC1768 and DP83848CVV. The function is very normal. There are no problems with factory testing. After using it in the hands of ...
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694
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sgmii auto negotiation - how long should this take?
I am working with LWIP - and an 1G marvell phy, m88e1111 - connected to a Microsemi SmartFusion 2 FPGA design using 10b8b (aka: TBI) interface.
I'm doing something wrong with the auto negotiation and ...
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46
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Fast Ethernet transmitter structure
Does anyone knows internal structure of a typical Fast Ethernet 100BASE-TX transmitter?
I wonder how MLT-3 voltage levels are formed and what can cause abnormal voltage levels at the PHY output?
...
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2k
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The SERDES/transceiver design inside the Ethernet MAC controller
I'm a little confused about the "SERDES" interface between MAC and PHY chip, and I drew some figures to illustrate the connections which confuse me as shown below. The MAC controllers in 3 figures are ...
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