Questions tagged [phy]
The phy tag has no usage guidance.
74
questions
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34 views
Fast Ethernet transmitter structure
Does anyone knows internal structure of a typical Fast Ethernet 100BASE-TX transmitter?
I wonder how MLT-3 voltage levels are formed and what can cause abnormal voltage levels at the PHY output?
...
0
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1answer
121 views
The SERDES/transceiver design inside the Ethernet MAC controller
I'm a little confused about the "SERDES" interface between MAC and PHY chip, and I drew some figures to illustrate the connections which confuse me as shown below. The MAC controllers in 3 figures are ...
0
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1answer
90 views
Ethernet vs CAN bus physical signal
Reading about Controller Area Networks and Ethernet standard, I cannot understand why there is a difference in the way the signal is transmitted. Both protocols use twisted pair cables to communicate, ...
0
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0answers
23 views
No ethernet connection with Atmel Start example with custom board
I want to use the Atmel Start ethernet example with my custom board what contains the Atmel chip ATSAME70Q21A-AN and Ethernet Phy KSZ8041TL. To test the ethernet connection on the board I used Atmel ...
0
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1answer
61 views
A few questions about the application of ethernet controller and PHY chip and SFP module
I have a question about the connection/application between the ethernet controller and PHY/SFP modules.
Actually, there're so many scenarios for building up a NIC card, which makes me confused.
For ...
0
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1answer
72 views
Ethernet PHY clock and sync
I have a general question about reference clocks for ethernet PHYs.
The PHYs I have seen so far require an external clock source like a xtal or other singleended clock (in addition to the clk lines ...
1
vote
1answer
80 views
How to connect CPU with RGMII pins to an LTE module that takes only SGMII signals?
The Hi3519 Hisilicon CPU has RGMII pins. We are trying to connect it to the EC21 LTE Module from Quectel which contains SGMII pins. Would using two Realtek RTL8201F-VB-GG PHY chips with magnetics ...
2
votes
1answer
75 views
10/100Mbps Magnetics with 10/100/1000 PHY
I have a SOC that has a KSZ9031RN PHY, that is a Gigabit PHY. But I'm going to use only in 10/100 Mode with 4 wires.
Gigabit PHY datasheet recommends a magnetic for Gigabit Ethernet, that are ...
0
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0answers
20 views
How is the DLL used in MIPI C-PHY or D-PHY?
I guess the title says it all. I can't seem to find how exactly the Delay Locked Loop (DLL) is used inside in one of the MIPI PHYs.
Thanks.
1
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0answers
86 views
PHY Link only establishing 10 Mbps speed when both devices 100 Mbps capable
I've designed a circuit board with a Microchip switch (KSZ9897) going to a Ethernet-to-VDSL module (LX200V20).
The PHY ports between the two devices are connected using a transformerless connection ...
0
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1answer
72 views
Why this evaluation board use different track impedance than the right one? Ethernet PHY, routing
Im doing a design with a implementation of 1Gb ethernet switch, for that I bought a evaluation board to do it well.
The problem is that in the layout of the ev board I can check that the track ...
1
vote
2answers
264 views
Single pair ethernet (SPE) PHY with ESP32
can I connect this Single Pair Ethernet PHY http://www.ti.com/product/DP83TC811R-Q1 to a ESP32 chip? Do I miss something?
Does anyone already know a Switch for Single Pair Ethernet?
Looking forward ...
0
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1answer
44 views
OFDM symbol period and minimum burst durations
I have been reading about cognitive radio using OFDM and literature on technologies like LTE and 802.11 variants. A useful value in the system analysis is the OFDM symbol period \$T_u\$.
Is it ...
4
votes
1answer
331 views
Design ethernet switch for multiple devices on pcb?
I'm working on a pcb design with a Raspberry Pi CM module and a microcontroller with ethernet capacity. The goal is to connect the devices to the internet.
I'm currently using a normal ethernet ...
0
votes
1answer
117 views
Why is Logical root sequence number in Root Zadoff-Chu needed?
I have been investigating RACH preamble planning and the properties of Root Zadoff-Chu sequences as used in 3GPP LTE.
From Wikipedia, Zadoff-Chu sequences have the following properties:
The auto ...
0
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1answer
81 views
Ethernet magnetics [duplicate]
I am working on a system prototype which includes two ethernet switches (KSZ9896) to provide Ethernet Gigabit connectivity between several devices (let's call them slaves, from now on); every slave ...
2
votes
1answer
1k views
How can I configure PHY in cubeMX on own board?
I made a customboard using STM32f217VET microcontroller and KSZ8081 PHY (builtin pull-up resistors for TXP TXM and RXP RXM). I Configured my board to use MII mode, anda I used a 25MHz oscillator to do ...
0
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2answers
200 views
How to connect the PHY crystal for RMII?
I'm attempting to implement Ethernet communication for the first time and have run into an issue with my PHY. I'm using the KSZ8091RNBCA. According to the datasheet, when running in RMII mode, the XO ...
2
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2answers
985 views
Impedance Matching Resistors on MII Ethernet Lines
Microchip is taking forever to activate my account so I will ask this here...
I am using the KSZ8081 PHY for MII Ethernet.
https://www.mouser.com/ProductDetail/Microchip-Technology-Micrel/...
1
vote
1answer
117 views
PHY Register 5 Technology Ability Field Meaning
I have a question about each bit fields(bit 5 to bit 8) of PHY register 5.
The following is the description page of a PHY.
I know that these fields are Technology Ability Field which is the link-...
0
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2answers
145 views
Inverting REFCLOCK of Ethernet PHY
A few years ago I had to design a board that uses the NXP LPC1769 MCU and had Ethernet connectivity. I was in need of a PHY chip and the LAN8720 was choosen.
During design however, I noticed that NXP ...
4
votes
1answer
471 views
Should I terminate the MII/RMII interfaces?
For Ethernet PHY design, the MDI interface should be terminated. Then how about the MII/RMII or GMII/RGMII interfaces? I've seen some designs terminated them, and most not. There are some PHY chips ...
2
votes
2answers
466 views
Use crystal or oscillator for a Ethernet PHY?
I've saw so many reference designs use just a crystal to generate the clock for ethernet phys, though they can be generated with a crystal oscillator too. Such as KSZ9021's 'XI' and 'XO' pin.
Are ...
0
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2answers
198 views
RSET pin function of RTL8211E
I'm using Realtek's ethernet PHY RTL8211E, but can't figure out what's the purpose of pin 'RSET', and how to connect it. The only datasheet I can find is
here.
It's wired I can't get that datasheet ...
0
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1answer
163 views
Using SMI to check speed of ethernet phy
I am trying to use the ethernet PHY which comes with my Digilent Nexus 4 DDR, a Microchip LAN8720A (datasheet). I wrote a controller which lets me read and write values to the smi registers using the ...
2
votes
1answer
481 views
Ethernet PHYs IEEE1588 PTP vs SOF
I currently working on a new design that should support Ethernet IEEE1588 PTP. I was looking for Ethernet 1GBit PHYs with IEEE1588 support when I saw this on TI website:
http://www.ti.com/interface/...
1
vote
2answers
626 views
Lan9500 to Switch (KSZ8795) MII wiring
I'm an experienced analog/power designer that's been asked by a coworker to scrub a digital design. He's pretty junior, but a good friend, so I am helping. (So now we're BOTH in trouble. ;-P
We ...
0
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1answer
455 views
is MDIO required for PHY?
Most of the Ethernet PHY chips (e.g. LAN8720) provide strapping option to control operation.
I am short of IO pins in my uC, and I do not need (AFAIK) to change anything more in the PHY operation.
(...
0
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1answer
126 views
Direct connection between two SFP+ cables [closed]
I have been reading a lot about modern fiber networking recently and I have a clarifying semi-hypothetical question:
Imagine I have two 3-foot sections of Multi Mode Fiber, and four SFP+ 10G ...
3
votes
1answer
1k views
Ethernet Transmission with one MAC and Multiple PHYs
I have been recently learning about ethernet subsystem. I see that the MDIO interface is shared across multiple (upto 32) PHYs from a single MAC and each PHY's state can be accessed using the 5-bit ...
3
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1answer
211 views
Correct Ethernet Jack + Magnetics for 100Base-TX
I've been shopping around for Ethernet jacks for use in a personal project. The part specifically states that it's internal PHYs are 100BASE-TX/10BASE-T/Te IEEE 802.3
I understand the basic ...
1
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2answers
3k views
Differential Pair Length Matching for DP83848I
I'm looking in the datasheet and layout guide of the DP838481 but I can't seem to find where it talks about length matching for the RX and TX differential pairs. It only mentions length matching for ...
1
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1answer
148 views
NIC connection with PHY issue
We have an NIC (computer A) connected to Marvell 88e1116R via Ethernet cable, the Marvell chip is then connected to Xilinx FPGA, the FPGA connected to ADSL Analog front end (AFE), the AFE is connected ...
0
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2answers
101 views
usage of at24c02 eeprom with ethernet module
ı design a altium circuit schematic which consists of lan8720 tranciever rj45 and also at24c02 eeprom .However ı dont know exactly what MAC means and what it does. Why do we use eeprom with ethernet?...
0
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1answer
84 views
Ethernet Switch used for CCA to CCA comm without FPGA/Proc for MAC
I'd like to connect Ethernet between devices through magnetics without the FPGA or processor involved. For example, I have several off board (PWB) Ethernet signals coming onto my board and then onto ...
0
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1answer
1k views
Purpose of QSGMII
I do not understand the purpose of QSGMII. QSGMII is supposed to combine 4 SGMII signals from 4 MACs into 1 QSGMII signal at 5 GHz. However, there is no Ethernet standard that works at 4 (or 5) GHz. ...
0
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1answer
454 views
SGMII, MDIO and link training
I am reading this document : https://www.nxp.com/webapp/Download?colCode=AN3869
I got this link from NXP support, but I did not get a precise answer to my questiosn and I would like to be sure :
The ...
1
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1answer
276 views
Should I remove terminating resistors in ethernet TAP?
I would like to design Ethernet TAP, with PHY, that I can connect to FPGA via RGMII interface. I know, that I could do this like there, but I would like to be able to analyze low level data in MAC. ...
1
vote
1answer
1k views
Does SGMII use MDIO?
I was reading the SGMII specification and the documentation of a Gigabit MII to SGMII converter (see MAX24287). I do not see a MDIO to control the registers of the PHY (Basic Mode Status Register, ...
3
votes
1answer
147 views
How might an LPDDR2 PHY be designed?
I was reading the LPDDR2 spec today out of curiosity. While browsing the spec I became curious about "how might one hypothetically design a minimal working LPDDR2 PHY on paper/for simulation, perhaps ...
6
votes
1answer
743 views
Why are there different Ethernet PHY magnetic configurations?
I'm looking at pcb-mount Ethernet ports like these:
I'm seeing a few different configurations of the magnetics within the ports. On a single Wurth data sheet, there are 4:
Schematic 2 is the part we ...
1
vote
3answers
1k views
Ethernet PHY/MAC/SWITCH IC available?
I'm wanting to use an ethernet switch/Phy LAN9303 to output 2, maybe 3 ethernet signals. I know that I need a 25MHz clock, supporting resistors and caps as well as the magnetics, but I want to know if ...
1
vote
1answer
1k views
What do pull-up and pull-down resistors do in an ethernet PHY?
I've noticed that most ethernet physical layers (i.e. the interface between the MAC/network and e.g. an RJ45 connector with magnetics) have pull-up or pull-down resistors on the TX and RX lines. For ...
2
votes
1answer
1k views
GMII/RGMII TX_ER signal: guaranteed functionality?
I have a question seeking to clarify EXACTLY what happens during a GMII exchange between MAC and PHY. Specifically, regarding the TX_ER signal.
IEEE 802.3 Section 3:
TX_ER is driven by the ...
9
votes
1answer
2k views
Ethernet: distance from PHY to magnetics
I am confused as to the preferred placement of Ethernet PHY and magnetics. I thought that in general, the closer the better. But then SMSC/Microchip app note (http://ww1.microchip.com/downloads/en/...
2
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1answer
596 views
Is PHY always needed?
If I'm sending UDP from a microcontroller to another (both have built in MAC, STM32f4 Discovery boards to be precise), must I have a PHY attached to both or can I get away with only sending a MII ...
-1
votes
1answer
210 views
Can a same phy be used for IPV6 and IPV4?
Currently I am using LAN8720 from microchip in my device for IPV4 network?Can same PHY work with IPV6 network?
If yes the why?
and if no then what can anyone suggest me a decent chip for it?
Thanks
1
vote
1answer
776 views
MAC PHY defenitions
from Wikipedia:
The media-independent interface (MII) was originally defined as a
standard interface used to connect a Fast Ethernet (i.e., 100 Mbit/s)
media access control (MAC) block to a ...
0
votes
1answer
175 views
Ethernet PHY Layer Compatibility
I have two different embedded devices with ethernet connection. One is based on Texas Intruments DM648 DSP chip and the internals of the other are unknown to me.
When I connect each one of them ...
1
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1answer
953 views
How to test Ethernet PHY's MDI interface through JTAG Boundary scan
We now use SCANWORKS Boundary Scan Tool from ASSET to make Ethernet SWITCH's manufacturing test. But in almost all PHY chips from broadcom corp, the MDI interfaces are "Linkage" bits. It means that ...
