Questions tagged [physical-design]
This can refer to the design of the actual transistors inside an IC. That is also called IC layout.
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What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?
I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
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Any spec detailing physical properties (length, area, shape) and sillicon dopping concentration of standard NPN transistors such as BC 107?
I'm trying to find the physical constructive parameters (especially doping levels) of the common NPN transistor BC 107/108/109 but I can't find any resource detailing this things, only the standard ...
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What are the theoretical constraints that prevent making the propagation delay of a CMOS inverter arbitrarily small?
I'm taking a course on CMOS circuit design and, from my course slides, I have that the the low-high propagation delay of a matched CMOS inverter is given by
$$
\frac{2\,L\,{\left(C_{\textrm{DB2}} +C_W ...
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How can standard cells of a process design kit have multi-Vdd?
I was confused after reading the datasheet of a process design kit (PDK) where it says that the standard cells support multi Vdd.
How is this possible? Isn't Vdd fixed for standard cells? Since all ...
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What's wrong with this CMOS implementation of XOR?
I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate. My first attempt had floating nodes and other issues with untethered ...
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Why is this CMOS implementation of XOR wrong?
I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate.
My attempt at this is the following:
The given answer is this:
Why is ...
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Standard cell design flow in an ASIC design flow
I have a question regarding the standard cell design flow in an ASIC design flow.
That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
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Why is the output voltage of an electric generator limited to 25 kV?
I'm currently studying electrical machines, and reading the book I found the following statement:
The output voltage of an electric generator is usually limited to 25 kV due to physical ...
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How do I improve a simple home-made capacitor?
I was explaining to my son that a capacitor is simply 2 sheets of foil separated by a dielectric and rolled up and he said, "can we make one then?"
I'm giving it a go. I used household ...
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2
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Variation in Tphl of MOS nand gate due to input patterns
I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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What makes some commercial JFETs asymmetric?
In a MOSFET, the obvious cause of asymmetry is the fact that the source is tied to the body. But in a JFET, no such obvious answer exists, as the body, gate, and drain are all the same piece of ...
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using solenoid magnetic field to press a button
I'm looking for a simple way to make Arduino press a spray button. I don't care which button to use, it can be either this type:
or the following:
I know there are ways to solve this problem using a ...
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DRAM Rank-Level Allocations
I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
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Vias in a the layout of a CMOS Integrated Circuit
Is there a downside to using maximum possible VIAs (adhering to DRC rules) to connect two very long metals (ex. Power rails in Mx and Mx+1) running in parallel at block level? I know that multiple ...
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Uncertainty(jitter) in setup and hold calculation
In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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Tips for designing a permanent magnet synchronous generator?
I'm currently working on designing a permanent magnet synchronous generator for one of my personal projects and I'm having trouble getting a voltage I am satisfied with. My goal is to get around 4-6 V ...
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Working of NMOS as a capacitor
I came across instances where NMOS was used as a capacitor in analog circuits. This is done by shorting the drain and source. The drain/source acts as one terminal of the capacitor while gate acts as ...
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MOSFET treshold voltage
Does anyone know how MOS treshold voltage varies if the physical distance between source and drain decreases ?
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Machine learning for floorplanning
I have an educational assignment to make an floor-planning tool.
Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
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Why do lead-acid batteries only last for a few years? [closed]
Why do lead-acid (automotive-style) batteries typically only last for a few years of regular use (or x amount of cycles) before having problems?
Obviously, things can't last forever. But, what are ...
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Segmented Display With SMD Pads? (Not Thru-Hole or Half-hole SMD) [duplicate]
I'm looking through a product design, and I've seen these SMD / sticky segmented displays LCD being used.
They are not hand-soldered, the segmented display appears to use some conductive sticky pad ...
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How can I calculate/estimate the resistance of the thin film structured like in the picture (top view)?
let's say the thin film is made of metal with resistivity rho and thickness t.
I need to calculate the sheet resistance between point A and B.
any reference suggestion is really appreciated.
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Do PCBs have schematics? [closed]
I have been studying electronics a bit at home in my spair time. I was wondering if manufacturers make schematics for PCBs? If I could get ahold of something like that i feel that I could understand ...
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How to design ultra low-power opamp?
I am designing a low-power opamp (differential amplifier) that will be used in the low-power consumption devices, e.g., power management circuits, portable devices, or energy harvesting circuits. I am ...
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Floorplanning vs Placement in VLSI
The major steps of physical design that I learnt from a VLSI lecture are: 1)Partitioning 2)Floorplanning 3)Placement 4)Routing. The question of mine is about the steps 2 and 3.
It seems like the ...
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Spinning Solar Cells at 50 hz make a pure sine wave? [closed]
What would be the out put of the solar panels spinning towards the sun? Ideal conditions would be o gravity in a vacuum tube or space.
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What is standard about standard cells in layout designing? [closed]
Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
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Multiple Transistors (FinFET) sharing a gate?
Transistors are among the most fundamental components of electronic devices, and that to produce transistors with better performance, FinFET transistors have been developed:
This allows for better ...
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Fear of electric arcs on a multiple outlet [closed]
I am physically near a multiple power outlet of the following model:
The official page of the article is PowerCube |Extended|
My doubt is: each outlet seems to close to each other. Should I fear ...
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Calculating resistance for metal layer from LEF File
I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278.
In the File description it is written as ...
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Help understanding practical transistor considerations?
So first, sorry if I make some incorrect assumptions or statements. If I do, just correct me and forgive my ignorance.
It seems like everything I've been taught so far in classes about transistors ...
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GDSII stream reading
GDSII is a photomask\artwork format for photolitography. I am having trouble resolving a particular line in the file.
For example, 'SRefs' means it refers to one of the structures and uses this ...
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Odd resistor design
In one of my designs, I specified the Rohm LTR10EZPF1003 100K 0802-Wide resistor:
The issue is that when I added the resistor to the circuit, it creates a direct short:
Measuring between the Green ...
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Is sinking mode and open drain the same concept in electronics?
I'm reading a few manuals about I2C , SPI where it says I2C ports are open drain,which I don't know what it is.
I know about sinking mode and sourcing mode of ports in electronic circuits.
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What is the measurement grid in the context of strain gauge?
The sensor I am investigating is the 1-LM11 by Omega.
I am looking at the specification at there are two metrics which confuse me, the measurement grid A is 1.5mm while measurement grid B is 2.5mm. ...
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Does this sort of connection on a Yagi Antenna make sense?
Here is an image of a WiFi yagi antenna I bought recently (and opened up for I could see no spectrum out of my SDR)
I see that the coax has been connected to two plates, which I think act as dipoles. ...
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I need help with designing my first PCB on Proteus?
I've placed the component of a simple power supply circuit on PCB layout screen using auto-placer and auto-router. I would like to know many things about dimensions:
Is there a standard space ...
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How is a signal physically routed in an FPGA?
I've looked at this similar question, but it does not provide the answer I'm looking for. The documents from Xilinx also confuse me and the diagram provided in the Implementation view of the Xilinx ...
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Source synchronous vs Common clock methodology in Physical design
The common clock and source synchronous clock scheme is explained here: http://referencedesigner.com/books/si/common-vs-source-sync.php.
Question is:
1) How is maximum frequency attained with source ...
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Kick-off Spread Spectrum Clocking
Need of SSC:
Spread spectrum clocking (SSC) is a special way to reduce the radiated emissions of digital clock signals. These levels or energy is radiated and therefore this is where a potential EMI ...
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School Project : To determine Eq. resistance of a cube whose each edge has a resistor, say R [closed]
Background
I am a high school student, we are supposed to submit a Physics Project, individually.
Since I have never done any Electrical Project/Experiment before, I came up with the idea of making a ...
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How to make a phase shifter?
I've gotten interested in beam-forming via a phased antenna array. I read a few articles/tutorials and they have very nice diagrams of antenna arrays and how the antennas interact to behind each ...
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Is it possible to reverse engineer a ROM chip by grinding and taking photos?
Recently someone made a claim that you can reverse engineer a ROM by physically grinding the chip and taking pictures of the various layers.
Is this really possible?
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Clock nets Routing
We know that the clock tree synthesis is performed before signal routing. What is the specific reason for that. Or we can route both at the same time?
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Where is the cold junction on the commercial thermocouples?
According to all textbooks and articles, a thermocouple must have a cold junction somewhere on the middle of it.
But none of the commercial products have a middle point or a marked spot for ...
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Muxes, Adders, Comparators, and Gates
This question is actually from one of my previous discussions, which I still don't understand how to implement. The goal is to use abstraction to design a circuit, which converts two-digit ASCII ...
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LM2907 schematic critique
I have been working with the LM2907 as I have been designing a few circuits around it. This has lead to me wanting to understand more of its inner workings and build up a breadboard model of the ...
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In logical progression, what things does a person need to know to design a robust opamp from BJTs
Opamps contain things like current mirrors, differential stage, push-pull pair and much more. Once a person starts from learning that BJT has 3 terminals for which Ic≈Ie≈βIb, what topics must a person ...
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Physical push-down toggle button that pops up on voltage
I have encountered innumerable variations to functionally identical 2-lead physical switches, like the push-to-toggle buttons I am currently working with. Manually depressing the button toggles ...
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What is the physical size of a logic gate?
I always hear about process size improvements in the news, but could never figure out how it translates into dimensions of a logic gate. I found a chapter from Weste's CMOS VLSI Design, that contains ...
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