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Problem with 5-staged pipeline CPU design

We are doing a project designing a 5 staged pipelined CPU on RISC-V ISA, when designing the hazard detection unit and forwarding unit, instead of using the common datapath design, we design like this: ...
Wells's user avatar
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1 answer
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Is it possible to use registers on Intel‑based FPGAs ? If not what’s the alternative for solving the bandwidth issue?

In order to bruteforce a key where the first private’s key bytes are known (leaving 270 possible private key to search) I’d like to do the following: pick up a 64‑bit private key range split that ...
user2284570's user avatar
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Confusion about the Link Register content during exceptions in ARM

I can't understand how the link register of the exception mode is updated during the exception. Why for the SVC, Prefetch Abort and Undefined Instruction, the LR is having PC + 4 but for the Data ...
Emad Kheyroddin's user avatar
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60 views

Understanding ARM Pipeline: Questions on PC Incrementation and Exception Handling for SVC Instructions

I read this on ARM community website but i got confused: "Imagine your 3-stage pipeline like this: PC - FETCH - PC+4 -> DEC - PC+4 -> EXECUTE || Exceptions are generated (pended) at the end ...
Emad Kheyroddin's user avatar
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On understanding tradeoffs associated with pipeline depth

In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the ...
EE18's user avatar
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1 answer
155 views

Understanding decode stage of x86 fetch-decode-execute pipeline and its (lack of) register requirements

FDE pipeline has register requirements for the F & D stages: For fetching an instruction from memory, the instruction pointer register points to the memory location of the next instruction to be ...
computegirl314's user avatar
3 votes
2 answers
512 views

How to pipeline an algorithm that not only has latency but also relies on feedback of the previous run?

Trapped in this problem for several days, I feel I can't think of a proper solution on myself. The problem is as below. Say, a source-input is streaming a sequence of ...
xc wang's user avatar
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1 answer
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Why do we need stalls even if branches can be determined?

I am learning about pipelining and was reading about control hazards from the book Computer Organization and Design: The Hardware/Software Interface (MIPS Edition). There is a paragraph in the book (...
Prithvidiamond's user avatar
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1 answer
51 views

Designing instruction emulating swap on a MIPS ISA with only 2 registers

In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units. How to design an instruction to emulate swap?
Nidhi's user avatar
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classic RISC pipeline: Why does memory access stage comes before register file write back?

Here are two confusions: Instruction fetch step provides info on what's the op and in which register the data lies, but how does that data comes into those registers? It seems that once the execution ...
lousycoder's user avatar
2 votes
2 answers
375 views

Pipelining digital logic with feedback

EDIT: Unfortunately, the example below was poorly chosen. Several people correctly pointed out that x2 is just a bit shift and doesn't actually require a multiplication. I'm aware of this but I ...
MattHusz's user avatar
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How does CPU control implement pipeline stall [closed]

The original question was deemed lack of focus. This post is specifically about cpu pipeline stall. How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during ...
Oliver Young's user avatar
-1 votes
3 answers
2k views

What is the difference between stalling and flushing in a microprocessor?

As the title suggests, I want to understand the difference. Attaching the reference.
Anonymus's user avatar
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1 answer
170 views

where to place registers in VHDL modules

I'm a software guy by trade and I have been dabbling in digital design on FPGA using the open source toolchain. I have made a few designs and generally understand how the handle verilog and VHDL. One ...
John Smith's user avatar
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3 answers
956 views

Question about pipeline techniques in FPGA

I'm trying to improve timing in my FPGA design. I need my logic to work with a 150MHz clock, the synthesizer is saying it can work only with ~138MHz maximum. I know that one of the popular ways to ...
Michael Rahav's user avatar
1 vote
2 answers
1k views

FSM vs Pipeline

I am new to the world of HDL. I am currently working on implementing AES in Verilog code. I manage the flow of my logic using varying FSMs. Given this approach I currently have to wait for the first ...
ChrisMcNeill's user avatar
1 vote
0 answers
161 views

How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
Anshul Gupta's user avatar
3 votes
1 answer
399 views

With what stage of the branch instruction does the IF stage executes if the branch is taken?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. Consider an instruction ...
Anshul Gupta's user avatar
1 vote
0 answers
58 views

Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
Abhishek Ghosh's user avatar
1 vote
1 answer
118 views

Throughput increase/decrease by how much percent

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
Anshul Gupta's user avatar
4 votes
1 answer
718 views

Is it possible to remove the write back stage in 5-stage pipeline?

In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
Lei Gao's user avatar
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1 answer
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Pipelined designs with outputs in differentes delay clocks

I have a pipelined design that ends in 13 clock cycles when the input value is not close to zero, but when the input is close to zero, the design only needs about 4 clock cycles, because of all the ...
Diego Ruiz's user avatar
2 votes
1 answer
147 views

Doubt in pipelining forwarding in MIPS

I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google I have a doubt in part ...
nmnsharma007's user avatar
-1 votes
2 answers
309 views

Parallel execution in a single ALU

I read that in theory, it is possible to use the circuits in an ALU in parallel. Now I am wondering whether there is any way to leverage this in practice on commodity CPUs? Specifically, I want to ...
cabeer's user avatar
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0 answers
618 views

Forwarding in RiscV multi cycle Pipeline

Any idea could be helpful I have been trying for days to understand forwarding mechanism in RiscV but unfountly I keep failing, so I though about asking basic question to make sure I am building on ...
carlos's user avatar
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102 views

Why we can't do forward in RiscV?

While studying forwarding in RiscV cpu I saw the following claim: But I can't understand why we can't do forward in this case, why in different conditions we were able to do this and now we can't? It ...
daniel's user avatar
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1 answer
496 views

Why are master-slave D flip flops preferred for pipeline stage buffers?

I'm watching a lecture on designing pipelines in HDL, and it's mentioned that the buffers (for intermediate values) between pipeline stages should be master-slave flip flops to avoid race conditions. ...
Justin Olbrantz's user avatar
0 votes
1 answer
322 views

Pipelined Feedback Summation on FPGA, Verilog

I'm working on a project and I need to write a Pulse Integration block for RADAR project. To do it I using some kind of buffer and in the first loop insert the data input to it: buffer[0]=din. ...
Michael Rahav's user avatar