All Questions
9 questions
7
votes
4
answers
1k
views
How does pipelined CPU access both code and data memory in real life?
In the Digital Design and Computer Architecture RISC-V Edition page 442, a pipelined CPU is designed with separate instruction and data memories, as shown in the figure below.
However, this picture ...
- 193
4
votes
1
answer
161
views
Understading CPU pipeline stages
I'm working on implementing a CPU that needs a three-stage pipeline. The division of those stages is open for me to determine.
I am struggling to comprehend how the stages are counted. While some ...
- 75
0
votes
1
answer
57
views
Problem with 5-staged pipeline CPU design
We are doing a project designing a 5 staged pipelined CPU on RISC-V ISA, when designing the hazard detection unit and forwarding unit, instead of using the common datapath design, we design like this:
...
- 9
-1
votes
3
answers
2k
views
What is the difference between stalling and flushing in a microprocessor?
As the title suggests, I want to understand the difference. Attaching the reference.
- 107
1
vote
0
answers
61
views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
- 155
4
votes
1
answer
802
views
Is it possible to remove the write back stage in 5-stage pipeline?
In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
- 113
-1
votes
2
answers
363
views
Parallel execution in a single ALU
I read that in theory, it is possible to use the circuits in an ALU in parallel. Now I am wondering whether there is any way to leverage this in practice on commodity CPUs?
Specifically, I want to ...
- 3
0
votes
0
answers
776
views
Forwarding in RiscV multi cycle Pipeline
Any idea could be helpful
I have been trying for days to understand forwarding mechanism in RiscV but unfountly I keep failing, so I though about asking basic question to make sure I am building on ...
- 41
0
votes
0
answers
114
views
Why we can't do forward in RiscV?
While studying forwarding in RiscV cpu I saw the following claim:
But I can't understand why we can't do forward in this case, why in different conditions we were able to do this and now we can't?
It ...
- 31