Skip to main content

Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

Filter by
Sorted by
Tagged with
0 votes
1 answer
40 views

How is the \$M^2\$ term derived in the PLL output phase noise spectrum?

Originally, I was interested in the derivation of Equation 12.5 in the RF synthesis chapter of Razavi's textbook Design of phase-locked loops. I tried to look up the origin of it and found out a very ...
Tong Su's user avatar
  • 113
0 votes
0 answers
16 views

Transfer function of noise from Vtune of VCO to its output phase noise using VerilogA model

I am using the code below for VCO, and it is pretty standard and straightforward. I want to make sure that the noise transfer function from control voltage to phase noise is correct, as I am going to ...
hassan's user avatar
  • 1
0 votes
0 answers
40 views

What options are there for multiplying clock pulses by non-harmonic values?

I have a MIDI clock signal which will output pulses at 24ppqn and a device I would like to synchronise which runs at 64ppqn. This is equivalent to a an ⁸⁄₃ clock multiplication. My current method is ...
Pernel_Sned's user avatar
4 votes
2 answers
210 views

For this particular Ring oscillator topology, will the circuit prefer to latch up or oscillate?

This circuit is chosen from Razavi's textbook Design of CMOS Phase-Locked loops In this circuit, where the outer inverters are weaker than the inner ones, does the circuit prefer to latch up or ...
Tong Su's user avatar
  • 113
0 votes
0 answers
52 views

Crystal load capacitor physical defect

I have a 16MHz crystal that is used to derive a 60MHz PLL. I have not seen many issues but have a PCBA that loses its PLL lock. I'm not sure why but I looked at one of the load capacitors up close (...
Orca_StackOverflow's user avatar
0 votes
0 answers
57 views

Delta Sigma Modulator for 2/3 Multi modulus divider used in FracN PLL

I have been trying to implement a Delta Sigma modulator for a 2/3 Multi Modulus divider. I am referring to Riley's paper: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=229400 I have designed ...
Pranjal Mahajan's user avatar
0 votes
0 answers
40 views

Generating sine, triangle (etc) waves from ttl output of a GPS module (Ublox)

I'm building a variable frequency standard using a Ublox gps board off Ebay. It'll be hooked up to an Arduino and you enter the desired frequency via a keypad. The signal from the module is a square ...
Mandelstam's user avatar
0 votes
0 answers
63 views

STM32F031 HSI clock temperature impact

I developed an electrical board that contains a STM32F31C4T6. The product worked well for more than two but since this summer I have customer feedback on malfunctions of the card, it no longer works ...
Kolia's user avatar
  • 55
1 vote
1 answer
69 views

PLL Theory - Laplace Transform

[Design of Analog CMOS inteagrtaed circuits by Razavi] Can someone explain what Lapalce transform rules states that this is possible? They have a function of excess output phase / excess input phase ...
muosac's user avatar
  • 87
0 votes
1 answer
72 views

Is it legitimate to apply reset logic to inputs only?

Let us consider this module for FPGA implementation: ...
alfred486's user avatar
2 votes
0 answers
84 views

Low jitter clock multiplier

I am using a 2-channel arbitrary waveform generator to generate two 40 MHz signals. The AWG also has a trigger signal output: short (~20 ns) pulses of ~2.5 V. The AWG has a negligible jitter of about ...
Andrew's user avatar
  • 21
1 vote
2 answers
113 views

How to generate a sine wave that is in phase with a generated square wave at 1MHz for lock-in amplifier?

I am building a lock in amplifier (LIA) for fluorescence lifetime measurement using off the shelf components, after going through literature, I have decided to use square wave for excitation of the ...
Pranav Agumbe's user avatar
1 vote
1 answer
81 views

STM32F407 PLL config not producing 1ms SysTick

I've a bare metal PLL setup for my STM32F407 which should generate a 168MHz system clock. However for some reason the 1ms SysTick interrupt is orders of magnitude off the grid. The math works out on ...
Michael's user avatar
  • 113
2 votes
0 answers
104 views

What Exactly Is Meant by a 2nd Order Phase Locked Loop?

I'm teaching myself about polyphase clock sync for demodulation of OQPSK. An article from gnuradio.org entitled "Polyphase Clock Sync" makes references to a 2nd order loop. The context seems ...
James Strieter's user avatar
0 votes
0 answers
38 views

Finding PID coefficient for my PLL system

I have a feedback loop as shown below. We are fixing the noisy YIG with a cavity resonator and feedback (shown in the attached paper and diagram below). The phase difference between the signal is ...
lub2354's user avatar
  • 373
0 votes
1 answer
41 views

Are two FPLLs in sync?

Two FPLLs are being driven by a common clock and the output of each FPLL is used to drive a counter after achieving a lock. When we turn on the circuit both FPLLs miraculously lock EXACTLY at the same ...
shaiko's user avatar
  • 479
0 votes
2 answers
17 views

Debugging PLL STW81200TR not locking

I need a bit of debugging help with SWT81200 PLL that I am using on my custom designed PCB. I am able to configure registers through SPI communication, but the problem is that I am not able to achieve ...
Vasja Pira's user avatar
1 vote
0 answers
78 views

Type 2 comparator locking on ringing

I have successfully designed a 4046 IC with a phase 2 comparator locking to an external 10 MHz VCOCXO. The circuit is simple vcoxco----> divide by 10--> Schmitt Trigger --> divide by 10 -->...
Ken90's user avatar
  • 176
0 votes
2 answers
194 views

What is the maximum PLL output frequency in the STM32H7A3?

I'm setting up a hyperram, and I want to run it at 200MHz, with the DHQC setting enabled. The peripheral manual on page 874 says: DHQC must not be set when the prescaler value is 0, as this action ...
Drew's user avatar
  • 7,078
0 votes
1 answer
128 views

Designing loop filter for frequency-modulated PLL

I'm designing a PLL circuit to stabilize a ~200MHz VCO against temperature-induced frequency drift. However, I need to be able to occasionally (~few times/sec) send a short pulse (~few μs) to modulate ...
Ryan White's user avatar
0 votes
0 answers
103 views

How to synthetize a 10 kHz signal from 1 Hz analogically

I would like to synthesize a 1 Hz signal to a 10 kHz one without using MCU or related DPLLs. Anyone has a schematic example? I found this reference schematic on Art of Electronics. Would that suit (...
Ken90's user avatar
  • 176
0 votes
0 answers
28 views

How to find the direction of phase difference of sine signals using multiplier phase detector?

I am using a multiplier phase detector like here 1to find the phase difference between two phase shifted sine signals, and I got the value of magnitude but how to find if the signal 2 is leading/...
Rima's user avatar
  • 133
0 votes
1 answer
875 views

Using MMCM/PLL source clock pin elsewhere in design breaks timing

TL;DR: New to Vivado Clocking Wizard, using the clock pin from the FPGA for anything other than the input to MMCM/PLL IP fails timing. I'm working with Vivado ML 2022 in VHDL targeting an Artix-7 FPGA ...
RyzenFromFire's user avatar
2 votes
0 answers
99 views

Best way to close GPSDO PLL digital loop?

I am trying to build a GPSDO with a holdover capability of 500us/24hs (maximum drift accumulated). The system uses a 10MHz OCXO and it is my intention to use a microcontroller (ATMega, STM or ...
Fernando Hernandez Ruiz's user avatar
1 vote
1 answer
69 views

Creating a large number of crystal-stabilized pulse waves at precise frequencies

I intend to generate 22 separate 50% duty cycle pulse or square waves. The frequencies range from about 5 Hz to 350000 Hz and are all irrational numbers, so I would like as much precision as possible. ...
dcsuka's user avatar
  • 111
1 vote
2 answers
95 views

N-counter issue ADF4001

I designed and tested a PCB with a PLL circuit. The goal is to lock on the reference signal which is a square wave. The problem I am having is that the signal of the N-counter shows no response, just ...
Chris's user avatar
  • 21
2 votes
0 answers
466 views

Problems Comparator II of this CD4046 for LTspice

I downloaded a CD4046B model from user ale_t, which can be found here: https://www.electro-tech-online.com/threads/new-spice-model-for-cd4046b-phase-locked-loop-ic.149093/ However, the Phase ...
JP117's user avatar
  • 21
0 votes
1 answer
184 views

About PLL input frequency

I am working on a PLL design. I am at the research stage now. I am confused about the PLL input frequency range. This frequency has to remain constant. If this input frequency stays constant, how can ...
natarajmarble's user avatar
0 votes
1 answer
601 views

Clock crystal oscillator and PLL accuracy

If I use an 8 MHz oscillator with accuracy of 25 ppm and the PLL multiplies it to 32 MHz, then the accuracy is also multiplied (x4 = 100 ppm) or is it not? Thanx.
Erick.87's user avatar
0 votes
2 answers
511 views

Frequency multiplication with PLL circuit

I am currently working on frequency multiplication with a PLL circuit. I want to give it an input frequency of 10 kHz to 100 kHz and I want to get 160 kHz to 1.6 MHz from the VCO output. That's a ...
natarajmarble's user avatar
0 votes
0 answers
32 views

How to get freq stability with constant offset for PLL synthesizer?

I used ADF5356 PLL synthesizer. And i use reference oscillator freq is 10MHz with initially offset 0.1ppm and stability is 10 ppb. I need to output freq is 3750 MHz. Expected output result: 10MHz × 0....
Purushothaman Jayaraman's user avatar
-1 votes
1 answer
358 views

How to generate correct frequency in DDS using stm32?

I had asked a question a week ago regarding DDS on STM32 and I got some good answers. Based on that I tried to write a code to implement DDS on stm32. In my project I need to generate a 10 KHz sine ...
Rima's user avatar
  • 133
2 votes
2 answers
677 views

Implementing direct digital synthesis in STM32 microcontroller

I am working on a project that requires phase locking (digitally) of an output signal from a sensor to the reference signal which needs to be done on STM32 microcontroller. I am new to this area, and ...
Rima's user avatar
  • 133
4 votes
4 answers
650 views

Meaning of "three-stating" a PLL charge pump

I am designing a phase lock circuit using an Analog Devices ADF4107 PLL Frequency synthesizer (https://www.analog.com/en/products/adf4107.html). The PLL is programmed manually and one of the settings ...
ultravioletcatastrophe's user avatar
0 votes
1 answer
80 views

PLL design in amplifier

We have designed a PLL for an operating range of 11-14 GHz. The output of the VCO goes directly to the amplifier, and then to a divider, see the picture. Is there anything that affects PLL locking ...
Dinesh 's user avatar
2 votes
1 answer
163 views

Reliability issue of HMC833 PLL

We are using an HMC833LP6GE PLL in our design for generating 122.88 MHz from a reference of 100 MHz. We are feeding a reference signal of >5 dBm. What we are observing is that out of 10 times, if ...
MightyBeard007's user avatar
0 votes
1 answer
127 views

Can't find transistor-based PLL circuit example

I am learning electronics as a hobby. My current interest is phase locked loops (PLL.) I was able to find a lot of block diagrams with explanations of how PLLs work and also CD4046 based PLL ...
Igor Lapin's user avatar
2 votes
1 answer
327 views

PLL minimum frequency: how much tolerance?

Many FPGAs have phase-locked loops which can multiply the frequency of a clock. The signal path of a PLL is rather simple: ...
techmann's user avatar
1 vote
3 answers
263 views

Selecting optimal phase locked loop (PLL) frequency for microcontroller peripherals

Typically microcontrollers use an input clock source with a certain frequency. This clock source is then divided and multiplied to a PLL frequency which is much higher. Finally, the PLL frequency is ...
user694733's user avatar
0 votes
1 answer
58 views

How did he calculate the error in this example?

He found an error of about 18%. What is the error formula used in this example? From section 1.5.1 of the book Design of PLLs by Behzad Razav.
Zineddine Haboussi's user avatar
2 votes
0 answers
56 views

Designing circuit of clock recovery from data line [duplicate]

I am currently struggling with the following challenge. In the system I am currently designing, the transmitting device is equipped with an image sensor with MIPI output (1 data line, 12 Mbit data ...
piotr's user avatar
  • 292
0 votes
0 answers
111 views

Oscillator with low frequency drift

I need a ~70MHz oscillator with low frequency drift (less than 1%) over a wide temperature range (10°C to 50°C). I dont have any experience with oscillators, so I have no idea which type of oscillator ...
BenK's user avatar
  • 135
2 votes
1 answer
101 views

ATTiny861A fast PWM mode not working

For a couple of hours, I struggle to find the source of my PWM output to not generate a PWM signal. I changed register values to explicitly show their contents - I hope it will make the diagnostics ...
drydre's user avatar
  • 75
1 vote
0 answers
55 views

LMX2820 readback operation [duplicate]

How can a readback operation be done on LMX2820? I've looked through over it's datasheet, register map and AN documents and there is no information about that. In LMX2594 read and write operations are ...
lazba's user avatar
  • 171
0 votes
1 answer
104 views

I2C Protocol. Receiving a byte from slave device. How does the slave pull down the SDA line between two edges of SCL?

As we know, the waveforms of the I2C signals (SDA and SCL) are very similar to the following: The main requirement is that during the transmission of a byte, the SDA does not transition while SCL is ...
acefrrag's user avatar
0 votes
1 answer
75 views

Phase detection accuracy with USRP N210 and CBX-40

I have designed a simple TX/RX system in GRC with a single USRP N210 and CBX-40. I am transmitting sinusoidal signals at various frequencies within the 2-6GHz range and detecting the amplitude and ...
Fati's user avatar
  • 1
0 votes
1 answer
179 views

STM32 PLL settings make my program crash

I am following a course on USB programming on STM32 platform. My board is a STM32F746G-DISCO with a STM32F746NG microcontroller. In the course, the teacher sets his board to these frequencies: SYSCLK ...
Wheatley's user avatar
  • 690
2 votes
1 answer
1k views

Dead zone in phase frequency detector (PFD)

I am working on a design of a PFD for a PLL. I came across an issue of dead zone which requires a minimum time for the switches to be on so the charge pump works the way we want (image 1.) The ...
negative_feedback's user avatar
0 votes
0 answers
111 views

Can I use a resistor to transfer voltage to current rather using transconductance amplifier?

The situation is I intend to transfer voltage to current to control a laser. The voltage comes from an optical phase-locked loop (OPLL). It is changing over time, so the current transferred from this ...
Madao's user avatar
  • 1
0 votes
0 answers
111 views

Do any FPGAs that set undefined values ​in registers after power up exist?

There is some discussions how to set default values or start an initial sequence in FPGAs design after programming/power-up. The most reliable method is using a supervisor IC which guaranteed send ...
Arseniy's user avatar
  • 2,245

1
2 3 4 5
8