Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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23 views

Conclusions about PFD/Charge pump simulation

I have built a Sequential NAND based phase detector with a charge pump that includes a differential amplifier and I want your help make some conclusions about the results I got running all the ...
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Sequential NAND Based Phase-Frequency Detector output

I'm trying to understand the output of my phase detector only for a pulse that goes from zero to one. here is my schematic: (ref is Clk_ref, and Div is Clk_out, both come from an outside circuit) ...
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Can someone help me in getting to know what is wrong with my Frequency multiplier circuit using 565?

I just learned the working of NE565 and I tried to simulate a Frequency as multiplier using 565 in Proteus , but I don't know why PIN 4 of my NE565 is not giving any output . Its coming plane blank in ...
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comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
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87 views

Phase detection with non-ideal PFD

I'm trying to simulate for Phase Frequency Detector with the following implementation: and inside NAND_PFD: NOTE: the triangles on the right are inverters and not amplifiers. I'm currently ...
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30 views

Bootstrapped charge pump design for phase frequency detector

I'm trying design a charge pump as it's showed in the following link: https://ibb.co/DDc6DsF (for some reason I couldn't upload it, I don't know why). what I don't understand is what is \$I_{ref}\$ (...
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37 views

RF sampling ADCs(ADC12DJ3200 ),PLLS and regulators placement and layout

I am novice in PCB component placement and layout. I have just started my career in Hardware design. We have designed a schematic for Data Acquisition System. In our design, we are using three RF ...
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30 views

Choosing PLL Loop Filter Bandwidth and Phase Margin for Frequency Ramp Generation

I am new to PLLs and am trying to use one to generate a frequency ramp between 5.725 GHz and 5.875 GHz. I have found tools online that help design loop filters for PLLs, and all of these tools require ...
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60 views

Trouble understanding Loop Filter in a PLL

I'm currently trying to understand the function of a loop filter. But where I'm stuck is that I know the output of the charge pump is a series of current pulses whose width is proportional to the ...
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79 views

Choosing a suitable PFD for PLL

I'm building a capacitive vibration sensor and it has to reject the stray capacitance by locking the LC oscillator at 64 MHz, where I can demodulate relatively small frequency changes. The best way to ...
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111 views

Why should crystal switching be avoided?

The MC44144 is a gated phase locked loop intended for video applications that is described in its datasheet as "sensitive to shunt capacitance" and that "crystal switching should be avoided". What ...
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29 views

Arty7 Verilog Control PWM input Clk using PLL

I currently running into a problem of creating an instant of the PLL Clk_Wizard from Xilinx IP. My goal for this project is to provide a much faster clock for the PWM module (for exotic FET). I'm very ...
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Phase noise of a digital PLL

I assume the reader is aware of how a DPLL works. The DPLL oscillates with a frequency of \$F_{out}\$. The DCO free running frequency is \$F_{free}\$. In the model of our DPLL we've only considered ...
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84 views

Common symbol for PLL

Is there a common symbol for PLLs, either for schematics or functional diagrams? I need a symbol which would be easily recognized as a PLL, without having to draw the phase comparator, loop filter, ...
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51 views

digital PLL - oscillations

I'm building a 3 phase digital PLL and implementing it on a microcontroller. I included a schematic of the SRF-PLL principle that I use. The abc->dq0 transform is done so that the q component for a ...
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64 views

Phase Frequency Detector without dead zone

How does the two inverter delay stage in Figure 6.14 on page 265 of Design of CMOS RF Integrated Circuits and Systems helps to eliminate dead zone in Phase Frequency Detector ? How does the PFD ...
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VCO circuit Analysis

can you help me with the basic comprehension of this Voltage Controlled Oscillator scheme (it was used in a PLL)? I do not understand why there are two varactors instead of one, and the role of the ...
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117 views

Is it possible to create a PLL purely in digital design, if so how?

Provided that we want to reduce jitter on an a periodic input signal (square wave between 0 and Vcc) which is only in some 100 of KHz range, one possibility is to create a system purely using RTL code ...
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34 views

Fractional-N frequency synthesis does not work on Mach XO2 FPGA

I'm using the Right side PLL to implement a clock generator on a Mach XO2 7000 FPGA that takes in a 50 MHz clock generated by the Left side PLL and outputs a clock that can be changed from 50 MHz to ...
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97 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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77 views

Doubt about Phase Locked Loop

How is it possible that the Signal Output will have the same frequencies as the Reference Signal?\$f_1\$, Frequency of the Reference Signal;\$f_2\$, Frequency of the VCO. Let's assume that \$f_1>...
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62 views

The mean value of phase noise as a stochastic process

What is the mean value of phase noise as a stochastic process? Where can I get a theoretical analysis of this topic?
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117 views

Two details about phase noise have been confusing me for a long time. Hope to be resolved

Just like FLOYD M. GARDNER said in the PhaseLock Techniques, 3rd Edition: "In light of that success in spectrum analyzers, a practitioner’s answer to the question above is: The spectrum of phase noise ...
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197 views

What is the difference between a PLL and a frequency-synthesizer? [closed]

It seems that a LPF is contained in PLL and not in frequency-synthesizer. Maybe I had made a wrong judgement.
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113 views

Hall Effect pulse multiplier circuit

I would like to use a Phase Locked Loop (PLL) to multiply a 4x signal to be an 8x signal, and modify the same 4x signal to be a 64x signal so that all three signals are available as a 5v clean low - ...
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50 views

PID: how to deal with delay between controller and a process?

In designing a digital pll, I'm facing a problema with a communication delay between the loop filter output and the frequency synthesizer (via SPI). If I dont consider the communication delay the ...
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Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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PLL with two input frequency within lock range for FM demodulation

I have current output from a photodiode which I believe containing at least two distinct frequencies that is not too far apart from the lock range of a PLL which taking this current as the input ...
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108 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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183 views

Stability of a PLL

I try to design a analog PLL. I use a doubly balanced mixer as phase detector and a VCXO. The reference is a benchtop signal generator. So I currently try to design the loop filter, and I struggled a ...
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216 views

Using LTSPice to make Function Blocks for SIMULINK

I have a PLL that I want to model in Simulink using the control theory toolkit. I have the schematics for the PLL in LTSpice. Does anyone know of a way that I can integrate the spice model with my ...
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118 views

Frequency multiplier from kHz to MHz

I'm not familiar with electronics at all, and would like to get some ideas to implement frequency multiplication of LVCMOS. I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
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1answer
91 views

PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
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36 views

STM32F405 Internal vs External Oscillator

If the frequency stability over a temperature range is not a concern in a project instead it's reliability in continuous long time operation is a more important factor then which of the two ...
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77 views

Frequency tracking PLL type

I'm unable to understand which PLL type (1 or 2) is better suited for frequency tracking and why? Can anyone explain how that additional integrator in type 2 will affect tracking? Thanks in advance!
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Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same ...
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38 views

Stability Criteria of Type 3 Digital PLL

I suppose we can derive the stability criteria based on poles of open-loop transfer function of F(z) in expression (4.11). However, the pole analysis does not help in deriving the stability criteria ...
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603 views

Can I program a platform independent PLL in VHDL?

Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom ...
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93 views

Are there still programmable clock synthesizers with single ended TTL output leves (in 2019)?

I'm looking for a clock synthesizer IC that can drive my vintage 5V NMOS CPU in the range of 5 - 50MHz. The granularity would preferably be in the range of 100kHz or less. All I can find when ...
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First order PLL power consumption

For a system level project I want to estimate the impact having a single vs. multiple PLLs. Is there a first order estimate that relates power, jitter (total integrated phase noise) and possibly ...
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Derivation of stability criterion for type 3 digital PLL

Could anyone help to derive the following expression (4.23) which is the stability criterion for type 3 digital PLL ? Note: Screenshots are taken from Floyd Gardner's book : Phaselock Techniques 3rd ...
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54 views

PLL : conceptual confusion

In the PLL it is said that Capture range is the frequency from which the PLL starts functioning and Locked range is the frequency where the output of VCO is equal to that of reference oscillator ...
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46 views

Is it possible to power down all the PLLs and VCO of a MAX 10 Device?

We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled ...
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102 views

Maximum CPU Frequency of PIC24FJ256GA705 That I Can Get with 8MHz Crystal

I'm used to run PIC24 device family (e.g PIC24FJ256GB) at CPU freq 32MHz using the PLL. Recently I got to use PIC24FJ256GA705 on my new project and when I read the datasheet, I found out that the PLL ...
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1answer
646 views

LTSpice simulation stalls after 100ms transient with 'Heightened Def Con'

I simulate a system of two mutually delay-coupled electronic clocks (DPLLs - digital phase-locked loops). This worked well and also in reasonable time so far. However, moving into a particular regime ...
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323 views

Altera Cyclone IV PLL: What limits the available multiplication/division factor values

Altera Cyclone IV EP4CE6E22 with a 50 MHz input clock. I want to get 24 MHz out of the ALTPLL megafunction. The requested multiplication/division settings are 12/25 but actual settings turn out to be ...
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130 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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Can I use a PLL to generate the *phase* component of an SSB signal?

I want to use Kahn's method of Envelope Elimination and Restoration (EER) to produce a single-sideband, supressed-carrier (SSB) signal. Kahn simply clipped a low-level SSB signal, but I wonder if it ...
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138 views

Understanding PLL performance: PFD output bandwidth

For an application I need to FM modulate a signal with a 10 MHz bandwidth. Due to constraints I have no control over, I have to do it in an analog way (so I can't just digitize the signal, IQ modulate,...
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107 views

Phase Locked Loop Gain Design- FM Demodulation

Say I am trying to demodulate a message up to 25kHz in frequency, with a peak frequency deviation of 75kHz and a carrier of 1MHz, implying a 200kHz bandwidth using carsons rule. Would I design the ...