Questions tagged [pll]
PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.
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Poor accuracy in PLL
I'm using the CDCE913 to output various frequencies in the range of 77.2-97.4 MHz.
When I program it to output a specific frequency using the calculations found in the datasheet, it doesn't output ...
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PLL controls frequency or phase?
I have a slight confusion about the working of the PLL. I have been following this document about digital PLL. I want to use PLL to get the same frequency and phase as that of a grid for a grid ...
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How to Create an FM Signal with a MHz Carrier Frequency and kHz Sinusoidal Information Signal for PLL in Simulink?
I am working on a project in Simulink that involves a Phase-Locked Loop (PLL). In this project, I need to use two different frequencies—one in the MHz range and the other in the kHz range. I am trying ...
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USB3300: ULPI link reports "Failed PLL lock" error upon booting into Petalinux
Currently debugging the USB2.0 transceiver or PHY chip (USB3300) that seem to fail to have the ULPI link lock the transmitted 60MHz clock signal (PLL lock failed error). I found that the chip's ...
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Question about MASH (ΣΔ) time domain adpll model from Syllaios paper
I have been trying to implement the adpll in time domain from Syllaios paper in Octave, the adpll is locking from my simulations (and fractional), but i have a question which I don't know how to ...
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Maximizing power transfer from 50Hz AC line via toroidal current transformer
This paper looked at ways of achieving high power-to-weight ratio for harvesting power from a 50Hz overhead line.
https://findresearcher.sdu.dk/ws/portalfiles/portal/250674676/...
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In a type 1 PLL will the output and input have phase difference after phase is locked?
Regarding XOR based type 1 digital PLL, I can see that after the phase-locking the output freq. and the input freq. will be same.
But how about the phase? Will the phase difference be zero or? I ...
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Help to configure an LTspice PLL simulation
I never tried PLLs before and to gain some insight I'm trying to simulate CD4046Bg in LTspice where I want the output to phase-lock and follow the input signal. I tried so far the below:
But I get an ...
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Does PLL stabilize the frequency variations of a crystal oscillator?
I don't know inner workings of phased locked loop and only know that PLL can be used to multiply the clock frequency of a crystal oscillator for instance for a micro-controller.
My question is: does ...
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Need Help Increasing PWM Frequency from 800 Hz to 8000+ Hz for DC Motor Speed Control
I'm currently developing a speed control system for a powerful 12V DC motor that pulls a heavy load. To enhance system efficiency, I need to raise the PWM frequency from the 800 Hz (PLC upper limit) ...
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Lattice Diamond PLL Configuration for decimal output
I have been working on a Lattice FPGA to configure a 37.125MHz output for a 24MHz input clock... but the only way I have been able to accomplish getting this is with a 5% tolerance and a big ...
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Are these filters suitable for this application?
I want to use the ADF4350 as a local oscillator and I want it to sweep as fast as possible from a start frequency A to the end frequency B the issue is the span is large and for that i have to use a ...
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How to calculate the PLL sweep time?
How can I calculate the sweep time of a PLL for a given bandwidth and a frequency span and setted step?
Let say:
Span 30MHz
Bandwidth 30KHz
Steps 200KHz
Edit:
So lets say we want to sweep from a start ...
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Why don't we use an integrator as the loop filter of a PLL?
In a book on phaselock that I was reading, it mentioned that ideally, one would use an ideal integrator as the loop filter of a PLL. Since we can implement integrators with op-amps, why don't we use ...
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Where to find/learn standard meaning of ω or φ, etc., in RF circuit design
I am retired from a long career in Electronic Warfare (EW) in the US Navy, followed by decades in communications in two-way radio engineering, cellular system technical management, etc, and then a ...
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Why the loop bandwidth must be much smaller than the input frequency to ensure settling behavior?
Razavi said, in Section 9.6 Loop bandwidth of his book RF Microelectronics that
In the design of PLLs, we impose... a loop bandwidth much smaller than the input frequency to ensure a well-behaved ...
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Generating Sinewave with PLL [closed]
I'm trying to make a sine wave and sweep frequency near 150MHz. Since my application requires exact frequency and high stability, I'm trying to look for a PLL.
However, I cannot determine if the chip ...
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How is the \$M^2\$ term derived in the PLL output phase noise spectrum?
Originally, I was interested in the derivation of Equation 12.5 in the RF synthesis chapter of Razavi's textbook Design of phase-locked loops.
I tried to look up the origin of it and found out a very ...
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Transfer function of noise from Vtune of VCO to its output phase noise using VerilogA model
I am using the code below for VCO, and it is pretty standard and straightforward. I want to make sure that the noise transfer function from control voltage to phase noise is correct, as I am going to ...
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What options are there for multiplying clock pulses by non-harmonic values?
I have a MIDI clock signal which will output pulses at 24ppqn and a device I would like to synchronise which runs at 64ppqn. This is equivalent to a an ⁸⁄₃ clock multiplication.
My current method is ...
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For this particular Ring oscillator topology, will the circuit prefer to latch up or oscillate?
This circuit is chosen from Razavi's textbook Design of CMOS Phase-Locked loops
In this circuit, where the outer inverters are weaker than the inner ones, does the circuit prefer to latch up or ...
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Crystal load capacitor physical defect
I have a 16MHz crystal that is used to derive a 60MHz PLL.
I have not seen many issues but have a PCBA that loses its PLL lock. I'm not sure why but I looked at one of the load capacitors up close (...
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Delta Sigma Modulator for 2/3 Multi modulus divider used in FracN PLL
I have been trying to implement a Delta Sigma modulator for a 2/3 Multi Modulus divider. I am referring to Riley's paper: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=229400
I have designed ...
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Generating sine, triangle (etc) waves from ttl output of a GPS module (Ublox)
I'm building a variable frequency standard using a Ublox gps board off Ebay. It'll be hooked up to an Arduino and you enter the desired frequency via a keypad. The signal from the module is a square ...
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STM32F031 HSI clock temperature impact
I developed an electrical board that contains a STM32F31C4T6. The product worked well for more than two but since this summer I have customer feedback on malfunctions of the card, it no longer works ...
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PLL Theory - Laplace Transform
[Design of Analog CMOS inteagrtaed circuits by Razavi]
Can someone explain what Lapalce transform rules states that this is possible? They have a function of excess output phase / excess input phase ...
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Is it legitimate to apply reset logic to inputs only?
Let us consider this module for FPGA implementation:
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Low jitter clock multiplier
I am using a 2-channel arbitrary waveform generator to generate two 40 MHz signals. The AWG also has a trigger signal output: short (~20 ns) pulses of ~2.5 V. The AWG has a negligible jitter of about ...
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How to generate a sine wave that is in phase with a generated square wave at 1MHz for lock-in amplifier?
I am building a lock in amplifier (LIA) for fluorescence lifetime measurement using off the shelf components, after going through literature, I have decided to use square wave for excitation of the ...
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STM32F407 PLL config not producing 1ms SysTick
I've a bare metal PLL setup for my STM32F407 which should generate a 168MHz system clock.
However for some reason the 1ms SysTick interrupt is orders of magnitude off the grid.
The math works out on ...
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What Exactly Is Meant by a 2nd Order Phase Locked Loop?
I'm teaching myself about polyphase clock sync for demodulation of OQPSK. An article from gnuradio.org entitled "Polyphase Clock Sync" makes references to a 2nd order loop. The context seems ...
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Finding PID coefficient for my PLL system
I have a feedback loop as shown below. We are fixing the noisy YIG with a cavity resonator and feedback (shown in the attached paper and diagram below).
The phase difference between the signal is ...
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Are two FPLLs in sync?
Two FPLLs are being driven by a common clock and the output of each FPLL is used to drive a counter after achieving a lock. When we turn on the circuit both FPLLs miraculously lock EXACTLY at the same ...
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Debugging PLL STW81200TR not locking
I need a bit of debugging help with SWT81200 PLL that I am using on my custom designed PCB. I am able to configure registers through SPI communication, but the problem is that I am not able to achieve ...
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Type 2 comparator locking on ringing
I have successfully designed a 4046 IC with a phase 2 comparator locking to an external 10 MHz VCOCXO. The circuit is simple
vcoxco---->
divide by 10-->
Schmitt Trigger -->
divide by 10 -->...
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What is the maximum PLL output frequency in the STM32H7A3?
I'm setting up a hyperram, and I want to run it at 200MHz, with the DHQC setting enabled. The peripheral manual on page 874 says:
DHQC must not be set when the prescaler value is 0, as this action ...
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Designing loop filter for frequency-modulated PLL
I'm designing a PLL circuit to stabilize a ~200MHz VCO against temperature-induced frequency drift. However, I need to be able to occasionally (~few times/sec) send a short pulse (~few μs) to modulate ...
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How to synthetize a 10 kHz signal from 1 Hz analogically
I would like to synthesize a 1 Hz signal to a 10 kHz one without using MCU or related DPLLs.
Anyone has a schematic example? I found this reference schematic on Art of Electronics.
Would that suit (...
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How to find the direction of phase difference of sine signals using multiplier phase detector?
I am using a multiplier phase detector like here 1to find the phase difference between two phase shifted sine signals, and I got the value of magnitude but how to find if the signal 2 is leading/...
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Using MMCM/PLL source clock pin elsewhere in design breaks timing
TL;DR: New to Vivado Clocking Wizard, using the clock pin from the FPGA for anything other than the input to MMCM/PLL IP fails timing.
I'm working with Vivado ML 2022 in VHDL targeting an Artix-7 FPGA ...
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Best way to close GPSDO PLL digital loop?
I am trying to build a GPSDO with a holdover capability of 500us/24hs (maximum drift accumulated).
The system uses a 10MHz OCXO and it is my intention to use a microcontroller (ATMega, STM or ...
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Creating a large number of crystal-stabilized pulse waves at precise frequencies
I intend to generate 22 separate 50% duty cycle pulse or square waves. The frequencies range from about 5 Hz to 350000 Hz and are all irrational numbers, so I would like as much precision as possible.
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N-counter issue ADF4001
I designed and tested a PCB with a PLL circuit. The goal is to lock on the reference signal which is a square wave. The problem I am having is that the signal of the N-counter shows no response, just ...
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Problems Comparator II of this CD4046 for LTspice
I downloaded a CD4046B model from user ale_t, which can be found here:
https://www.electro-tech-online.com/threads/new-spice-model-for-cd4046b-phase-locked-loop-ic.149093/
However, the Phase ...
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About PLL input frequency
I am working on a PLL design. I am at the research stage now. I am confused about the PLL input frequency range.
This frequency has to remain constant. If this input frequency stays constant, how can ...
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Clock crystal oscillator and PLL accuracy
If I use an 8 MHz oscillator with accuracy of 25 ppm and the PLL multiplies it to 32 MHz, then the accuracy is also multiplied (x4 = 100 ppm) or is it not? Thanx.
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Frequency multiplication with PLL circuit
I am currently working on frequency multiplication with a PLL circuit.
I want to give it an input frequency of 10 kHz to 100 kHz and I want to get 160 kHz to 1.6 MHz from the VCO output. That's a ...
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How to get freq stability with constant offset for PLL synthesizer?
I used ADF5356 PLL synthesizer. And i use reference oscillator freq is 10MHz with initially offset 0.1ppm and stability is 10 ppb. I need to output freq is 3750 MHz.
Expected output result:
10MHz × 0....
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How to generate correct frequency in DDS using stm32?
I had asked a question a week ago regarding DDS on STM32 and I got some good answers. Based on that I tried to write a code to implement DDS on stm32.
In my project I need to generate a 10 KHz sine ...
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Implementing direct digital synthesis in STM32 microcontroller
I am working on a project that requires phase locking (digitally) of an output signal from a sensor to the reference signal which needs to be done on STM32 microcontroller. I am new to this area, and ...
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