Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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Definition of Phase Locked Loop

After learning some basics of Phase Locked Loop, I came to a conclusion that it may be defined as a circuit, which in its most basic form, tries to lock(equate) both the phase and the frequency. But ...
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PLL deviation from matched frequency

If there is a phase difference between output and the input of a PLL, an error signal would be generated by phase detector, implying that the loop yet needs to settle to a final state. This may happen ...
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How to connect ADF4153 modem oscillator serially with PC without using SDP board?

I tried to connect ADF4153 modem oscillator with PC using STC15W4K56S4 that I bought from Aliexpress. My PC is reading the modem but the program is not, so I am trying to connect the ADF4153 ...
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49 views

FM demodulation using PLL?

I have to demodulate a square wave FM+PWM modulated signal, so for the FM demod I'm using a PLL with a positive edge sensitive comparator to lock on frequency only (CD4046BE). Carrier frequency is ...
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Phase Detector for PLL: Operation and Realization

I have some doubts about the realization and the operation of a phase detector for a PLL. My reference book is "The Design of CMOS Radio-Frequency Integrated Circuits" (Thomas H. Lee). The basic ...
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Grid Tie Inverter Anti islanding

I was wondering about anti islanding design. Using grid tie inverters is usually the best choice when not investing in batteries, but suppose you have batteries and want the confort of grid tie AND ...
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How does a microcontroller provide a frequency higher than its crystal frequency? [duplicate]

I have a microcontroller which is connected to an 8MHz crystal. I have a schematic which has a QSPI flash IC connected to it whose clock is provide by the micro and happens to be 48MHz. I want to ...
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52 views

Finding capacitive load driving capability of a Sine wave crystal oscillator

I will be using Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 This sine wave oscillator will be on a separate PCB which we are calling as "...
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Driving high impedance load with Crystek Sine Wave Oscillator- CCSS-945X-25-100.000

I am planning to use Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 . Now in datasheet of oscillator, output power mentioned is 5dBm into 50 ...
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46 views

Is an unlocked PLL an open-loop clock? And is a locked PLL a closed-loop clock?

What is the difference between an open-loop clock and a closed-loop clock? Is a PLL with an oscillator lock a closed loop clock? Is a PLL without an oscillator lock an open-loop clock?
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Increasing peak to peak voltage using 1:2 balun

I came across this post on TI E2E forum. In this post user wants to drive LMK04832 PLL IC clock inputs using a sine wave. User has a source of sine wave with -1.53dBm or 0.528Vpkk which they will ...
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48 views

Confusion regarding the term“locking” in PLL

I am trying to learn PLL from a website https://www.allaboutcircuits.com/technical-articles/what-exactly-is-a-phase-locked-loop-anyways/ ]1 I came across a sentence containin[g the term "lock" ...
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Function of pll?

What is the relationship between input phase and output phase of a pll(phase locked loop)? Why is it called phase locked? Does it keeps/locks output phase to phase of input meaning output has same ...
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Conclusions about PFD/Charge pump simulation

I have built a Sequential NAND based phase detector with a charge pump that includes a differential amplifier and I want your help make some conclusions about the results I got running all the ...
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22 views

Sequential NAND Based Phase-Frequency Detector output

I'm trying to understand the output of my phase detector only for a pulse that goes from zero to one. here is my schematic: (ref is Clk_ref, and Div is Clk_out, both come from an outside circuit) ...
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Can someone help me in getting to know what is wrong with my Frequency multiplier circuit using 565?

I just learned the working of NE565 and I tried to simulate a Frequency as multiplier using 565 in Proteus , but I don't know why PIN 4 of my NE565 is not giving any output . Its coming plane blank in ...
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comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
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Phase detection with non-ideal PFD

I'm trying to simulate for Phase Frequency Detector with the following implementation: and inside NAND_PFD: NOTE: the triangles on the right are inverters and not amplifiers. I'm currently ...
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38 views

Bootstrapped charge pump design for phase frequency detector

I'm trying design a charge pump as it's showed in the following link: https://ibb.co/DDc6DsF (for some reason I couldn't upload it, I don't know why). what I don't understand is what is \$I_{ref}\$ (...
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RF sampling ADCs(ADC12DJ3200 ),PLLS and regulators placement and layout

I am novice in PCB component placement and layout. I have just started my career in Hardware design. We have designed a schematic for Data Acquisition System. In our design, we are using three RF ...
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1answer
66 views

Choosing PLL Loop Filter Bandwidth and Phase Margin for Frequency Ramp Generation

I am new to PLLs and am trying to use one to generate a frequency ramp between 5.725 GHz and 5.875 GHz. I have found tools online that help design loop filters for PLLs, and all of these tools require ...
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Trouble understanding Loop Filter in a PLL

I'm currently trying to understand the function of a loop filter. But where I'm stuck is that I know the output of the charge pump is a series of current pulses whose width is proportional to the ...
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80 views

Choosing a suitable PFD for PLL

I'm building a capacitive vibration sensor and it has to reject the stray capacitance by locking the LC oscillator at 64 MHz, where I can demodulate relatively small frequency changes. The best way to ...
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Why should crystal switching be avoided?

The MC44144 is a gated phase locked loop intended for video applications that is described in its datasheet as "sensitive to shunt capacitance" and that "crystal switching should be avoided". What ...
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Arty7 Verilog Control PWM input Clk using PLL

I currently running into a problem of creating an instant of the PLL Clk_Wizard from Xilinx IP. My goal for this project is to provide a much faster clock for the PWM module (for exotic FET). I'm very ...
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Phase noise of a digital PLL

I assume the reader is aware of how a DPLL works. The DPLL oscillates with a frequency of \$F_{out}\$. The DCO free running frequency is \$F_{free}\$. In the model of our DPLL we've only considered ...
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Common symbol for PLL

Is there a common symbol for PLLs, either for schematics or functional diagrams? I need a symbol which would be easily recognized as a PLL, without having to draw the phase comparator, loop filter, ...
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53 views

digital PLL - oscillations

I'm building a 3 phase digital PLL and implementing it on a microcontroller. I included a schematic of the SRF-PLL principle that I use. The abc->dq0 transform is done so that the q component for a ...
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68 views

Phase Frequency Detector without dead zone

How does the two inverter delay stage in Figure 6.14 on page 265 of Design of CMOS RF Integrated Circuits and Systems helps to eliminate dead zone in Phase Frequency Detector ? How does the PFD ...
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VCO circuit Analysis

can you help me with the basic comprehension of this Voltage Controlled Oscillator scheme (it was used in a PLL)? I do not understand why there are two varactors instead of one, and the role of the ...
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124 views

Is it possible to create a PLL purely in digital design, if so how?

Provided that we want to reduce jitter on an a periodic input signal (square wave between 0 and Vcc) which is only in some 100 of KHz range, one possibility is to create a system purely using RTL code ...
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Fractional-N frequency synthesis does not work on Mach XO2 FPGA

I'm using the Right side PLL to implement a clock generator on a Mach XO2 7000 FPGA that takes in a 50 MHz clock generated by the Left side PLL and outputs a clock that can be changed from 50 MHz to ...
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PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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Doubt about Phase Locked Loop

How is it possible that the Signal Output will have the same frequencies as the Reference Signal?\$f_1\$, Frequency of the Reference Signal;\$f_2\$, Frequency of the VCO. Let's assume that \$f_1>...
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The mean value of phase noise as a stochastic process

What is the mean value of phase noise as a stochastic process? Where can I get a theoretical analysis of this topic?
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Two details about phase noise have been confusing me for a long time. Hope to be resolved

Just like FLOYD M. GARDNER said in the PhaseLock Techniques, 3rd Edition: "In light of that success in spectrum analyzers, a practitioner’s answer to the question above is: The spectrum of phase noise ...
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What is the difference between a PLL and a frequency-synthesizer? [closed]

It seems that a LPF is contained in PLL and not in frequency-synthesizer. Maybe I had made a wrong judgement.
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Hall Effect pulse multiplier circuit

I would like to use a Phase Locked Loop (PLL) to multiply a 4x signal to be an 8x signal, and modify the same 4x signal to be a 64x signal so that all three signals are available as a 5v clean low - ...
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PID: how to deal with delay between controller and a process?

In designing a digital pll, I'm facing a problema with a communication delay between the loop filter output and the frequency synthesizer (via SPI). If I dont consider the communication delay the ...
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Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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PLL with two input frequency within lock range for FM demodulation

I have current output from a photodiode which I believe containing at least two distinct frequencies that is not too far apart from the lock range of a PLL which taking this current as the input ...
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141 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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220 views

Stability of a PLL

I try to design a analog PLL. I use a doubly balanced mixer as phase detector and a VCXO. The reference is a benchtop signal generator. So I currently try to design the loop filter, and I struggled a ...
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281 views

Using LTSPice to make Function Blocks for SIMULINK

I have a PLL that I want to model in Simulink using the control theory toolkit. I have the schematics for the PLL in LTSpice. Does anyone know of a way that I can integrate the spice model with my ...
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142 views

Frequency multiplier from kHz to MHz

I'm not familiar with electronics at all, and would like to get some ideas to implement frequency multiplication of LVCMOS. I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
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1answer
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PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
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42 views

STM32F405 Internal vs External Oscillator

If the frequency stability over a temperature range is not a concern in a project instead it's reliability in continuous long time operation is a more important factor then which of the two ...
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Frequency tracking PLL type

I'm unable to understand which PLL type (1 or 2) is better suited for frequency tracking and why? Can anyone explain how that additional integrator in type 2 will affect tracking? Thanks in advance!
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Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same ...
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Stability Criteria of Type 3 Digital PLL

I suppose we can derive the stability criteria based on poles of open-loop transfer function of F(z) in expression (4.11). However, the pole analysis does not help in deriving the stability criteria ...