Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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Phase detection accuracy with USRP N210 and CBX-40

I have designed a simple TX/RX system in GRC with a single USRP N210 and CBX-40. I am transmitting sinusoidal signals at various frequencies within the 2-6GHz range and detecting the amplitude and ...
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STM32 PLL settings make my program crash

I am following a course on USB programming on STM32 platform. My board is a STM32F746G-DISCO with a STM32F746NG microcontroller. In the course, the teacher sets his board to these frequencies: SYSCLK ...
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1 answer
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Dead zone in phase frequency detector (PFD)

I am working on a design of a PFD for a PLL. I came across an issue of dead zone which requires a minimum time for the switches to be on so the charge pump works the way we want (image 1.) The ...
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Can I use a resistor to transfer voltage to current rather using transconductance amplifier?

The situation is I intend to transfer voltage to current to control a laser. The voltage comes from an optical phase-locked loop (OPLL). It is changing over time, so the current transferred from this ...
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Do any FPGAs that set undefined values ​in registers after power up exist?

There is some discussions how to set default values or start an initial sequence in FPGAs design after programming/power-up. The most reliable method is using a supervisor IC which guaranteed send ...
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Getting ADC value of potentiometer at a 100 ms sample rate. For the sample, would using a timer for a delay suffice?

I am using the ADC on my HCS12 to get the value of a potentiometer. I am already using a PLL and a prescaler to change the frequency of the clock. Due to the requirements on my board, this value must ...
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2 answers
170 views

Help me select an option to generate 25 kHz PWM

I'm running Arduino Mega with Marlin Firmware (as my 3d printer controller) which to my understanding has its PWM set to 1 kHz. I want to control a 4-wire fan (Pfc0612de) with PWM from 30% to 100% and ...
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PLL phase error plot confusion

I am working on the implementation of different PLL for grid-connected converters. I have confusion in a particular plot for my research which is the phase error. First of all, I generated the ...
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4 answers
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PLL phase frequency detector

If there is a constant phase difference between the VCO signal and reference signal, the phase frequency detector will always givr an error signal. How can the PLL lock in this condition? I mean the ...
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PLL simulating using CPPSIM (with C++ code)

I'm working on my PLL simulation with CPPSIM (Prof. Michael Perrott's) There's some kind block and simulator will be make c++ code (I mean Block --> C++ code to operate simulation) But I wonder ...
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1 answer
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Why is the MCU clock out waveform sinusoidal and not square pulse

I got a new oscilloscope :) (proud amateur moment) I am trying to visualize the internal clock of a STM32G431RBT6 MCU. So I built an example program given by the vendor which provides the MCU clock ...
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Problems increasing VCO frequency above datasheet recommendations

Firstly, yes I contacted ST for answers. Until now, no answer. I'm using STM32F429 MCU and embedded USB FS PHY. To keep the 48 MHz USB PHY clock the maximum PLL clock that I can achieve is 168 MHz, ...
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107 views

Costas Loop QPSK/4QAM

I can use a Costas Loop, modified for QPSK/4QAM and recover the frequency and phase successfully when using a pattern of all 1s or all 0s or a pattern that is repetitive for each I and Q data rail (in ...
3 votes
1 answer
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How to determine phase sequence of the unbalanced three phase grid?

Let's say I have three phase voltage grid which is unbalanced (three phase utility grid). The phase voltages are sampled by the adc (suppose that the analog channel is properly designed from the hw ...
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2 answers
198 views

Square wave frequency multiplier

Where can I find a frequency multiplier circuit or IC that can multiply the frequency of a square wave or a sine wave by four? The input frequency can be from 100Hz to 1MHz, corresponding to an output ...
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1 answer
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Confusion about the estimated phase angle in SRF-PLL

I am working on a simple PLL Simulink model as a proof of concept: I have two problems that are causing confusion for me at the moment: What should the estimated phase angle look like? Mine is like ...
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Is choosing a high HSE frequency beneficial for the PLL CPU clock?

guys. The NUCLEO-H745ZI-Q board didn't populate the high-speed external (HSE, 4-48 MHz range) oscillators and I'm planning to solder one. I want to use the PLL so that the STM32H745's CPU1 clock can ...
1 vote
1 answer
170 views

VCO generating a lot of electrical noise, picked up by ultrasonic transducer

In my setup, I have a VCO CD4046 Phase Locked Loop IC generating a square wave, and an ultrasonic transducer set that transmits and receives that setup. You can imagine it looking something like this. ...
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3 answers
210 views

How is frequency measured in a power grid?

I know that voltage and current are measured with voltmeter and ammeter, but how is the frequenc measured in power grid applications? I know that a phase locked loop (PLL) can be used, but is this ...
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1 answer
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ADF4106 PLL output voltage lower than ATmega8A input voltage

I am working on making a frequency synthesizer getting ~900 MHz out of a VCO, using ADF4106 PLL. Now, for programming the PLL, I am intending to use AVR ATmega8A microcontroller. Everything is good, ...
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ADF4159 phase noise improvement

I integrated the ADF4159 PLL evaluation board with an external HMC510LP5E VCO to generate the desired frequencies for the application I'm working on. I'm using 100MHz reference signal from an ...
1 vote
1 answer
86 views

CD74HC4046 PLL slipping with off-air reference frequency

I am trying to use the Radio 4 198kHz carrier frequency to discipline a PLL, in order to generate a pulse-per-second (PPS) output that is stable over several hours. The issue I am facing is that the ...
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2 votes
3 answers
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STM32 on Registers Setting Up PLL, WWDG fault, Parameter/Setup Issue

STM32F746-Disco, Win 10, Cube 1.8.0; CMSIS-only (no HAL). C. I've been messing around with STM32F746 and learning to do various stuff directly via registers (interrupts, dma no problem). I left ...
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Loop Filter Bandpass Jitter Characteristic in PLL

I was watching some PLL video lectures by Professor Elad Alon, and he explains why intuitively the jitter transfer function of the loop filter to the PLL output has a bandpass characteristic. He says ...
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1 answer
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The relation between data bandwidth (BW) and BW of the local oscillator of a transmitter

Say we have some sort of data we want to send by means of a transmitter having a local oscillator as its carrier. The local oscillator can simply be realized by a phase locked loop with a certain loop ...
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decimator circuit using dflipflops

I am studying about DPLL. There are questions among CDR papers written by the same researchers. Is the symbol likes step symbol after Adder a quantizer? The output of Decimator by factor 2 is -1,0,+1 ...
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How to interpolate phase noise curves?

I am trying to calculate the phase jitter of a transmitter. A phase noise profile is given, say: ...
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Why do we need phase-locked loops?

I'm very confused about why we need phase-locked loops. On ScienceDirect.com, it reads: Phase-locked loops (PLLs) have many applications in the communications world. The main purpose of a PLL circuit ...
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PLL Clock distribution

I am generating 40MHz clock using ADF4106 PLL Frequency Synthesizer with VCO CVCO55CL-0038-0042. I am using this 40MHz generated frequency for distribution using ADCLK846. Output power from PLL is -3....
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How to calculate the phase noise contribution of an active loop filter in PLL

I want to calculate the contribution of each phase-locked loop (PLL) module to the total phase noise that has been done in ADIsimPLL. I'm having trouble calculating the contribution of the loop filter ...
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PLL and VCO example of a reference tone's frequency muliplied by 12000 to generate a master clock

A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency. The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 ...
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DDS example of a reference tone's frequency muliplied by 12000 to generate a master clock

A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency. The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 ...
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VCO from near-0 Hz to 100 MHz [closed]

Anyone know of a VCO which can range from close to 0 Hz up to around 100 MHz ? I have tried the 4046A IC, however am having trouble getting enough high frequency out of it.
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Spurs at 40 kHz frequency multiples

I have designed a PLL using an ADF4106 and a VCO. I have taken references from CN0290. I have designed the loop filter using the ADSimmPll tool from Analog Devices. I got below values from ADSimmPll ...
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how to calculate the transfer function of a differential active loop filter

When I was deriving the transfer function of a differential active loop filter provided by ADIsimPLL, I had some problems. The circuit diagram is shown below. First, for a differential active loop ...
-1 votes
1 answer
53 views

VCO tuning voltage range starting from higher than 0 V

I have seen some VCO datasheets. In every datasheet, I see that the tuning voltage range starts from some value above 0 V (like 0.5 V, 1 V etc). So, what would be the frequency at 0 V? And why do they ...
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CMOS active crystal oscillator output voltage uncertainty

I want to use SG7050CAN CMOS active crystal oscillator as reference input to ADF4106 PLL. The input voltage level is 0.8/AVDD Vp-p min/max. Now, the SG7050CAN datasheet says, it's low voltage is 0.4 V ...
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CMOS active crystal oscillator load capacitance, to be used for PLL reference

I do not have a clear idea of what load capacitance is. I am looking forward to use the ADF4106 PLL with a ~580 MHz VCO to synthesize the frequency. For the reference input to the PLL, I wanted to ...
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Loop filter R and C values rounding off

I am trying to design Loop filter with ADIsimPLL tool from Analog devices. I got below values for loop filter:- C1 --> 14.3 nF C2 --> 69.9 nF R1 --> 3.05 k How can I round off these values to ...
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How does a PLL PFD produce a high frequency?

I am going to work with a PLL and a VCO. I have read and understood the basic procedure in which the charge pump works. I understood that say, when the reference signal (or the divided signal) is up ...
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2 votes
1 answer
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Confusion on what the RF input to a PLL does

I am designing an FMCW radar, for which I need to generate an RF signal ramped in frequency. To accomplish this, I want to use a direct digital synthesizer (DDS) to generate the ramp at baseband then ...
3 votes
3 answers
264 views

Struggling to understand how a phase locked loop reaches lock

I have a basic question regarding PLLs and how they actually achieve lock. I was told that the PLLs go into the lock when the output of a phase detector is zero, therefore to drive VCO an integrator ...
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Modelling digital DLL for CDR for simulation/modelling purposes only

I have done a Verilog module for clock and data recovery (CDR) using DLL ( this is for simulation purposes only) I used Modelsim for simulation. In the transmitter (Tx), I only have a (clock that has ...
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1 vote
2 answers
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High frequency BLDC control for parallel speed and position control. Looking for thoughts

I was not able to find a similar topic but am kind of stuck with my problem. What am I doing? I am trying to control the speed of a BLDC Motor very precisely but have to control the position of the ...
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1 answer
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Can I use LVCMOS output crystal in 50 ohm system

I have a 50 ohm clocking system in a very low noise environment (RADAR). I want to use a Abracon 100 MHz VCXO (this one), which has a 3.3V LVCMOS output. Below you can see the block diagram of the ...
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2 answers
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Noisy out from the PLL

I have designed a PLL using an ADF4106 and a VCO. I have taken references from CN0290. I am able to get the desired output from the design, but there are other unwanted peaks in the output. I have ...
1 vote
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NE564 PLL chip operates on PCB only with loop filter pin 14 floating

This circuit has been implemented on my PCB. However, when I test this circuit (without the DRV135UA), it surprised me that the PLL works except Pin 14 of NE564D (V_PLL). At Pin 14, I did not measure ...
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Creating a digital PLL

I want to drive a quartz crystal resonator at its resonant frequency so I need to stay locked on to its resonant frequency as its resonant frequency changes. I'm using an FPGA to do this. I want to ...
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VCO output is its maximum frequency

I am trying to design PLL for generating 122.8MHz from 40 MHz REFIN. I am following the CN0290 EVM reference for the design. I have used CVCO33CL-0110-0150 VCO in the place of VCXO in EVM. When I am ...
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ADF4106 RF input range

I am trying to design PLL for generating 122.8MHz from 40 MHz REFIN. I am following the CN0290 EVM reference for design. As you can see, in the EVM REF_INPUT is of 10MHz and 100MHz frequency is being ...

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