Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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53 views

How to make a PLL output the phase modulo 360°?

I have made a PLL to obtain the mechanical angle encoded in quadrature sine signals (the envelope of a resolver output) ; it implements: error=in-out is approximatively equal to sin(in-out)=sin(in)cos(...
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32 views

PLL for Audio Frequency VCO using R divider

I'm attempting to design a PLL for an analog, audio frequency VCO, but I've run into a conceptual problem. I can't reasonably use a divider in the feedback path. My reference frequency would ...
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Does the PLL circuit which is used to increase frequency N times increase also the phase?

If we have a PLL with the following function: The output freq. becomes N times the input freq. But how about the phase difference between the input and the output?
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How does a PLL recover the clock from digital data signals and what does recovery mean?

Is there an easy way to explain this process to a non-expert? I read many places but couldn't figure out. I can understand the job of PLL which locks the output frequency to the fed back frequency ...
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31 views

Why must the VCCA be powered in Cyclone 10 LP even if PLLs are not being used?

The device documentation related to the Cyclone 10 LP FPGA states that "you must power up VCCA even if the PLL is not used". We were comparing the power dissipation of a Microsemi IGLOO2 FPGA with ...
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56 views

How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
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41 views

How do I find the transfer function of this op amp circuit?

This is a phase detector circuit used in PLL, the inverting input is a sinewave and there is a reference signal which is a square wave. How would the output look like if the inputs are in phase and ...
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58 views

Can an FPGA PLL lose lock if it is supplied with a stable input clock signal?

In an FPGA (Intel) design I have a PLL that is provided with a stable clock from a clock module on the PCB. The design is as shown on the figure below. The PLL has a lock indication. After the FPGA ...
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Converting PLL Discriminator into Doppler error

I'm writing a GPS receiver SDR software, and I have calculated the PLL discriminator ouptut as atan(Q_Prompt,I_Prompt) I would like to know the formula that converts the discrminator output to doppler ...
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47 views

FM Detector Using LM565

I am currently working on a power line communication project. I want to send an audio signal through the power line. In order to do that I would need to modulate my signal and in this project I am ...
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Problem in understanding how LM565 increases the VCO frequency

We were tinkering with an LM565 (PLL IC) in school and I noticed that despite the fact that the maximum frequency of VCO was 3.5 kHz, I was able to use the PLL up to circa 5 kHz with the free running ...
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Oscilloscope Phase Shift

I have a university research that i am conducting right now. My objective, as a first step, would be to phase shift an NRZ signal at high frequencies >40GHz, assuming this signal is already locked ...
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29 views

Multiplication of 2 waves in a phase detector of a phase-locked loop

What would be the product of a 60Hz square wave and a 60Hz sine wave with an approximate phase shift of -45 degrees? I could not find a proper solution to this anywhere.
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Loop Filter in an ADPLL

I am implementing an ADPLL in an FPGA with VHDL, and I am encountering a problem in correctly implementing the loop filter. The code that I currently have for the loop filter is the following : ...
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47 views

Increasing Locking range of ADPLL in VHDL on FPGA for FM Demodulation?

I am trying to implement an all digital PLL so as to demodulate an FM signal from the input. The centre frequency of the test signal is that of 140kHz. The system works fine upto a deviation of +-...
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VCO in MATLAB with Arbitrary Phase Noise Profile

I want to model a complete PLL behaviourally and use MATLAB with an arbitrary VCO phase noise profile. My VCO has a known KVCO and a known Phase Noise at a 1MHz offset (say 130dbc/hz). I also know ...
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66 views

Dividing down a VHF signal in a 4046 based PLL loop

I've decided to build a a PLL based synthesiser to produce the Local Oscillator(LO) signal for my DIY transceiver. My aim is to try to use commonly available (preferably inexpensive) parts in what is ...
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40 views

Charge Injection in Charge Pumps

let's consider the following charge pump, which is used a lot in some PLL circuits (reference): Let's focus on the left part of the circuit (until the Loop Filter Network): its aim is simply that of ...
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68 views

Loop Filter in all digital PLL cutoff?

I am implementing an all digital PLL system on an FPGA using VHDL. Now, I have not yet closed the loop, instead I have modelled a sinwave(simulating an input) at 22kHz and also modelled a cosine wave(...
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42 views

Phase Comparator and VCO in PLL

I have a basic question about the simplest PLL scheme: The purpose of this scheme is that of generating a signal which is a perfect copy of the input signal (which comes for instance from a crystal ...
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51 views

Loop Filter cutoff frequency of an all-digital PLL

I am trying to implement an all digital PLL for FM demodulation on an FPGA using VHDL. I built all the blocks needed, i.e the NCO centered at 100kHz, the phase detector(simple multiplier) but now I am ...
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231 views

Circuit for converting 48kHz to 12MHz

I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
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Understanding PLL VCO Integrator Phase-shift

In many PLL phase loop theory discussions, it's often said that the VCO acts as an integrator and therefore has a 90 degree phase shift. I've seen derivations of the VCO transfer function and this ...
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Definition of Phase Locked Loop

After learning some basics of Phase Locked Loop, I came to a conclusion that it may be defined as a circuit, which in its most basic form, tries to lock(equate) both the phase and the frequency. But ...
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PLL deviation from matched frequency

If there is a phase difference between output and the input of a PLL, an error signal would be generated by phase detector, implying that the loop yet needs to settle to a final state. This may happen ...
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How to connect ADF4153 modem oscillator serially with PC without using SDP board?

I tried to connect ADF4153 modem oscillator with PC using STC15W4K56S4 that I bought from Aliexpress. My PC is reading the modem but the program is not, so I am trying to connect the ADF4153 ...
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84 views

FM demodulation (not!) using PLL?

I have to demodulate a square wave FM+PWM modulated signal, so for the FM demod I'm using a PLL with a positive edge sensitive comparator to lock on frequency only (CD4046BE). Carrier frequency is ...
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86 views

Phase Detector for PLL: Operation and Realization

I have some doubts about the realization and the operation of a phase detector for a PLL. My reference book is "The Design of CMOS Radio-Frequency Integrated Circuits" (Thomas H. Lee). The basic ...
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Grid Tie Inverter Anti islanding

I was wondering about anti islanding design. Using grid tie inverters is usually the best choice when not investing in batteries, but suppose you have batteries and want the confort of grid tie AND ...
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102 views

How does a microcontroller provide a frequency higher than its crystal frequency? [duplicate]

I have a microcontroller which is connected to an 8MHz crystal. I have a schematic which has a QSPI flash IC connected to it whose clock is provide by the micro and happens to be 48MHz. I want to ...
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60 views

Finding capacitive load driving capability of a Sine wave crystal oscillator

I will be using Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 This sine wave oscillator will be on a separate PCB which we are calling as "...
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Driving high impedance load with Crystek Sine Wave Oscillator- CCSS-945X-25-100.000

I am planning to use Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 . Now in datasheet of oscillator, output power mentioned is 5dBm into 50 ...
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Is an unlocked PLL an open-loop clock? And is a locked PLL a closed-loop clock?

What is the difference between an open-loop clock and a closed-loop clock? Is a PLL with an oscillator lock a closed loop clock? Is a PLL without an oscillator lock an open-loop clock?
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Increasing peak to peak voltage using 1:2 balun

I came across this post on TI E2E forum. In this post user wants to drive LMK04832 PLL IC clock inputs using a sine wave. User has a source of sine wave with -1.53dBm or 0.528Vpkk which they will ...
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48 views

Confusion regarding the term“locking” in PLL

I am trying to learn PLL from a website https://www.allaboutcircuits.com/technical-articles/what-exactly-is-a-phase-locked-loop-anyways/ ]1 I came across a sentence containin[g the term "lock" ...
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Function of pll?

What is the relationship between input phase and output phase of a pll(phase locked loop)? Why is it called phase locked? Does it keeps/locks output phase to phase of input meaning output has same ...
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Conclusions about PFD/Charge pump simulation

I have built a Sequential NAND based phase detector with a charge pump that includes a differential amplifier and I want your help make some conclusions about the results I got running all the ...
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Sequential NAND Based Phase-Frequency Detector output

I'm trying to understand the output of my phase detector only for a pulse that goes from zero to one. here is my schematic: (ref is Clk_ref, and Div is Clk_out, both come from an outside circuit) ...
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Can someone help me in getting to know what is wrong with my Frequency multiplier circuit using 565?

I just learned the working of NE565 and I tried to simulate a Frequency as multiplier using 565 in Proteus , but I don't know why PIN 4 of my NE565 is not giving any output . Its coming plane blank in ...
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comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
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Phase detection with non-ideal PFD

I'm trying to simulate for Phase Frequency Detector with the following implementation: and inside NAND_PFD: NOTE: the triangles on the right are inverters and not amplifiers. I'm currently ...
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44 views

Bootstrapped charge pump design for phase frequency detector

I'm trying design a charge pump as it's showed in the following link: https://ibb.co/DDc6DsF (for some reason I couldn't upload it, I don't know why). what I don't understand is what is \$I_{ref}\$ (...
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RF sampling ADCs(ADC12DJ3200 ),PLLS and regulators placement and layout

I am novice in PCB component placement and layout. I have just started my career in Hardware design. We have designed a schematic for Data Acquisition System. In our design, we are using three RF ...
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119 views

Choosing PLL Loop Filter Bandwidth and Phase Margin for Frequency Ramp Generation

I am new to PLLs and am trying to use one to generate a frequency ramp between 5.725 GHz and 5.875 GHz. I have found tools online that help design loop filters for PLLs, and all of these tools require ...
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66 views

Trouble understanding Loop Filter in a PLL

I'm currently trying to understand the function of a loop filter. But where I'm stuck is that I know the output of the charge pump is a series of current pulses whose width is proportional to the ...
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Choosing a suitable PFD for PLL

I'm building a capacitive vibration sensor and it has to reject the stray capacitance by locking the LC oscillator at 64 MHz, where I can demodulate relatively small frequency changes. The best way to ...
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120 views

Why should crystal switching be avoided?

The MC44144 is a gated phase locked loop intended for video applications that is described in its datasheet as "sensitive to shunt capacitance" and that "crystal switching should be avoided". What ...
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Arty7 Verilog Control PWM input Clk using PLL

I currently running into a problem of creating an instant of the PLL Clk_Wizard from Xilinx IP. My goal for this project is to provide a much faster clock for the PWM module (for exotic FET). I'm very ...
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Phase noise of a digital PLL

I assume the reader is aware of how a DPLL works. The DPLL oscillates with a frequency of \$F_{out}\$. The DCO free running frequency is \$F_{free}\$. In the model of our DPLL we've only considered ...
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Common symbol for PLL

Is there a common symbol for PLLs, either for schematics or functional diagrams? I need a symbol which would be easily recognized as a PLL, without having to draw the phase comparator, loop filter, ...

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