Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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N Fractional PLL spectrum

I'm studying the different types of N-fractional PLLs based on switching between two or more frequencies to get the desired frequency. However, I'm facing difficulties to understand how the output ...
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Sinewave input for CD4046 (PLL)

Would a sinewave be a suitable input for the CD4046? I am trying use the CD4046 as a phase locked loop for a lock-in amplifier (the output from the CD4046 will be multiplied with a signal.) I have a ...
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why the control voltage of VCO in CP PLL oscillates?

I built a verilogA model for every block used in PLL, I replaced a verilogA model for VCO with a designed one but, I got oscillations imposed on the control voltage as shown below. Fdiv is the ...
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38 views

Vienna rectifier Matlab simulation

I am trying to simulate the following case: A three-phase source in a Matlab is connected to a Vienna Rectifier which is supposed to supply power to a resistive load of 50KW. Output DC voltage to be ...
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56 views

Using PLL as resonance tracker

Edit: Re-re-formulated :) I'm developing a resonant circuit with its resonant frequency around 3 GHz. I am constantly tuning this resonance frequency by an unknown amount. How can I read out the ...
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Design an N-Integer synthesizer with PLL (calculate R C of the LPF and constants of the PLL blocks)

I need to design an N-Integer synthesizer with PLL to generate the carrier signal for a WLAN transmission according to the 802.11b standard (2.412 GHz to 2.484 GHz with 20 MHz of bandwidth for each ...
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What do you mean Gear box in Serdes serializer? [duplicate]

I read a statement from a document on Serializer. It mentions no gearbox Serializer. Do you know what it meant?
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LTC6946-1: using oscillators to generate reference frequency for local oscillator signal

I have to use the LTC6946-1 (frequency synthesizer with inbuilt PLL, phase detector and programmable VCO) to generate a local oscillator signal for a radio transceiver. The output signal has to be 433....
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STM32L4 clock set up

I'm using STM32L4R5 for my project and this is my first time designing a clock source and using an ST microcontroller. I'm trying to figure out the clocking hardware configuration by reading the clock ...
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External clock oscillator and MCU

I am creating this post as a second part to a recent post I have made: STM32F446 & External Oscillator I have read other post about using a crystal that runs at 8 MHz rather than 25 MHz. Such as ...
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What is the benefit of having dynamic configuration in FPGA PLL?

With PLL it is possible to generate clock signal at different frequencies and phase values. So far I have seen that these settings are done at design time and do not have to be changed during run time....
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Franctional-N PLL spurious emissions/harmonics

I have a very rudimentary understanding of PLL frequency generation. I've heard from people that Fractional N PLL synthesizers generate a lot of spurious signals and harmonics on the output if ...
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Signal path / configuration help for a PLL for AWG

In our system signal path, there is a clock signal being sent from the FPGA noted as SCLK. This goes to each component not including the MCU. The way I understand this is that the PLL receives the ...
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How to multiply a very slow clock (1 kHz) into MHz range

I have an RS485 network connecting several MCU boards where communication happens in 1ms intervals. With the MCU it's therefore easy to create a 1kHz clock with approx 50% duty cycle using the ...
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Matlab digital phase locked loop script

I am trying to extract carrier signal from amplitude modulated signal. The amplitude modulated signal is stored in a CSV file. I tried to calculate calculate carrier frequency by calculating the zero ...
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Laplace Domain Representation for Phase Detector

I am trying to model an LTI system and determine the overall transfer function of the system. The setup consists of a laser signal being fed through some filters, amplifiers, etc. represented by ...
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How to select between different PLL and divider configurations with same result

I'm new to STM32 and totally ARM. I'm learning STM32 by a NUCLEO-L053R8 board and currently working on clock configurations. I want to clock CPU, USB and RNG all by PLL connected to HSI16 so there is ...
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Design for a PLL Auto-Locking Circuit

I am looking into electrolysis efficiency using an auto-locking PLL circuit that is supposed to latch onto the resonant frequency of the electrolysis cell, a frequency determined by the inductance of ...
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LC VCO sub 30nm node circuit and layout design

I am working on an LC VCO in a sub 30nm node to oscillate between 3 to 6 GHz. Here are the things I did so far: I already have the layout and extracted netlist for the integrated coil, L. So I did ...
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Accommodating Gain Elements in PLL Loop

Background I'm working on a PLL based frequency synthesizer for the 20m amateur radio band. For reference, I've asked questions in relation to this project before (see here). It uses the idea of an ...
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Configure STM32F3 PLL timing for ADC read of Power System and FFT

I am new to the STM32 series microcontrollers. I have a Nucleo with an STM32F303RE device to prototype a project I wish to explore. I got that model because I plan to slave ADC2 to ADC1 and read the ...
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Why does the 2nd stage of my MASH Delta Sigma Modulator have essentially no effect on the PSD?

I've asked about simulating Delta-Sigma Modulators a few times before and have made progress in simulating their design for a project, but I've hit a bit of a roadblock. I'm trying to simulate a 2-2 ...
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Disadvantages of DLL clock generators compared to PLL

I've been learning from many publications that DLLs offer various advantages over PLLs, such as low-jitter performance and fast locking. So, recently, DLLs have been used for local clock generation in ...
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What is wrong with my Simulink model of a first order Delta Sigma Modulator?

I'm trying to design a Delta-Sigma Modulator for frequency synthesizer applications and am (just right now) figuring out how to properly configure a first order DSM in Simulink. I've made a few small ...
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VCO Tuning with MOSCAPs

I'm designing an integrated VCO for use in an FM Radio frequency PLL. In order to reduce the external part count, I had the idea of using MOSCAPs as the frequency tuning element instead of external ...
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Is it possible to change the reference clock in a cpu while it is running

I understand that PLLs have a settling time but if I were to do a hardware modification that changes Vco of a reference clock to scale based on temperature of my CPU, would I be able to do so while ...
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Does imposing an odd initial condition reduce spurs in MASH Delta-Sigma Modulators that has second order stages?

I've been reading about how fractional spurs can be reduced in a Digital MASH Delta Sigma Modulator (especially for application with a fractional-N PLL) by having the initial condition of the first ...
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What is the “input” being fed into a Delta-Sigma Modulator in a Fractional-N PLL? Are bits needed for a specific resolution at the input or output?

I'm doing some reading into Fractional-N PLL design and I have a bit of conceptual confusion regarding a delta-sigma modulator used to toggle the modulus of a divider. If you're trying for a certain ...
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345 views

LM565/NE565 Spice modeling in Orcad PsPice/Proteus/Multisim

"Q: Display the outputs specified in the following figures in the simulation software and the results. That's it." I have trouble getting the answer from this circuit. When I realized that ...
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FPGA - synchronise “very close” clock from signal

This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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481 views

Clock jitter - ppm, ui, ps

I using Xilinx FPGA and need to use its PLL (MMCM or Clk Wizard) I have on my board LVDS 200MHz clock with 50 ppm frequency jitter, I took this and go to some converted I can find on the internet and ...
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Phase locked loop for Grid synchronization

Is there any IC available to implement PLL for the single-phase grid-connected inverter? one solution that I came across is using Texas instruments C2000 series microcontrollers and I also searched ...
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Analog/Linear PLL or DPLL or ADPLL?

I am a 3rd Engineering students who is preparing for analog/Mixed Signal design job. I want to do a project regarding PLLs. Which PLL should I choose to make.? There are different types of PLL ...
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How is a Multi-Bit Delta-Sigma Modulator used to toggle the modulus for a Fractional-N PLL?

I'm doing some reading about fractional-N PLL design, and a large part of this reading has been about Delta-Sigma Modulators, a method of producing a binary string to toggle the frequency divider ...
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Working out the Transfer Function of a PLL Loop given by the Analog Devices ADISim Tool

This is a followup question to this question, I asked previously. My synthesizer PLL still isn't locking and it must be the introduction of the mixer and filter into the loop that's causing the issue ...
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PLL Layout guidelines

I am designing a custom board using HMC833LP6GE. I am taking schematic reference from the Evaluation module. There will be onboard DS-PIC MCU for controlling the PLL. The reference input can be fed ...
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Trouble designing and understanding lowpass filter in analog (mixer) phase-locked loop (PLL)

I'm trying to design a software-based PLL that mimics the behavior of an analog PLL based on a 4-quadrant mixer as the phase detector (PD). The input signal is a sinusoid of unknown frequency between \...
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What are the applications of external feedback for FPGA PLL's?

I see that most FPGA vendors allow users to use an external clock signal as the feedback input to a PLL. When provided external feedback (which originates ultimately from the PLL output), the PLL will ...
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Runtime reconfigurable FPGA clock routing

I have a design with multiple inputs and outputs that should have different bit rates, configurable at runtime. Since there are more I/Os than PLLs, I need to share some PLLs, e.g.: port 1: 1 Mbps ...
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Using PLLs inside FPGAs

A document states that: Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking. You can use ...
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Issue for TCXO through frequency multiplier (PLL) for STM32 I2S signal

I try to use TCXO (KT7050A24576KAW33TAD) at 24.576 MHz through frequency multiplier (PLL) x4 (NB3N511DG) to clock the I2S bus (SAI domain) at 98.304 MHz on a MCU (STM32L4R5VIT6). Signals are not what ...
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Why does the overshoot exist when transmitter turns on?

I am implementing power amp. with 16-QAM. Because of issue on power consumption, I am using time division duplex (TDD). By TDD, the power amp. turns off if the carrier wave is not needed and vice ...
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PLL design VCO and RC filter connection in real sense and not in block diagram level

The above give basic block diagram of PLL, but according to my understanding after the output of Charge pump with loop filter , VC ie the control source for the VCO is connected to which part of the ...
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I want to generate two references pulses (Rising and Falling) generated from rising and falling edges of the reference pulse clock signal

I want to generate two references pulses (Rising and Falling) generated from rising and falling edges of the reference pulse clock signal. How can I do this with CMOS logic ?
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Is fractional PLL the key functionality that defines whether a microcontroller is able to generate an analog TV signal?

I've been researching microcontrollers with the goal of outputting NTSC and/or PAL video signals. And when I look at the microcontroller specifications, it appears to me that the single most important ...
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External Clock for AD7193 ADC

I'm attempting to design a data logger and the AD7193 seems to fit my requirements. I'd like to drive it by an external clock in a GPS-disciplined loop while sampling at an integer rate, as this would ...
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what is a BIOs Programmer used for?

Never used a BIOs programmer before. Wondering what are they for. For my current project, I need something to configure my PLL chip, which has an SPI interface. I already have the evaluation board ...
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What is the purpose of PLL in a general microcontroller

An ARM Cortex-M4 based microcontroller like TM4C123GH6PM is designed with multiple clock sources with a processor core clocked at 80MHz provided by the PLL, which, from what've read in NI-What is a ...
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Approach to an unknown orthogonal Beta Signal with a known alfa in single phase dq transformation

I am trying to implement a PLL controller to the MCU for tracking single phase line voltage . I get samples via an opamp circuit with a DC offset and the samples' raw values vary between |-244 , +244| ...
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Low pass filter target frequency for a mixed signal frequency synthesizer

I'm building a frequency synthesized local oscillator with coarse and fine tuning to span 30.5 to 32MHz. The design follows the following block diagram (bits not essential to this question removed ...

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