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Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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The mean value of phase noise as a stochastic process

What is the mean value of phase noise as a stochastic process? Where can I get a theoretical analysis of this topic?
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93 views

Two details about phase noise have been confusing me for a long time. Hope to be resolved

Just like FLOYD M. GARDNER said in the PhaseLock Techniques, 3rd Edition: "In light of that success in spectrum analyzers, a practitioner’s answer to the question above is: The spectrum of phase noise ...
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What is the difference between a PLL and a frequency-synthesizer? [closed]

It seems that a LPF is contained in PLL and not in frequency-synthesizer. Maybe I had made a wrong judgement.
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41 views

Hall Effect pulse multiplier circuit

I would like to use a Phase Locked Loop (PLL) to multiply a 4x signal to be an 8x signal, and modify the same 4x signal to be a 64x signal so that all three signals are available as a 5v clean low - ...
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1answer
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PID: how to deal with delay between controller and a process?

In designing a digital pll, I'm facing a problema with a communication delay between the loop filter output and the frequency synthesizer (via SPI). If I dont consider the communication delay the ...
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Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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PLL with two input frequency within lock range for FM demodulation

I have current output from a photodiode which I believe containing at least two distinct frequencies that is not too far apart from the lock range of a PLL which taking this current as the input ...
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1answer
66 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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1answer
137 views

Stability of a PLL

I try to design a analog PLL. I use a doubly balanced mixer as phase detector and a VCXO. The reference is a benchtop signal generator. So I currently try to design the loop filter, and I struggled a ...
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88 views

Using LTSPice to make Function Blocks for SIMULINK

I have a PLL that I want to model in Simulink using the control theory toolkit. I have the schematics for the PLL in LTSpice. Does anyone know of a way that I can integrate the spice model with my ...
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75 views

Frequency multiplier from kHz to MHz

I'm not familiar with electronics at all, and would like to get some ideas to implement frequency multiplication of LVCMOS. I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
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1answer
66 views

PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
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1answer
32 views

STM32F405 Internal vs External Oscillator

If the frequency stability over a temperature range is not a concern in a project instead it's reliability in continuous long time operation is a more important factor then which of the two ...
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Frequency tracking PLL type

I'm unable to understand which PLL type (1 or 2) is better suited for frequency tracking and why? Can anyone explain how that additional integrator in type 2 will affect tracking? Thanks in advance!
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3answers
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Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same ...
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1answer
32 views

Stability Criteria of Type 3 Digital PLL

I suppose we can derive the stability criteria based on poles of open-loop transfer function of F(z) in expression (4.11). However, the pole analysis does not help in deriving the stability criteria ...
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1answer
466 views

Can I program a platform independent PLL in VHDL?

Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom ...
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Are there still programmable clock synthesizers with single ended TTL output leves (in 2019)?

I'm looking for a clock synthesizer IC that can drive my vintage 5V NMOS CPU in the range of 5 - 50MHz. The granularity would preferably be in the range of 100kHz or less. All I can find when ...
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First order PLL power consumption

For a system level project I want to estimate the impact having a single vs. multiple PLLs. Is there a first order estimate that relates power, jitter (total integrated phase noise) and possibly ...
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Derivation of stability criterion for type 3 digital PLL

Could anyone help to derive the following expression (4.23) which is the stability criterion for type 3 digital PLL ? Note: Screenshots are taken from Floyd Gardner's book : Phaselock Techniques 3rd ...
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1answer
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PLL : conceptual confusion

In the PLL it is said that Capture range is the frequency from which the PLL starts functioning and Locked range is the frequency where the output of VCO is equal to that of reference oscillator ...
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1answer
36 views

Is it possible to power down all the PLLs and VCO of a MAX 10 Device?

We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled ...
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3answers
91 views

Maximum CPU Frequency of PIC24FJ256GA705 That I Can Get with 8MHz Crystal

I'm used to run PIC24 device family (e.g PIC24FJ256GB) at CPU freq 32MHz using the PLL. Recently I got to use PIC24FJ256GA705 on my new project and when I read the datasheet, I found out that the PLL ...
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1answer
387 views

LTSpice simulation stalls after 100ms transient with 'Heightened Def Con'

I simulate a system of two mutually delay-coupled electronic clocks (DPLLs - digital phase-locked loops). This worked well and also in reasonable time so far. However, moving into a particular regime ...
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1answer
200 views

Altera Cyclone IV PLL: What limits the available multiplication/division factor values

Altera Cyclone IV EP4CE6E22 with a 50 MHz input clock. I want to get 24 MHz out of the ALTPLL megafunction. The requested multiplication/division settings are 12/25 but actual settings turn out to be ...
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1answer
103 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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Can I use a PLL to generate the *phase* component of an SSB signal?

I want to use Kahn's method of Envelope Elimination and Restoration (EER) to produce a single-sideband, supressed-carrier (SSB) signal. Kahn simply clipped a low-level SSB signal, but I wonder if it ...
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126 views

Understanding PLL performance: PFD output bandwidth

For an application I need to FM modulate a signal with a 10 MHz bandwidth. Due to constraints I have no control over, I have to do it in an analog way (so I can't just digitize the signal, IQ modulate,...
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98 views

Phase Locked Loop Gain Design- FM Demodulation

Say I am trying to demodulate a message up to 25kHz in frequency, with a peak frequency deviation of 75kHz and a carrier of 1MHz, implying a 200kHz bandwidth using carsons rule. Would I design the ...
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2answers
207 views

Select Phase Detector Cutoff Frequency? Phase Locked Loop FM Demodulation

I'm studying a Phase Locked Loop used for FM demodulation, obviously a phase detector is used in the system. A basic implementation of a phase detector is a multiplier followed by a lowpass filter. I ...
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0answers
238 views

Matlab Phase Locked Loop Design : FM Demodulation

EDIT: It seems I've asked too much at once here. I'll do some more studying and come back if I have more specific questions. I'm trying to design an analog phase locked loop in Matlab. I've read ...
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1answer
30 views

PLL integrated CCC, Microsemi/Actel ProASIC3 nano Flash Family FPGA, A3P125

I have Micosemi/Actel ProASIC3 Nano A3P125,VQ100 Chip. I was looking for the PLL integrated CCC to connect 100MHz Clock and I have been through the manual ProASIC3 FPGA Fabric User’s Guide. where i ...
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Why doesn't my STM32F4 PLL seem to work?

I've spent a few days unsuccessfully trying to get my Nucleo F401RE to use the PLL for its system clock. I've configured it to use the 8MHz HSE and output 84MHz as the system clock. The code stops ...
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1answer
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how do i connect a PLL [closed]

i want to sync an ac source with the grid ac. I would like to connect a Phase locked loop circuit between a grid ac source and another ac source. I don't understand where to connect the ac source (...
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3answers
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How do processors control their clock speed?

I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power. For something like a desktop processor where the clock ...
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1answer
124 views

Why do we need external and internal reference simultaneously in lock in amplifier?

IN this note on lock-in-amplifier, I see that there is external which we phase lock the internal reference to. Then the internal reference is used for phase sensitive detection. My first question is ...
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2answers
337 views

Can we phase lock to a reference signal of square wave

Does the reference signal in the phase lock loop have to be a perfect sine wave? If not, how can it be phase locked to?
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2answers
642 views

Understanding Phase frequency detector logic

I have one of these common digital phase lock loops which compares the frequency and phase with a VCO (local oscillator) via a phase lock loop. I failed to understand why Figure (2) (A) and Figure (2)(...
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2answers
539 views

PLL vs Higher frequency crystal oscillator for fpga [closed]

I need 100MHz clock frequency to implement my HDL design on an FPGA. Is it better to use an FPGA board with 100MHz crystal oscillator or use PLL to increase the frequency? What are the advantages and ...
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4answers
220 views

Fast (high) frequency hopping with off-the-shelf components

I am looking for the easiest solution to synthesize 1.6 - 2.4 GHz (qudrature) in steps of 4 MHz settle within 10-50ns precise timing control when to switch frequency (e.g., at rising edge of an ...
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1answer
231 views

How to determine lock time of PLL/VCO vs frequency change?

I am trying to build a transceiver for a stepped-frequency radar. As a starting point, I am trying to generate my signal on NI's AWR VSS software. I am able to generate my signal but don't know what ...
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2answers
199 views

Could a vintage 9 transistor AM/FM implement a phase-locked loop of some form?

A side discussion around an answer to the question How many stations could one hear with an AM/FM radio in front of the ISS' cupola window? has arisen with regard to the possibility that a change in ...
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2answers
169 views

Benefits of higher order low pass in a negative feedback loop

Let \$G(s) = \frac{Y(s)}{R(s)}\$ be the loop gain of a negative feedback loop system. For example a system like this, where Y(s) and R(s) are the laplace transformed functions y(t) and r(t): ...
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1answer
190 views

What does “1.2 psrms integrated jitter” mean?

What does "1.2 psrms integrated jitter" mean? What is "psrm" as a unit for jitter? and how is it calculated? and does a unit interval differ from circuit to circuit?
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1answer
124 views

Transfer function of a digital phase frequency detector

I'm confused about the transfer function of a digital phase frequency detector. Why can we say that the pfd output is proportional to the phase error? The pfd (with charge pump) generates current ...
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2answers
170 views

Loop bandwith and open-, closed- loop gain in ADIsimPLL

I'm want to use ADIsimPll to calculate the loop filter properties for a PLL I want to build. I read some things in the programs help topics which I find somehow strange. Maybe you guys can help me out ...
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2answers
118 views

Is there any advantage to use a PLL with unitary frequency gain?

I am not a very experienced firmware developer, so I came across this doubt when I was reading the datasheet of a microcontroller: In my application, I will use a crystal to generate a clock signal ...
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4answers
174 views

Can I combine a PLL and a DDS?

I need a controllable frequency for use in a radio transceiver with a range of 3–50MHz (i.e., 80m–6m). The frequency needs to be selectable using a microcontroller. Because chips like the Si5351 tend ...
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2answers
198 views

How Replica Feedback bias circuit rejects supply noise?

I attached the circuit diagram along with a short description of its working principle. However, it's not clear how the circuit rejects supply noise. It will be great if someone can brief about what ...
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1answer
118 views

A capacitor as loop filter of a DLL

I know that if a second order, type two PLL has only a capacitor as its loop filter, it is unstable because its phase margin would be zero. but why is it ok for a DLL to only have a capacitor as its ...