Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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Problems increasing VCO frequency above datasheet recommendations

Firstly, yes I contacted ST for answers. Until now, no answer. I'm using STM32F429 MCU and embedded USB FS PHY. To keep the 48 MHz USB PHY clock the maximum PLL clock that I can achieve is 168 MHz, ...
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Costas Loop QPSK/4QAM

I can use a Costas Loop, modified for QPSK/4QAM and recover the frequency and phase successfully when using a pattern of all 1s or all 0s or a pattern that is repetitive for each I and Q data rail (in ...
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How to determine phase sequence of the unbalanced three phase grid?

Let's say I have three phase voltage grid which is unbalanced (three phase utility grid). The phase voltages are sampled by the adc (suppose that the analog channel is properly designed from the hw ...
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Lattice ECP5UM5G: receiving TMDS signal with the FGPA tranceivers

I'm trying to implement a DVI/HDMI receiver in the Lattice ECP5UM5G FPGA. This FPGA has four 5 Gb/s transceivers, that seems to be more than enough for high-resolution HDMI video. Unfortunately, the ...
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Square wave frequency multiplier

Where can I find a frequency multiplier circuit or IC that can multiply the frequency of a square wave or a sine wave by four? The input frequency can be from 100Hz to 1MHz, corresponding to an output ...
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Confusion about the estimated phase angle in SRF-PLL

I am working on a simple PLL Simulink model as a proof of concept: I have two problems that are causing confusion for me at the moment: What should the estimated phase angle look like? Mine is like ...
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Is choosing a high HSE frequency beneficial for the PLL CPU clock?

guys. The NUCLEO-H745ZI-Q board didn't populate the high-speed external (HSE, 4-48 MHz range) oscillators and I'm planning to solder one. I want to use the PLL so that the STM32H745's CPU1 clock can ...
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VCO generating a lot of electrical noise, picked up by ultrasonic transducer

In my setup, I have a VCO CD4046 Phase Locked Loop IC generating a square wave, and an ultrasonic transducer set that transmits and receives that setup. You can imagine it looking something like this. ...
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138 views

How is frequency measured in a power grid?

I know that voltage and current are measured with voltmeter and ammeter, but how is the frequenc measured in power grid applications? I know that a phase locked loop (PLL) can be used, but is this ...
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ADF4106 PLL output voltage lower than ATmega8A input voltage

I am working on making a frequency synthesizer getting ~900 MHz out of a VCO, using ADF4106 PLL. Now, for programming the PLL, I am intending to use AVR ATmega8A microcontroller. Everything is good, ...
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ADF4159 phase noise improvement

I integrated the ADF4159 PLL evaluation board with an external HMC510LP5E VCO to generate the desired frequencies for the application I'm working on. I'm using 100MHz reference signal from an ...
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CD74HC4046 PLL slipping with off-air reference frequency

I am trying to use the Radio 4 198kHz carrier frequency to discipline a PLL, in order to generate a pulse-per-second (PPS) output that is stable over several hours. The issue I am facing is that the ...
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STM32 on Registers Setting Up PLL, WWDG fault, Parameter/Setup Issue

STM32F746-Disco, Win 10, Cube 1.8.0; CMSIS-only (no HAL). C. I've been messing around with STM32F746 and learning to do various stuff directly via registers (interrupts, dma no problem). I left ...
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Loop Filter Bandpass Jitter Characteristic in PLL

I was watching some PLL video lectures by Professor Elad Alon, and he explains why intuitively the jitter transfer function of the loop filter to the PLL output has a bandpass characteristic. He says ...
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The relation between data bandwidth (BW) and BW of the local oscillator of a transmitter

Say we have some sort of data we want to send by means of a transmitter having a local oscillator as its carrier. The local oscillator can simply be realized by a phase locked loop with a certain loop ...
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decimator circuit using dflipflops

I am studying about DPLL. There are questions among CDR papers written by the same researchers. Is the symbol likes step symbol after Adder a quantizer? The output of Decimator by factor 2 is -1,0,+1 ...
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How to interpolate phase noise curves?

I am trying to calculate the phase jitter of a transmitter. A phase noise profile is given, say: ...
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Why do we need phase-locked loops?

I'm very confused about why we need phase-locked loops. On ScienceDirect.com, it reads: Phase-locked loops (PLLs) have many applications in the communications world. The main purpose of a PLL circuit ...
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PLL Clock distribution

I am generating 40MHz clock using ADF4106 PLL Frequency Synthesizer with VCO CVCO55CL-0038-0042. I am using this 40MHz generated frequency for distribution using ADCLK846. Output power from PLL is -3....
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how to calculate the phase noise contribution of an active loop filter in pll

I want to calculate the contribution of each phase-locked loop(pll) module to the total phase noise that has been done in ADIsimPLL. But I'm having trouble calculating the contribution of the loop ...
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PLL and VCO example of a reference tone's frequency muliplied by 12000 to generate a master clock

A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency. The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 ...
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DDS example of a reference tone's frequency muliplied by 12000 to generate a master clock

A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency. The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 ...
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VCO from near-0 Hz to 100 MHz [closed]

Anyone know of a VCO which can range from close to 0 Hz up to around 100 MHz ? I have tried the 4046A IC, however am having trouble getting enough high frequency out of it.
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Spurs at 40 kHz frequency multiples

I have designed a PLL using an ADF4106 and a VCO. I have taken references from CN0290. I have designed the loop filter using the ADSimmPll tool from Analog Devices. I got below values from ADSimmPll ...
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how to calculate the transfer function of a differential active loop filter

When I was deriving the transfer function of a differential active loop filter provided by ADIsimPLL, I had some problems. The circuit diagram is shown below. First, for a differential active loop ...
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VCO tuning voltage range starting from higher than 0 V

I have seen some VCO datasheets. In every datasheet, I see that the tuning voltage range starts from some value above 0 V (like 0.5 V, 1 V etc). So, what would be the frequency at 0 V? And why do they ...
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CMOS active crystal oscillator output voltage uncertainty

I want to use SG7050CAN CMOS active crystal oscillator as reference input to ADF4106 PLL. The input voltage level is 0.8/AVDD Vp-p min/max. Now, the SG7050CAN datasheet says, it's low voltage is 0.4 V ...
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CMOS active crystal oscillator load capacitance, to be used for PLL reference

I do not have a clear idea of what load capacitance is. I am looking forward to use the ADF4106 PLL with a ~580 MHz VCO to synthesize the frequency. For the reference input to the PLL, I wanted to ...
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1 answer
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Loop filter R and C values rounding off

I am trying to design Loop filter with ADIsimPLL tool from Analog devices. I got below values for loop filter:- C1 --> 14.3 nF C2 --> 69.9 nF R1 --> 3.05 k How can I round off these values to ...
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How does a PLL PFD produce a high frequency?

I am going to work with a PLL and a VCO. I have read and understood the basic procedure in which the charge pump works. I understood that say, when the reference signal (or the divided signal) is up ...
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Confusion on what the RF input to a PLL does

I am designing an FMCW radar, for which I need to generate an RF signal ramped in frequency. To accomplish this, I want to use a direct digital synthesizer (DDS) to generate the ramp at baseband then ...
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3 answers
211 views

Struggling to understand how a phase locked loop reaches lock

I have a basic question regarding PLLs and how they actually achieve lock. I was told that the PLLs go into the lock when the output of a phase detector is zero, therefore to drive VCO an integrator ...
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1 answer
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Modelling digital DLL for CDR for simulation/modelling purposes only

I have done a Verilog module for clock and data recovery (CDR) using DLL ( this is for simulation purposes only) I used Modelsim for simulation. In the transmitter (Tx), I only have a (clock that has ...
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1 vote
2 answers
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High frequency BLDC control for parallel speed and position control. Looking for thoughts

I was not able to find a similar topic but am kind of stuck with my problem. What am I doing? I am trying to control the speed of a BLDC Motor very precisely but have to control the position of the ...
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Can I use LVCMOS output crystal in 50 ohm system

I have a 50 ohm clocking system in a very low noise environment (RADAR). I want to use a Abracon 100 MHz VCXO (this one), which has a 3.3V LVCMOS output. Below you can see the block diagram of the ...
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2 answers
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Noisy out from the PLL

I have designed a PLL using an ADF4106 and a VCO. I have taken references from CN0290. I am able to get the desired output from the design, but there are other unwanted peaks in the output. I have ...
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1 vote
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NE564 PLL chip operates on PCB only with loop filter pin 14 floating

This circuit has been implemented on my PCB. However, when I test this circuit (without the DRV135UA), it surprised me that the PLL works except Pin 14 of NE564D (V_PLL). At Pin 14, I did not measure ...
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3 answers
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Creating a digital PLL

I want to drive a quartz crystal resonator at its resonant frequency so I need to stay locked on to its resonant frequency as its resonant frequency changes. I'm using an FPGA to do this. I want to ...
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VCO output is its maximum frequency

I am trying to design PLL for generating 122.8MHz from 40 MHz REFIN. I am following the CN0290 EVM reference for the design. I have used CVCO33CL-0110-0150 VCO in the place of VCXO in EVM. When I am ...
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ADF4106 RF input range

I am trying to design PLL for generating 122.8MHz from 40 MHz REFIN. I am following the CN0290 EVM reference for design. As you can see, in the EVM REF_INPUT is of 10MHz and 100MHz frequency is being ...
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1 answer
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Fractional output from integral PLL

Is it possible to get a fractional output from an integral output PLL? I am using ADF4106. Is it possible to generate 122.8MHz using this PLL?
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3 votes
1 answer
80 views

Phase relationship of multiple Fractional-N PLLs with same reference clock

I think I understand the general operation of PLLs in the case where a single reference clock generates a single output clock. Once the PLL is locked, there is a deterministic relationship between the ...
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2 answers
105 views

PLL or DLL with controllable phase

I have a clock signal coming from an instrument that I need to use to synchronise other instruments. However secondary instruments need to have different phases and I need to be able to sweep the ...
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What is the output of this VCO?

I am using ROS-43-119+ from Mini-circuits. I need a VCO that can generate a 40MHz frequency. ROS-43-119+ can generate my required frequency by controlling the tuning voltage. I need sinewave output ...
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When input clock frequency out of range, provide alternative clock

I have a system that receives a ~352 MHz clock signal that is divided down to provide clock signals (that are phase synchronous with the 352 MHz master clock) to various modules. The precise ...
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3 answers
65 views

VCXO output frequency tuning

I am planning to use this VCXO CVSS-945-100.000 to generate 40MHz by providing the control voltage from a PLL. The datasheet mentions control voltage as below: Is it possible to generate 40MHz using ...
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267 views

Loop filter bandwidth calculation

I am trying to Design a PLL using ADF4106 and VCXO. The reference frequency is 10MHz and VCXO output is 40MHz. I need to design a Loop filter for converting charge-pump voltage from PLL into Control ...
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1 answer
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PLL input circuitry

I am trying to design a PLL using the ADF4XX series PLL from Analog Devices. I am taking design references from the EVM schematic. I will be providing 10MHz reference and generating 40MHz using CVSS-...
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2 votes
0 answers
72 views

Disadvantage of 3rd order vs 2nd order digital PLL with high C/N0?

I tried to determine the best choice between an aided 2nd order and an unaided 3rd order carrier digital PLL in a context where the \$C/N_0\$ is very high. From all aspects, the 3rd order loop seems ...
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How to count individual cycles of a 24 GHz clocking signal? [duplicate]

Are there digital counters or similar circuits available that can count cycles or even half cycles (e.g., by threshold crossing) of a 24 GHz clocking signal? I am not looking for frequency counters ...
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