Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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Disadvantages of DLL clock generators compared to PLL

I've been learning from many publications that DLLs offer various advantages over PLLs, such as low-jitter performance and fast locking. So, recently, DLLs have been used for local clock generation in ...
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What is wrong with my Simulink model of a first order Delta Sigma Modulator?

I'm trying to design a Delta-Sigma Modulator for frequency synthesizer applications and am (just right now) figuring out how to properly configure a first order DSM in Simulink. I've made a few small ...
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VCO Tuning with MOSCAPs

I'm designing an integrated VCO for use in an FM Radio frequency PLL. In order to reduce the external part count, I had the idea of using MOSCAPs as the frequency tuning element instead of external ...
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Is it possible to change the reference clock in a cpu while it is running

I understand that PLLs have a settling time but if I were to do a hardware modification that changes Vco of a reference clock to scale based on temperature of my CPU, would I be able to do so while ...
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49 views

Does imposing an odd initial condition reduce spurs in MASH Delta-Sigma Modulators that has second order stages?

I've been reading about how fractional spurs can be reduced in a Digital MASH Delta Sigma Modulator (especially for application with a fractional-N PLL) by having the initial condition of the first ...
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What is the “input” being fed into a Delta-Sigma Modulator in a Fractional-N PLL? Are bits needed for a specific resolution at the input or output?

I'm doing some reading into Fractional-N PLL design and I have a bit of conceptual confusion regarding a delta-sigma modulator used to toggle the modulus of a divider. If you're trying for a certain ...
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LM565/NE565 Spice modeling in Orcad PsPice/Proteus/Multisim

"Q: Display the outputs specified in the following figures in the simulation software and the results. That's it." I have trouble getting the answer from this circuit. When I realized that ...
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FPGA - synchronise “very close” clock from signal

This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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312 views

Clock jitter - ppm, ui, ps

I using Xilinx FPGA and need to use its PLL (MMCM or Clk Wizard) I have on my board LVDS 200MHz clock with 50 ppm frequency jitter, I took this and go to some converted I can find on the internet and ...
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Phase locked loop for Grid synchronization

Is there any IC available to implement PLL for the single-phase grid-connected inverter? one solution that I came across is using Texas instruments C2000 series microcontrollers and I also searched ...
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Analog/Linear PLL or DPLL or ADPLL?

I am a 3rd Engineering students who is preparing for analog/Mixed Signal design job. I want to do a project regarding PLLs. Which PLL should I choose to make.? There are different types of PLL ...
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How is a Multi-Bit Delta-Sigma Modulator used to toggle the modulus for a Fractional-N PLL?

I'm doing some reading about fractional-N PLL design, and a large part of this reading has been about Delta-Sigma Modulators, a method of producing a binary string to toggle the frequency divider ...
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62 views

Working out the Transfer Function of a PLL Loop given by the Analog Devices ADISim Tool

This is a followup question to this question, I asked previously. My synthesizer PLL still isn't locking and it must be the introduction of the mixer and filter into the loop that's causing the issue ...
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PLL Layout guidelines

I am designing a custom board using HMC833LP6GE. I am taking schematic reference from the Evaluation module. There will be onboard DS-PIC MCU for controlling the PLL. The reference input can be fed ...
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1answer
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Trouble designing and understanding lowpass filter in analog (mixer) phase-locked loop (PLL)

I'm trying to design a software-based PLL that mimics the behavior of an analog PLL based on a 4-quadrant mixer as the phase detector (PD). The input signal is a sinusoid of unknown frequency between \...
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What are the applications of external feedback for FPGA PLL's?

I see that most FPGA vendors allow users to use an external clock signal as the feedback input to a PLL. When provided external feedback (which originates ultimately from the PLL output), the PLL will ...
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59 views

Runtime reconfigurable FPGA clock routing

I have a design with multiple inputs and outputs that should have different bit rates, configurable at runtime. Since there are more I/Os than PLLs, I need to share some PLLs, e.g.: port 1: 1 Mbps ...
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Using PLLs inside FPGAs

A document states that: Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking. You can use ...
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Issue for TCXO through frequency multiplier (PLL) for STM32 I2S signal

I try to use TCXO (KT7050A24576KAW33TAD) at 24.576 MHz through frequency multiplier (PLL) x4 (NB3N511DG) to clock the I2S bus (SAI domain) at 98.304 MHz on a MCU (STM32L4R5VIT6). Signals are not what ...
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Why does the overshoot exist when transmitter turns on?

I am implementing power amp. with 16-QAM. Because of issue on power consumption, I am using time division duplex (TDD). By TDD, the power amp. turns off if the carrier wave is not needed and vice ...
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1answer
38 views

PLL design VCO and RC filter connection in real sense and not in block diagram level

The above give basic block diagram of PLL, but according to my understanding after the output of Charge pump with loop filter , VC ie the control source for the VCO is connected to which part of the ...
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33 views

I want to generate two references pulses (Rising and Falling) generated from rising and falling edges of the reference pulse clock signal

I want to generate two references pulses (Rising and Falling) generated from rising and falling edges of the reference pulse clock signal. How can I do this with CMOS logic ?
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Is fractional PLL the key functionality that defines whether a microcontroller is able to generate an analog TV signal?

I've been researching microcontrollers with the goal of outputting NTSC and/or PAL video signals. And when I look at the microcontroller specifications, it appears to me that the single most important ...
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43 views

External Clock for AD7193 ADC

I'm attempting to design a data logger and the AD7193 seems to fit my requirements. I'd like to drive it by an external clock in a GPS-disciplined loop while sampling at an integer rate, as this would ...
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what is a BIOs Programmer used for?

Never used a BIOs programmer before. Wondering what are they for. For my current project, I need something to configure my PLL chip, which has an SPI interface. I already have the evaluation board ...
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What is the purpose of PLL in a general microcontroller

An ARM Cortex-M4 based microcontroller like TM4C123GH6PM is designed with multiple clock sources with a processor core clocked at 80MHz provided by the PLL, which, from what've read in NI-What is a ...
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Approach to an unknown orthogonal Beta Signal with a known alfa in single phase dq transformation

I am trying to implement a PLL controller to the MCU for tracking single phase line voltage . I get samples via an opamp circuit with a DC offset and the samples' raw values vary between |-244 , +244| ...
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Low pass filter target frequency for a mixed signal frequency synthesizer

I'm building a frequency synthesized local oscillator with coarse and fine tuning to span 30.5 to 32MHz. The design follows the following block diagram (bits not essential to this question removed ...
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Why the program does not work when I enable PLL on STM32F4?

When I try to the code below, program running very well. But when I enable PLL_ON bit, the program does not work. Code that works: ...
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Microcontroller internal Clock frequency tolerances [duplicate]

I am having this microcontroller - S32K142 64 Pin 5V Core voltage Microcontroller Reference Manual I want to use the FIRC and want to see the frequency tolerance of the FIRC. Can someone help to find ...
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108 views

What's the precision of a quartz crystal?

Crystal datasheets usually list the following parameters: The Frequency Tolerance of a crystal is defined as the allowable deviation from the specified Frequency when measured at 25°C or room ...
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Phase Locked Loop Frequency Multiplier x 100

Can someone please help me with selecting resistors and caps. I have a PLL set up using a CD4046BE (PC2) connected to 2 x CD4017 decade counters to enable a x100 multiplier. My input frequency range ...
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Ways to observe clock signal of an STM32 MCU

Is there a nice way to be able to observe the clock signal in an oscilloscope to validate my settings for clock speed? After setting it to 168 MHz with PLL for an STM32F407VGT6 MCU let's say.
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How can I gate the output of this phase detector?

I want to make a PLL which will lock to the subcarrier of a composite video signal during colourburst. The colourburst is present for about 2.25uS of each scanline which is 64uS long. So during that 2....
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How to choose between different equivalent PLL/divider configurations?

If there are multiple ways to get the required clocks for a given CODEC, how do you choose between them? For example, if a CODEC can accept 64fs, 128fs, 256fs, and has an internal PLL that can ...
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How to make a PLL output the phase modulo 360°?

I have made a PLL to obtain the mechanical angle encoded in quadrature sine signals (the envelope of a resolver output) ; it implements: error=in-out is approximatively equal to sin(in-out)=sin(in)cos(...
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PLL for Audio Frequency VCO using R divider

I'm attempting to design a PLL for an analog, audio frequency VCO, but I've run into a conceptual problem. I can't reasonably use a divider in the feedback path. My reference frequency would ...
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Does the PLL circuit which is used to increase frequency N times increase also the phase?

If we have a PLL with the following function: The output freq. becomes N times the input freq. But how about the phase difference between the input and the output?
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How does a PLL recover the clock from digital data signals and what does recovery mean?

Is there an easy way to explain this process to a non-expert? I read many places but couldn't figure out. I can understand the job of PLL which locks the output frequency to the fed back frequency ...
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Why must the VCCA be powered in Cyclone 10 LP even if PLLs are not being used?

The device documentation related to the Cyclone 10 LP FPGA states that "you must power up VCCA even if the PLL is not used". We were comparing the power dissipation of a Microsemi IGLOO2 FPGA with ...
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How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
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How do I find the transfer function of this op amp circuit?

This is a phase detector circuit used in PLL, the inverting input is a sinewave and there is a reference signal which is a square wave. How would the output look like if the inputs are in phase and ...
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Can an FPGA PLL lose lock if it is supplied with a stable input clock signal?

In an FPGA (Intel) design I have a PLL that is provided with a stable clock from a clock module on the PCB. The design is as shown on the figure below. The PLL has a lock indication. After the FPGA ...
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Converting PLL Discriminator into Doppler error

I'm writing a GPS receiver SDR software, and I have calculated the PLL discriminator ouptut as atan(Q_Prompt,I_Prompt) I would like to know the formula that converts the discrminator output to doppler ...
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FM Detector Using LM565

I am currently working on a power line communication project. I want to send an audio signal through the power line. In order to do that I would need to modulate my signal and in this project I am ...
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166 views

Problem in understanding how LM565 increases the VCO frequency

We were tinkering with an LM565 (PLL IC) in school and I noticed that despite the fact that the maximum frequency of VCO was 3.5 kHz, I was able to use the PLL up to circa 5 kHz with the free running ...
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Oscilloscope Phase Shift

I have a university research that i am conducting right now. My objective, as a first step, would be to phase shift an NRZ signal at high frequencies >40GHz, assuming this signal is already locked ...
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Multiplication of 2 waves in a phase detector of a phase-locked loop

What would be the product of a 60Hz square wave and a 60Hz sine wave with an approximate phase shift of -45 degrees? I could not find a proper solution to this anywhere.
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Loop Filter in an ADPLL

I am implementing an ADPLL in an FPGA with VHDL, and I am encountering a problem in correctly implementing the loop filter. The code that I currently have for the loop filter is the following : ...
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Increasing Locking range of ADPLL in VHDL on FPGA for FM Demodulation?

I am trying to implement an all digital PLL so as to demodulate an FM signal from the input. The centre frequency of the test signal is that of 140kHz. The system works fine upto a deviation of +-...

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