Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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153 views

Circuit for converting 48kHz to 12MHz

I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
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1answer
188 views

PLL multiplier input output phase

I need to pass a 100MHz continous clock between an MCU and FPGA. The clock edges are aligned to various interface signals between both devices. I wonder if I can pass a submultiple of the clock like ...
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45 views

PLL deviation from matched frequency

If there is a phase difference between output and the input of a PLL, an error signal would be generated by phase detector, implying that the loop yet needs to settle to a final state. This may happen ...
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39 views

Understanding PLL VCO Integrator Phase-shift

In many PLL phase loop theory discussions, it's often said that the VCO acts as an integrator and therefore has a 90 degree phase shift. I've seen derivations of the VCO transfer function and this ...
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32 views

Definition of Phase Locked Loop

After learning some basics of Phase Locked Loop, I came to a conclusion that it may be defined as a circuit, which in its most basic form, tries to lock(equate) both the phase and the frequency. But ...
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13 views

How to connect ADF4153 modem oscillator serially with PC without using SDP board?

I tried to connect ADF4153 modem oscillator with PC using STC15W4K56S4 that I bought from Aliexpress. My PC is reading the modem but the program is not, so I am trying to connect the ADF4153 ...
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49 views

FM demodulation using PLL?

I have to demodulate a square wave FM+PWM modulated signal, so for the FM demod I'm using a PLL with a positive edge sensitive comparator to lock on frequency only (CD4046BE). Carrier frequency is ...
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60 views

Phase Detector for PLL: Operation and Realization

I have some doubts about the realization and the operation of a phase detector for a PLL. My reference book is "The Design of CMOS Radio-Frequency Integrated Circuits" (Thomas H. Lee). The basic ...
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3answers
258 views

4 quadrature clock vs 2 quadrature clock + falling edges

I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL. I read several papers about this subject and I found about ...
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508 views

How to choose reference current in a charge pump circuit?

The figure shows a charge pump circuit using servo loop. The circuit is from Razavi RF Microelectronics text book. How to fix the Iref in the first branch?
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1answer
141 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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1answer
665 views

Is it possible to replicate the Thomas Henry X-4046 circuit using the PLL_Virtual component in Multisim?

The part of the circuit I'm having trouble implementing is the transistor pair that are used to control the output frequency (going into pin 11 of the 4046). I have removed the Exp FM, Linear FM, ...
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27 views

Grid Tie Inverter Anti islanding

I was wondering about anti islanding design. Using grid tie inverters is usually the best choice when not investing in batteries, but suppose you have batteries and want the confort of grid tie AND ...
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2answers
79 views

How does a microcontroller provide a frequency higher than its crystal frequency? [duplicate]

I have a microcontroller which is connected to an 8MHz crystal. I have a schematic which has a QSPI flash IC connected to it whose clock is provide by the micro and happens to be 48MHz. I want to ...
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1answer
297 views

How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
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52 views

Finding capacitive load driving capability of a Sine wave crystal oscillator

I will be using Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 This sine wave oscillator will be on a separate PCB which we are calling as "...
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63 views

Driving high impedance load with Crystek Sine Wave Oscillator- CCSS-945X-25-100.000

I am planning to use Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 . Now in datasheet of oscillator, output power mentioned is 5dBm into 50 ...
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1answer
46 views

Is an unlocked PLL an open-loop clock? And is a locked PLL a closed-loop clock?

What is the difference between an open-loop clock and a closed-loop clock? Is a PLL with an oscillator lock a closed loop clock? Is a PLL without an oscillator lock an open-loop clock?
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38 views

Increasing peak to peak voltage using 1:2 balun

I came across this post on TI E2E forum. In this post user wants to drive LMK04832 PLL IC clock inputs using a sine wave. User has a source of sine wave with -1.53dBm or 0.528Vpkk which they will ...
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143 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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123 views

Help with design of current DAC

I am required to design a current DAC (64 element NMOS) that sinks the current of another current DAC (16 element PMOS). The specs are as follows: 1. The smallest current output from the PMOS DAC is ...
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1answer
48 views

Confusion regarding the term“locking” in PLL

I am trying to learn PLL from a website https://www.allaboutcircuits.com/technical-articles/what-exactly-is-a-phase-locked-loop-anyways/ ]1 I came across a sentence containin[g the term "lock" ...
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224 views

Function of pll?

What is the relationship between input phase and output phase of a pll(phase locked loop)? Why is it called phase locked? Does it keeps/locks output phase to phase of input meaning output has same ...
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1answer
130 views

Two details about phase noise have been confusing me for a long time. Hope to be resolved

Just like FLOYD M. GARDNER said in the PhaseLock Techniques, 3rd Edition: "In light of that success in spectrum analyzers, a practitioner’s answer to the question above is: The spectrum of phase noise ...
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275 views

Loop bandwith and open-, closed- loop gain in ADIsimPLL

I'm want to use ADIsimPll to calculate the loop filter properties for a PLL I want to build. I read some things in the programs help topics which I find somehow strange. Maybe you guys can help me out ...
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Conclusions about PFD/Charge pump simulation

I have built a Sequential NAND based phase detector with a charge pump that includes a differential amplifier and I want your help make some conclusions about the results I got running all the ...
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22 views

Sequential NAND Based Phase-Frequency Detector output

I'm trying to understand the output of my phase detector only for a pulse that goes from zero to one. here is my schematic: (ref is Clk_ref, and Div is Clk_out, both come from an outside circuit) ...
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51 views

Can someone help me in getting to know what is wrong with my Frequency multiplier circuit using 565?

I just learned the working of NE565 and I tried to simulate a Frequency as multiplier using 565 in Proteus , but I don't know why PIN 4 of my NE565 is not giving any output . Its coming plane blank in ...
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27 views

comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
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2answers
90 views

Phase detection with non-ideal PFD

I'm trying to simulate for Phase Frequency Detector with the following implementation: and inside NAND_PFD: NOTE: the triangles on the right are inverters and not amplifiers. I'm currently ...
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1answer
38 views

Bootstrapped charge pump design for phase frequency detector

I'm trying design a charge pump as it's showed in the following link: https://ibb.co/DDc6DsF (for some reason I couldn't upload it, I don't know why). what I don't understand is what is \$I_{ref}\$ (...
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Can I input a square wave LO into a mixer?

I would like to downconvert a signal at 169.55MHz (10khz bandwidth) into an IF of 20.4MHz. For that purpose, I need a local oscillator of 149.15MHz or 189.95MHz. But... of course, I cannot find a ...
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314 views

How Replica Feedback bias circuit rejects supply noise?

I attached the circuit diagram along with a short description of its working principle. However, it's not clear how the circuit rejects supply noise. It will be great if someone can brief about what ...
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1answer
790 views

LTSpice simulation stalls after 100ms transient with 'Heightened Def Con'

I simulate a system of two mutually delay-coupled electronic clocks (DPLLs - digital phase-locked loops). This worked well and also in reasonable time so far. However, moving into a particular regime ...
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1answer
113 views

PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
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44 views

RF sampling ADCs(ADC12DJ3200 ),PLLS and regulators placement and layout

I am novice in PCB component placement and layout. I have just started my career in Hardware design. We have designed a schematic for Data Acquisition System. In our design, we are using three RF ...
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What is the difference between first order, second order and third order phase locked loops?

What does PLL order represent? What are the disadvantages in order 1 & 2 PLL comprared to order 3? How to choose the pll type for an application like QPSK demodulator?
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1answer
269 views

How to test PLL for step input change in phase

I wrote a simulation for second-order PLL and I would like to test it with an input to see whether my PLL can track the phase. I would like to change the phase of my sinusoidal signal with step with ...
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1answer
66 views

Choosing PLL Loop Filter Bandwidth and Phase Margin for Frequency Ramp Generation

I am new to PLLs and am trying to use one to generate a frequency ramp between 5.725 GHz and 5.875 GHz. I have found tools online that help design loop filters for PLLs, and all of these tools require ...
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2answers
100 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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1answer
64 views

Trouble understanding Loop Filter in a PLL

I'm currently trying to understand the function of a loop filter. But where I'm stuck is that I know the output of the charge pump is a series of current pulses whose width is proportional to the ...
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80 views

Choosing a suitable PFD for PLL

I'm building a capacitive vibration sensor and it has to reject the stray capacitance by locking the LC oscillator at 64 MHz, where I can demodulate relatively small frequency changes. The best way to ...
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1answer
113 views

Why should crystal switching be avoided?

The MC44144 is a gated phase locked loop intended for video applications that is described in its datasheet as "sensitive to shunt capacitance" and that "crystal switching should be avoided". What ...
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33 views

Arty7 Verilog Control PWM input Clk using PLL

I currently running into a problem of creating an instant of the PLL Clk_Wizard from Xilinx IP. My goal for this project is to provide a much faster clock for the PWM module (for exotic FET). I'm very ...
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46 views

Phase noise of a digital PLL

I assume the reader is aware of how a DPLL works. The DPLL oscillates with a frequency of \$F_{out}\$. The DCO free running frequency is \$F_{free}\$. In the model of our DPLL we've only considered ...
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89 views

Common symbol for PLL

Is there a common symbol for PLLs, either for schematics or functional diagrams? I need a symbol which would be easily recognized as a PLL, without having to draw the phase comparator, loop filter, ...
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1answer
53 views

digital PLL - oscillations

I'm building a 3 phase digital PLL and implementing it on a microcontroller. I included a schematic of the SRF-PLL principle that I use. The abc->dq0 transform is done so that the q component for a ...
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1answer
68 views

Phase Frequency Detector without dead zone

How does the two inverter delay stage in Figure 6.14 on page 265 of Design of CMOS RF Integrated Circuits and Systems helps to eliminate dead zone in Phase Frequency Detector ? How does the PFD ...
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93 views

VCO circuit Analysis

can you help me with the basic comprehension of this Voltage Controlled Oscillator scheme (it was used in a PLL)? I do not understand why there are two varactors instead of one, and the role of the ...
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125 views

Is it possible to create a PLL purely in digital design, if so how?

Provided that we want to reduce jitter on an a periodic input signal (square wave between 0 and Vcc) which is only in some 100 of KHz range, one possibility is to create a system purely using RTL code ...