Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

57 questions with no upvoted or accepted answers
Filter by
Sorted by
Tagged with
2
votes
1answer
130 views

Two details about phase noise have been confusing me for a long time. Hope to be resolved

Just like FLOYD M. GARDNER said in the PhaseLock Techniques, 3rd Edition: "In light of that success in spectrum analyzers, a practitioner’s answer to the question above is: The spectrum of phase noise ...
2
votes
1answer
118 views

PCIe Gen2 PLL lock issue

Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY. This PHY's PLL requires a 100 MHz reference clock. We are using the reference ...
2
votes
0answers
43 views

Can I use a PLL to generate the *phase* component of an SSB signal?

I want to use Kahn's method of Envelope Elimination and Restoration (EER) to produce a single-sideband, supressed-carrier (SSB) signal. Kahn simply clipped a low-level SSB signal, but I wonder if it ...
2
votes
0answers
376 views

Matlab Phase Locked Loop Design : FM Demodulation

EDIT: It seems I've asked too much at once here. I'll do some more studying and come back if I have more specific questions. I'm trying to design an analog phase locked loop in Matlab. I've read ...
2
votes
0answers
71 views

Intermittent control signal injection clock sync

I have a big challenge in my design to overcome: I need clock frequency accuracy of <0.2ppm with incredibly low power consumption. What we are doing currently is, using a 3G transceiver' baseband ...
1
vote
0answers
51 views

Can someone help me in getting to know what is wrong with my Frequency multiplier circuit using 565?

I just learned the working of NE565 and I tried to simulate a Frequency as multiplier using 565 in Proteus , but I don't know why PIN 4 of my NE565 is not giving any output . Its coming plane blank in ...
1
vote
1answer
38 views

Bootstrapped charge pump design for phase frequency detector

I'm trying design a charge pump as it's showed in the following link: https://ibb.co/DDc6DsF (for some reason I couldn't upload it, I don't know why). what I don't understand is what is \$I_{ref}\$ (...
1
vote
0answers
46 views

Phase noise of a digital PLL

I assume the reader is aware of how a DPLL works. The DPLL oscillates with a frequency of \$F_{out}\$. The DCO free running frequency is \$F_{free}\$. In the model of our DPLL we've only considered ...
1
vote
0answers
89 views

Common symbol for PLL

Is there a common symbol for PLLs, either for schematics or functional diagrams? I need a symbol which would be easily recognized as a PLL, without having to draw the phase comparator, loop filter, ...
1
vote
2answers
80 views

Doubt about Phase Locked Loop

How is it possible that the Signal Output will have the same frequencies as the Reference Signal?\$f_1\$, Frequency of the Reference Signal;\$f_2\$, Frequency of the VCO. Let's assume that \$f_1>...
1
vote
0answers
35 views

PLL with two input frequency within lock range for FM demodulation

I have current output from a photodiode which I believe containing at least two distinct frequencies that is not too far apart from the lock range of a PLL which taking this current as the input ...
1
vote
0answers
58 views

Derivation of stability criterion for type 3 digital PLL

Could anyone help to derive the following expression (4.23) which is the stability criterion for type 3 digital PLL ? Note: Screenshots are taken from Floyd Gardner's book : Phaselock Techniques 3rd ...
1
vote
0answers
113 views

Phase Locked Loop Gain Design- FM Demodulation

Say I am trying to demodulate a message up to 25kHz in frequency, with a peak frequency deviation of 75kHz and a carrier of 1MHz, implying a 200kHz bandwidth using carsons rule. Would I design the ...
1
vote
2answers
320 views

How Replica Feedback bias circuit rejects supply noise?

I attached the circuit diagram along with a short description of its working principle. However, it's not clear how the circuit rejects supply noise. It will be great if someone can brief about what ...
1
vote
0answers
76 views

closed loop zero in second order PLL with a proportional-integral filter

Why does the closed-loop zero in second-order PLL with a PI filter enhance the phase noise near PLL bandwidth frequency? I know that it enhances the phase margin but i can't find the logic behind why ...
1
vote
1answer
298 views

How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
1
vote
1answer
668 views

Is it possible to replicate the Thomas Henry X-4046 circuit using the PLL_Virtual component in Multisim?

The part of the circuit I'm having trouble implementing is the transistor pair that are used to control the output frequency (going into pin 11 of the 4046). I have removed the Exp FM, Linear FM, ...
1
vote
3answers
258 views

4 quadrature clock vs 2 quadrature clock + falling edges

I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL. I read several papers about this subject and I found about ...
1
vote
0answers
172 views

pragma directives to set frequency for dsPIC33

currently I set the frequency of my dsPIC33EV with following code: ...
1
vote
0answers
111 views

What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?

Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
1
vote
0answers
98 views

TDF transmitter to arduino

1) I have a project to build a time clock based on the TDF signal on 162kHz, from Allouis, France. The time coding is similar to DCF-77 so I will send it to an Arduino with proper code. I managed to ...
1
vote
0answers
73 views

HD-SDI monitor locks-unlocks

I have an SD/HD/3G-SDI output driven by a LMH0303, pretty much stock standard application circuit straight out of the datasheet. The SDI datastream is generated by an XC7K70T FPGA, so I have great ...
1
vote
0answers
66 views

Digital PLL reference noise rejection

I have a fully digital implementation of a PLL. The problem that I have is the white noise coming from the PFD (you can view it as input jitter). I would like to filter it a lot, but an implementation ...
1
vote
0answers
96 views

RF frequency synthesis - how low power can I reasonably go?

I'm an undergrad working on the analog frontend for a student-developed cube satellite. After looking at the options, I've decided to use the CML Microcircuits CMX994 for the receiver and the CMX998 ...
1
vote
0answers
113 views

Disciplining a TCXO from a broadcast reference source

In the UK (and much of europe), a broadcast time and frequency reference is available in the form of the MST radio time signal. This is broadcast using on-off keying on a frequency of 60 kilohertz, to ...
1
vote
0answers
327 views

Frequency locked loop for input jitter rejection

I have an application where I want to multiply from a xtal oscillator at 32KHz to a system clock of 40MHz. A standard PLL isn't going to do the job, because the 32KHz jitter is measured in ns. Since ...
1
vote
0answers
1k views

Altera ModelSim simulating PLL

In my design, I make use of the ATLPLL Library/IP which is to convert the clock frequency accordingly for my design. I am Using De0-Nano board for my project which has cyclone IV FPGA. The ATLPLL ...
1
vote
0answers
1k views

stm32f2xx HSI configuration does not work correctly

I'm using below settings (in SystemInit function) to configure a STM32F215RG MCU to work at maximum speed (120MHZ) with USB support: ...
0
votes
0answers
18 views

How to connect ADF4153 modem oscillator serially with PC without using SDP board?

I tried to connect ADF4153 modem oscillator with PC using STC15W4K56S4 that I bought from Aliexpress. My PC is reading the modem but the program is not, so I am trying to connect the ADF4153 ...
0
votes
1answer
77 views

FM demodulation (not!) using PLL?

I have to demodulate a square wave FM+PWM modulated signal, so for the FM demod I'm using a PLL with a positive edge sensitive comparator to lock on frequency only (CD4046BE). Carrier frequency is ...
0
votes
0answers
27 views

Grid Tie Inverter Anti islanding

I was wondering about anti islanding design. Using grid tie inverters is usually the best choice when not investing in batteries, but suppose you have batteries and want the confort of grid tie AND ...
0
votes
1answer
64 views

Driving high impedance load with Crystek Sine Wave Oscillator- CCSS-945X-25-100.000

I am planning to use Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 . Now in datasheet of oscillator, output power mentioned is 5dBm into 50 ...
0
votes
0answers
23 views

Conclusions about PFD/Charge pump simulation

I have built a Sequential NAND based phase detector with a charge pump that includes a differential amplifier and I want your help make some conclusions about the results I got running all the ...
0
votes
0answers
22 views

Sequential NAND Based Phase-Frequency Detector output

I'm trying to understand the output of my phase detector only for a pulse that goes from zero to one. here is my schematic: (ref is Clk_ref, and Div is Clk_out, both come from an outside circuit) ...
0
votes
0answers
27 views

comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
0
votes
0answers
44 views

RF sampling ADCs(ADC12DJ3200 ),PLLS and regulators placement and layout

I am novice in PCB component placement and layout. I have just started my career in Hardware design. We have designed a schematic for Data Acquisition System. In our design, we are using three RF ...
0
votes
0answers
80 views

Choosing a suitable PFD for PLL

I'm building a capacitive vibration sensor and it has to reject the stray capacitance by locking the LC oscillator at 64 MHz, where I can demodulate relatively small frequency changes. The best way to ...
0
votes
0answers
33 views

Arty7 Verilog Control PWM input Clk using PLL

I currently running into a problem of creating an instant of the PLL Clk_Wizard from Xilinx IP. My goal for this project is to provide a much faster clock for the PWM module (for exotic FET). I'm very ...
0
votes
0answers
40 views

Fractional-N frequency synthesis does not work on Mach XO2 FPGA

I'm using the Right side PLL to implement a clock generator on a Mach XO2 7000 FPGA that takes in a 50 MHz clock generated by the Left side PLL and outputs a clock that can be changed from 50 MHz to ...
0
votes
0answers
292 views

Using LTSPice to make Function Blocks for SIMULINK

I have a PLL that I want to model in Simulink using the control theory toolkit. I have the schematics for the PLL in LTSpice. Does anyone know of a way that I can integrate the spice model with my ...
0
votes
0answers
145 views

Frequency multiplier from kHz to MHz

I'm not familiar with electronics at all, and would like to get some ideas to implement frequency multiplication of LVCMOS. I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
0
votes
1answer
45 views

Stability Criteria of Type 3 Digital PLL

I suppose we can derive the stability criteria based on poles of open-loop transfer function of F(z) in expression (4.11). However, the pole analysis does not help in deriving the stability criteria ...
0
votes
0answers
26 views

First order PLL power consumption

For a system level project I want to estimate the impact having a single vs. multiple PLLs. Is there a first order estimate that relates power, jitter (total integrated phase noise) and possibly ...
0
votes
1answer
65 views

PLL : conceptual confusion

In the PLL it is said that Capture range is the frequency from which the PLL starts functioning and Locked range is the frequency where the output of VCO is equal to that of reference oscillator ...
0
votes
1answer
143 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
0
votes
1answer
48 views

PLL integrated CCC, Microsemi/Actel ProASIC3 nano Flash Family FPGA, A3P125

I have Micosemi/Actel ProASIC3 Nano A3P125,VQ100 Chip. I was looking for the PLL integrated CCC to connect 100MHz Clock and I have been through the manual ProASIC3 FPGA Fabric User’s Guide. where i ...
0
votes
0answers
338 views

Why doesn't my STM32F4 PLL seem to work?

I've spent a few days unsuccessfully trying to get my Nucleo F401RE to use the PLL for its system clock. I've configured it to use the 8MHz HSE and output 84MHz as the system clock. The code stops ...
0
votes
2answers
277 views

Loop bandwith and open-, closed- loop gain in ADIsimPLL

I'm want to use ADIsimPll to calculate the loop filter properties for a PLL I want to build. I read some things in the programs help topics which I find somehow strange. Maybe you guys can help me out ...
0
votes
2answers
123 views

Help with design of current DAC

I am required to design a current DAC (64 element NMOS) that sinks the current of another current DAC (16 element PMOS). The specs are as follows: 1. The smallest current output from the PMOS DAC is ...
0
votes
1answer
85 views

Simulation of PLL

I am simulating a PLL with a reference frequency of 25 MHz, VCO freq of 450 MHz. I want to plot the gain versus frequency offset of the closed loop PLL in cadence. How should I give the inputs to get ...