Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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Can I use a PLL to generate the *phase* component of an SSB signal?

I want to use Kahn's method of Envelope Elimination and Restoration (EER) to produce a single-sideband, supressed-carrier (SSB) signal. Kahn simply clipped a low-level SSB signal, but I wonder if it ...
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Intermittent control signal injection clock sync

I have a big challenge in my design to overcome: I need clock frequency accuracy of <0.2ppm with incredibly low power consumption. What we are doing currently is, using a 3G transceiver' baseband ...
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How to interpolate phase noise curves?

I am trying to calculate the phase jitter of a transmitter. A phase noise profile is given, say: ...
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Disadvantage of 3rd order vs 2nd order digital PLL with high C/N0?

I tried to determine the best choice between an aided 2nd order and an unaided 3rd order carrier digital PLL in a context where the \$C/N_0\$ is very high. From all aspects, the 3rd order loop seems ...
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Design for a PLL Auto-Locking Circuit

I am looking into electrolysis efficiency using an auto-locking PLL circuit that is supposed to latch onto the resonant frequency of the electrolysis cell, a frequency determined by the inductance of ...
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How to make a PLL output the phase modulo 360°?

I have made a PLL to obtain the mechanical angle encoded in quadrature sine signals (the envelope of a resolver output) ; it implements: error=in-out is approximatively equal to sin(in-out)=sin(in)cos(...
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Two details about phase noise have been confusing me for a long time. Hope to be resolved

Just like FLOYD M. GARDNER said in the PhaseLock Techniques, 3rd Edition: "In light of that success in spectrum analyzers, a practitioner’s answer to the question above is: The spectrum of phase noise ...
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Matlab Phase Locked Loop Design : FM Demodulation

EDIT: It seems I've asked too much at once here. I'll do some more studying and come back if I have more specific questions. I'm trying to design an analog phase locked loop in Matlab. I've read ...
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How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
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PLL Clock distribution

I am generating 40MHz clock using ADF4106 PLL Frequency Synthesizer with VCO CVCO55CL-0038-0042. I am using this 40MHz generated frequency for distribution using ADCLK846. Output power from PLL is -3....
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High frequency BLDC control for parallel speed and position control. Looking for thoughts

I was not able to find a similar topic but am kind of stuck with my problem. What am I doing? I am trying to control the speed of a BLDC Motor very precisely but have to control the position of the ...
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NE564 PLL chip operates on PCB only with loop filter pin 14 floating

This circuit has been implemented on my PCB. However, when I test this circuit (without the DRV135UA), it surprised me that the PLL works except Pin 14 of NE564D (V_PLL). At Pin 14, I did not measure ...
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Signal path / configuration help for a PLL for AWG

In our system signal path, there is a clock signal being sent from the FPGA noted as SCLK. This goes to each component not including the MCU. The way I understand this is that the PLL receives the ...
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What is wrong with my Simulink model of a first order Delta Sigma Modulator?

I'm trying to design a Delta-Sigma Modulator for frequency synthesizer applications and am (just right now) figuring out how to properly configure a first order DSM in Simulink. I've made a few small ...
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Why does the overshoot exist when transmitter turns on?

I am implementing power amp. with 16-QAM. Because of issue on power consumption, I am using time division duplex (TDD). By TDD, the power amp. turns off if the carrier wave is not needed and vice ...
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Approach to an unknown orthogonal Beta Signal with a known alfa in single phase dq transformation

I am trying to implement a PLL controller to the MCU for tracking single phase line voltage . I get samples via an opamp circuit with a DC offset and the samples' raw values vary between |-244 , +244| ...
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Phase Locked Loop Frequency Multiplier x 100

Can someone please help me with selecting resistors and caps. I have a PLL set up using a CD4046BE (PC2) connected to 2 x CD4017 decade counters to enable a x100 multiplier. My input frequency range ...
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How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
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How do I find the transfer function of this op amp circuit?

This is a phase detector circuit used in PLL, the inverting input is a sinewave and there is a reference signal which is a square wave. How would the output look like if the inputs are in phase and ...
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Oscilloscope Phase Shift

I have a university research that i am conducting right now. My objective, as a first step, would be to phase shift an NRZ signal at high frequencies >40GHz, assuming this signal is already locked ...
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Can someone help me in getting to know what is wrong with my Frequency multiplier circuit using 565?

I just learned the working of NE565 and I tried to simulate a Frequency as multiplier using 565 in Proteus , but I don't know why PIN 4 of my NE565 is not giving any output . Its coming plane blank in ...
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Phase noise of a digital PLL

I assume the reader is aware of how a DPLL works. The DPLL oscillates with a frequency of \$F_{out}\$. The DCO free running frequency is \$F_{free}\$. In the model of our DPLL we've only considered ...
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Common symbol for PLL

Is there a common symbol for PLLs, either for schematics or functional diagrams? I need a symbol which would be easily recognized as a PLL, without having to draw the phase comparator, loop filter, ...
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PLL with two input frequency within lock range for FM demodulation

I have current output from a photodiode which I believe containing at least two distinct frequencies that is not too far apart from the lock range of a PLL which taking this current as the input ...
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Derivation of stability criterion for type 3 digital PLL

Could anyone help to derive the following expression (4.23) which is the stability criterion for type 3 digital PLL ? Note: Screenshots are taken from Floyd Gardner's book : Phaselock Techniques 3rd ...
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Phase Locked Loop Gain Design- FM Demodulation

Say I am trying to demodulate a message up to 25kHz in frequency, with a peak frequency deviation of 75kHz and a carrier of 1MHz, implying a 200kHz bandwidth using carsons rule. Would I design the ...
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closed loop zero in second order PLL with a proportional-integral filter

Why does the closed-loop zero in second-order PLL with a PI filter enhance the phase noise near PLL bandwidth frequency? I know that it enhances the phase margin but i can't find the logic behind why ...
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pragma directives to set frequency for dsPIC33

currently I set the frequency of my dsPIC33EV with following code: ...
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What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?

Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
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TDF transmitter to arduino

1) I have a project to build a time clock based on the TDF signal on 162kHz, from Allouis, France. The time coding is similar to DCF-77 so I will send it to an Arduino with proper code. I managed to ...
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PLL multiplier input output phase

I need to pass a 100MHz continous clock between an MCU and FPGA. The clock edges are aligned to various interface signals between both devices. I wonder if I can pass a submultiple of the clock like ...
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HD-SDI monitor locks-unlocks

I have an SD/HD/3G-SDI output driven by a LMH0303, pretty much stock standard application circuit straight out of the datasheet. The SDI datastream is generated by an XC7K70T FPGA, so I have great ...
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Digital PLL reference noise rejection

I have a fully digital implementation of a PLL. The problem that I have is the white noise coming from the PFD (you can view it as input jitter). I would like to filter it a lot, but an implementation ...
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RF frequency synthesis - how low power can I reasonably go?

I'm an undergrad working on the analog frontend for a student-developed cube satellite. After looking at the options, I've decided to use the CML Microcircuits CMX994 for the receiver and the CMX998 ...
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Disciplining a TCXO from a broadcast reference source

In the UK (and much of europe), a broadcast time and frequency reference is available in the form of the MST radio time signal. This is broadcast using on-off keying on a frequency of 60 kilohertz, to ...
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Frequency locked loop for input jitter rejection

I have an application where I want to multiply from a xtal oscillator at 32KHz to a system clock of 40MHz. A standard PLL isn't going to do the job, because the 32KHz jitter is measured in ns. Since ...
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Altera ModelSim simulating PLL

In my design, I make use of the ATLPLL Library/IP which is to convert the clock frequency accordingly for my design. I am Using De0-Nano board for my project which has cyclone IV FPGA. The ATLPLL ...
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stm32f2xx HSI configuration does not work correctly

I'm using below settings (in SystemInit function) to configure a STM32F215RG MCU to work at maximum speed (120MHZ) with USB support: ...
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Doubt about Phase Locked Loop

How is it possible that the Signal Output will have the same frequencies as the Reference Signal?\$f_1\$, Frequency of the Reference Signal;\$f_2\$, Frequency of the VCO. Let's assume that \$f_1>...
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Costas Loop QPSK/4QAM

I can use a Costas Loop, modified for QPSK/4QAM and recover the frequency and phase successfully when using a pattern of all 1s or all 0s or a pattern that is repetitive for each I and Q data rail (in ...
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Lattice ECP5UM5G: receiving TMDS signal with the FGPA tranceivers

I'm trying to implement a DVI/HDMI receiver in the Lattice ECP5UM5G FPGA. This FPGA has four 5 Gb/s transceivers, that seems to be more than enough for high-resolution HDMI video. Unfortunately, the ...
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ADF4159 phase noise improvement

I integrated the ADF4159 PLL evaluation board with an external HMC510LP5E VCO to generate the desired frequencies for the application I'm working on. I'm using 100MHz reference signal from an ...
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Loop Filter Bandpass Jitter Characteristic in PLL

I was watching some PLL video lectures by Professor Elad Alon, and he explains why intuitively the jitter transfer function of the loop filter to the PLL output has a bandpass characteristic. He says ...
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decimator circuit using dflipflops

I am studying about DPLL. There are questions among CDR papers written by the same researchers. Is the symbol likes step symbol after Adder a quantizer? The output of Decimator by factor 2 is -1,0,+1 ...
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how to calculate the phase noise contribution of an active loop filter in pll

I want to calculate the contribution of each phase-locked loop(pll) module to the total phase noise that has been done in ADIsimPLL. But I'm having trouble calculating the contribution of the loop ...
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how to calculate the transfer function of a differential active loop filter

When I was deriving the transfer function of a differential active loop filter provided by ADIsimPLL, I had some problems. The circuit diagram is shown below. First, for a differential active loop ...
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How does a PLL PFD produce a high frequency?

I am going to work with a PLL and a VCO. I have read and understood the basic procedure in which the charge pump works. I understood that say, when the reference signal (or the divided signal) is up ...
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Modelling digital DLL for CDR for simulation/modelling purposes only

I have done a Verilog module for clock and data recovery (CDR) using DLL ( this is for simulation purposes only) I used Modelsim for simulation. In the transmitter (Tx), I only have a (clock that has ...
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VCO output is its maximum frequency

I am trying to design PLL for generating 122.8MHz from 40 MHz REFIN. I am following the CN0290 EVM reference for the design. I have used CVCO33CL-0110-0150 VCO in the place of VCXO in EVM. When I am ...
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ADF4106 RF input range

I am trying to design PLL for generating 122.8MHz from 40 MHz REFIN. I am following the CN0290 EVM reference for design. As you can see, in the EVM REF_INPUT is of 10MHz and 100MHz frequency is being ...
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