Questions tagged [pll]
PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.
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What is the difference between a PLL and a DLL?
Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what ...
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PLL - why compare phases not frequencies
I have a question about PLL's. The aim of PLL is to get two signals with the same frequencies (there can be a shift in phases, as I understand). So, in this case, why do you use a phase detector to ...
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Why is the MCU clock out waveform sinusoidal and not square pulse
I got a new oscilloscope :) (proud amateur moment)
I am trying to visualize the internal clock of a STM32G431RBT6 MCU. So I built an example program given by the vendor which provides the MCU clock ...
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How can over 24 GHz communication be possible?
I read the article Google wants the US' wireless spectrum for balloon-based Internet. It says to use over 24 GHz frequency spectrum for communication.
Is it ever possible to generate that high ...
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What is the purpose of PLL in a general microcontroller
An ARM Cortex-M4 based microcontroller like TM4C123GH6PM is designed with multiple clock sources with a processor core clocked at 80MHz provided by the PLL, which, from what've read in NI-What is a ...
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How do processors control their clock speed?
I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power.
For something like a desktop processor where the clock ...
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What is the difference between first order, second order and third order phase locked loops?
What does PLL order represent?
What are the disadvantages in order 1 & 2 PLL comprared to order 3?
How to choose the pll type for an application like QPSK demodulator?
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Why do we need phase-locked loops?
I'm very confused about why we need phase-locked loops.
On ScienceDirect.com, it reads:
Phase-locked loops (PLLs) have many applications in the communications world. The main purpose of a PLL circuit ...
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Using PLLs inside FPGAs
A document states that:
Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.
You can use ...
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Why is there a PLL in CPU?
I read that PLL are used in CPU to generate the clock, but I can't understand why.
I don't really have any guess of why this is.
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How do I drive 14.3Mhz clock input from 10MHz?
I intend to use an IC which requires 14.3MHz clock input, but want to drive it from a stable 10MHz source - derived from GPS. How do I turn the 10MHz clock into the 14.3MHz that the IC requires?
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Why do frequency synthesizers often use N/N+1 prescalers?
Frequency synthesizers, like Analog's ADF411x often have prescalers in their PLL which divide by 16/17, 32/33 or 64/65? What's the 2^N+1 value used for?
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All Digital Phase Lock Loop
I'm looking to implement a phase lock in an FPGA without using any external components (other than the ADC). For simplicity locking to a simple binary pulse is adequate. The frequency of the signals ...
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Ways to observe clock signal of an STM32 MCU
Is there a nice way to be able to observe the clock signal in an oscilloscope to validate my settings for clock speed? After setting it to 168 MHz with PLL for an STM32F407VGT6 MCU let's say.
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How does a PLL inside a FPGA work?
I have used Altera FPGAs from last year and I would like to know how the PLLs inside works.
Mainly, really have any kind of analog circuitry inside in order to measure phase-offset between VCO and ...
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3 Hz from a watch crystal
I have a stepper motor which step angle is 2 degrees. I want to display seconds using a needle attached to this stepper.
The watch crystal divides nicely to produce 1Hz pulses, so every second I can ...
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Why microcontroller takes many clock cycles to start up with PLL clock source?
I was looking over the ATTiny85 datasheet and noticed on page 26 that with a PLL clock source, the fastest startup time is 14CK + 1K (1024) CK + 4 ms. Am I misinterpreting what they mean by 1K CK, or ...
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Creating a clock multiplier using a PLL
I understand that PLLs can be used to modify the phase of a clock signal for various purposes. I have also heard that PLLs are often used to multiply clocks.
How can a PLL be used to multiply a ...
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What is a Jaffe-Rechtin PLL?
Eberhardt Rechtin and Richard Jaffe (both involved in NASAs DSN) published this paper (paywalled) on PLL-design and -performance back in 1955. It is referenced quite often, so I wanted to understand ...
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pic32 maximum external frequency while running from internal 8MHz RC oscillator
I am completely new to PICs and I have never worked with a part as complex as this. In particular, I'm wondering if it is possible to generate a reference clock (REFCLKO in the datasheet) at 11.2896 ...
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Can I input a square wave LO into a mixer?
I would like to downconvert a signal at 169.55MHz (10khz bandwidth) into an IF of 20.4MHz.
For that purpose, I need a local oscillator of 149.15MHz or 189.95MHz.
But... of course, I cannot find a ...
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Reconstructing Clock for Serial Signal
Suppose that I have a serial signal (example below), which is transmitted without an accompanying clock signal, I would like find a circuit (using discrete components / ICs, possibly an FPGA, but not ...
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Phase locked Loop in Demodulation
Can someone please clarify how a PLL works and how it can the result is used to deduce phase?
My understanding is that a PLL is used to demodulate in situations when the demodulator knows the carrier ...
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Understanding requirements for USB 2.0 high-speed
I am little bit confused about the requirements of USB 2.0 high-speed.
USB 2.0. high-speed maximum transfer rate is 480 Mbit/s. So from my understanding to fully utilize this data rate one should ...
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Generate a 4.25 GHz using 50 MHz crystal/oscillator and PLL
I want to generate a 4.25 GHz using a PLL and 50 MHz crystal/oscillator.
I am confused as to what I need to look for in a PLL. In a integer-N PLL, the prescalers are 16/17, 32/33, 64/65, etc. So, my ...
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MCU clock drift and radio frequency drift - are they the same?
Let's assume that I have two sensor nodes, one with crystal oscillator running at 24 MHz frequency, the other at 24 MHz + 10 ppm frequency.
To my understanding, in system-on-chip (for example, Texas ...
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Pulse on edge of different clock
I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK).
Now I need a pulse each time a rising edge of the original clock ...
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PLL usage in DIY hobby project [closed]
I was wondering if anybody was using PLL (Phase Locked Loop) in DIY hobby project? If yes what was the application? Did you made it from discrete components (as opposed from one placed in uController ...
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Linearized phase domain model of a PLL - what does a ratio of input phase over output phase mean?
I am trying to design a PLL and want to test it first in Matlab.
I have seen that the phase of the input and output are linearized, but I don't understand what is defined by the input/output phase.
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Can I program a platform independent PLL in VHDL?
Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom ...
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Why should crystal switching be avoided?
The MC44144 is a gated phase locked loop intended for video applications that is described in its datasheet as "sensitive
to shunt capacitance" and that "crystal switching should be avoided".
What ...
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Injection locked frequency dividers
I am beginning to design a monolithic frequency synthesizer (around 2.4GHz) in which I need the maximum of spectral purity. I was looking at injection locked frequency dividers (ILFDs) for use as a ...
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LTSpice simulation stalls after 100ms transient with 'Heightened Def Con'
I simulate a system of two mutually delay-coupled electronic clocks (DPLLs - digital phase-locked loops). This worked well and also in reasonable time so far. However, moving into a particular regime ...
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Help to translate jitter design constraint in a frequency synthesizer design with 4046 and 4017 ICs
I'm trying to design a frequency synthesizer with the old-school 4046 and 4017 ICs, with a scaling factor N = 1,5,7,10.
The input signal is a square wave with adjustable frequency from 1 kHz to 10 ...
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How do I use a PLL to multiply the input frequency by an irrational number?
For integer multiples, I can use a frequency divider after the VCO to get a multiple of the input frequency. But how do I multiply the input frequency by an irrational number, say \$\sqrt2\$?
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Meaning of "three-stating" a PLL charge pump
I am designing a phase lock circuit using an Analog Devices ADF4107 PLL Frequency synthesizer (https://www.analog.com/en/products/adf4107.html).
The PLL is programmed manually and one of the settings ...
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Fast (high) frequency hopping with off-the-shelf components
I am looking for the easiest solution to
synthesize 1.6 - 2.4 GHz (qudrature)
in steps of 4 MHz
settle within 10-50ns
precise timing control when to switch frequency (e.g., at rising edge of an ...
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Gated clocks and clock enables in FPGA and ASICS
Please correct me if I am wrong. I have generally read that for FPGA's gating the master clock is a bad design practice and that one should use master clock & clock enable whenever circuit needs a ...
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FPGA - synchronise “very close” clock from signal
This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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Circuit for converting 48kHz to 12MHz
I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
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Converting the 400 picosecond pulse train to 15 MHz clock signal
My goal: I am trying to phase lock a 74HC-based digital circuit from a clock reference at 10~15MHz pulse repetition rate. The pulse width is around 400 picosecond. The peak voltage is sometimes below ...
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For this particular Ring oscillator topology, will the circuit prefer to latch up or oscillate?
This circuit is chosen from Razavi's textbook Design of CMOS Phase-Locked loops
In this circuit, where the outer inverters are weaker than the inner ones, does the circuit prefer to latch up or ...
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A capacitor as loop filter of a DLL
I know that if a second order, type two PLL has only a capacitor as its loop filter, it is unstable because its phase margin would be zero. but why is it ok for a DLL to only have a capacitor as its ...
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Adding cursors to analog oscilloscope
Background
I saw this video on youtube where this guy adds a marker to his analog oscilloscope by sending a pulse to the z axis input:
https://www.youtube.com/watch?v=QCFBBiIm1h0
I want to do the ...
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Is it possible to drive a HDMI output without exact clock frequencies (74.25 MHz, etc.)?
I'm driving a TFP410 parallel to DVI (HDMI) converter using a DM368. Unfortunately I can't generate the exact clock frequencies required for HDMI CEA modes (74.25 MHz, 148.5 Mhz, etc.), I'm stuck with ...
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What are the jitter characteristics of PLLs internal to Stratix V FPGAs?
I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
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In clock recovery, how is the recovered clock used to recover data?
I've been refreshing my memory on clock recovery, and I've hit some issues trying to understand how the recovered clock can be practically used to latch data bits from the input data stream.
For ...
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Displayport clock recovery
The displayport protocol runs at a fixed frequency of either 1.62GHz, 2.7GHz, or 5.4GHz. The pixel stream (strm_clk) it carries runs at an arbitrary frequency and is likely to be asynchronous to the ...
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Looking for 10GHz range clock generator
A bit of background: I'm doing some research with Doppler cooling and I need to design a new electronics package to tune a set of lasers to stimulate various two photon transitions.
At the moment, ...
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Servo amplifier for DC motors
I have an Harmonic drive and would like to design a PLL (phase-locked loop) controller for speed control of it. Here is a block diagram of a motor-speed control system based on PLL techniques:
My ...
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