Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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25
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3answers
21k views

What is the difference between a PLL and a DLL?

Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what ...
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4answers
9k views

PLL - why compare phases not frequencies

I have a question about PLL's. The aim of PLL is to get two signals with the same frequencies (there can be a shift in phases, as I understand). So, in this case, why do you use a phase detector to ...
15
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3answers
4k views

How can over 24 GHz communication be possible?

I read the article Google wants the US' wireless spectrum for balloon-based Internet. It says to use over 24 GHz frequency spectrum for communication. Is it ever possible to generate that high ...
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3answers
3k views

How do processors control their clock speed?

I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power. For something like a desktop processor where the clock ...
9
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5answers
9k views

What is the difference between first order, second order and third order phase locked loops?

What does PLL order represent? What are the disadvantages in order 1 & 2 PLL comprared to order 3? How to choose the pll type for an application like QPSK demodulator?
9
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2answers
991 views

Why do frequency synthesizers often use N/N+1 prescalers?

Frequency synthesizers, like Analog's ADF411x often have prescalers in their PLL which divide by 16/17, 32/33 or 64/65? What's the 2^N+1 value used for?
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2answers
1k views

All Digital Phase Lock Loop

I'm looking to implement a phase lock in an FPGA without using any external components (other than the ADC). For simplicity locking to a simple binary pulse is adequate. The frequency of the signals ...
8
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5answers
4k views

Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
8
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5answers
2k views

How do I drive 14.3Mhz clock input from 10MHz?

I intend to use an IC which requires 14.3MHz clock input, but want to drive it from a stable 10MHz source - derived from GPS. How do I turn the 10MHz clock into the 14.3MHz that the IC requires?
8
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1answer
10k views

How does a PLL inside a FPGA work?

I have used Altera FPGAs from last year and I would like to know how the PLLs inside works. Mainly, really have any kind of analog circuitry inside in order to measure phase-offset between VCO and ...
7
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7answers
1k views

3 Hz from a watch crystal

I have a stepper motor which step angle is 2 degrees. I want to display seconds using a needle attached to this stepper. The watch crystal divides nicely to produce 1Hz pulses, so every second I can ...
7
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2answers
989 views

Why microcontroller takes many clock cycles to start up with PLL clock source?

I was looking over the ATTiny85 datasheet and noticed on page 26 that with a PLL clock source, the fastest startup time is 14CK + 1K (1024) CK + 4 ms. Am I misinterpreting what they mean by 1K CK, or ...
7
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1answer
158 views

What is a Jaffe-Rechtin PLL?

Eberhardt Rechtin and Richard Jaffe (both involved in NASAs DSN) published this paper (paywalled) on PLL-design and -performance back in 1955. It is referenced quite often, so I wanted to understand ...
7
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1answer
582 views

pic32 maximum external frequency while running from internal 8MHz RC oscillator

I am completely new to PICs and I have never worked with a part as complex as this. In particular, I'm wondering if it is possible to generate a reference clock (REFCLKO in the datasheet) at 11.2896 ...
6
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3answers
5k views

Can I input a square wave LO into a mixer?

I would like to downconvert a signal at 169.55MHz (10khz bandwidth) into an IF of 20.4MHz. For that purpose, I need a local oscillator of 149.15MHz or 189.95MHz. But... of course, I cannot find a ...
6
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4answers
1k views

Reconstructing Clock for Serial Signal

Suppose that I have a serial signal (example below), which is transmitted without an accompanying clock signal, I would like find a circuit (using discrete components / ICs, possibly an FPGA, but not ...
6
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1answer
663 views

Creating a clock multiplier using a PLL

I understand that PLLs can be used to modify the phase of a clock signal for various purposes. I have also heard that PLLs are often used to multiply clocks. How can a PLL be used to multiply a ...
6
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1answer
1k views

Generate a 4.25 GHz using 50 MHz crystal/oscillator and PLL

I want to generate a 4.25 GHz using a PLL and 50 MHz crystal/oscillator. I am confused as to what I need to look for in a PLL. In a integer-N PLL, the prescalers are 16/17, 32/33, 64/65, etc. So, my ...
5
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2answers
932 views

MCU clock drift and radio frequency drift - are they the same?

Let's assume that I have two sensor nodes, one with crystal oscillator running at 24 MHz frequency, the other at 24 MHz + 10 ppm frequency. To my understanding, in system-on-chip (for example, Texas ...
5
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3answers
816 views

Phase locked Loop in Demodulation

Can someone please clarify how a PLL works and how it can the result is used to deduce phase? My understanding is that a PLL is used to demodulate in situations when the demodulator knows the carrier ...
5
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1answer
2k views

Pulse on edge of different clock

I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK). Now I need a pulse each time a rising edge of the original clock ...
5
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5answers
962 views

PLL usage in DIY hobby project [closed]

I was wondering if anybody was using PLL (Phase Locked Loop) in DIY hobby project? If yes what was the application? Did you made it from discrete components (as opposed from one placed in uController ...
5
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2answers
873 views

Linearized phase domain model of a PLL - what does a ratio of input phase over output phase mean?

I am trying to design a PLL and want to test it first in Matlab. I have seen that the phase of the input and output are linearized, but I don't understand what is defined by the input/output phase. ...
5
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1answer
115 views

Why should crystal switching be avoided?

The MC44144 is a gated phase locked loop intended for video applications that is described in its datasheet as "sensitive to shunt capacitance" and that "crystal switching should be avoided". What ...
5
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2answers
326 views

Injection locked frequency dividers

I am beginning to design a monolithic frequency synthesizer (around 2.4GHz) in which I need the maximum of spectral purity. I was looking at injection locked frequency dividers (ILFDs) for use as a ...
5
votes
1answer
235 views

Help to translate jitter design constraint in a frequency synthesizer design with 4046 and 4017 ICs

I'm trying to design a frequency synthesizer with the old-school 4046 and 4017 ICs, with a scaling factor N = 1,5,7,10. The input signal is a square wave with adjustable frequency from 1 kHz to 10 ...
4
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2answers
654 views

How do I use a PLL to multiply the input frequency by an irrational number?

For integer multiples, I can use a frequency divider after the VCO to get a multiple of the input frequency. But how do I multiply the input frequency by an irrational number, say \$\sqrt2\$?
4
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1answer
704 views

Can I program a platform independent PLL in VHDL?

Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom ...
4
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1answer
128 views

A capacitor as loop filter of a DLL

I know that if a second order, type two PLL has only a capacitor as its loop filter, it is unstable because its phase margin would be zero. but why is it ok for a DLL to only have a capacitor as its ...
4
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3answers
343 views

Adding cursors to analog oscilloscope

Background I saw this video on youtube where this guy adds a marker to his analog oscilloscope by sending a pulse to the z axis input: https://www.youtube.com/watch?v=QCFBBiIm1h0 I want to do the ...
4
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1answer
377 views

Is it possible to drive a HDMI output without exact clock frequencies (74.25 MHz, etc.)?

I'm driving a TFP410 parallel to DVI (HDMI) converter using a DM368. Unfortunately I can't generate the exact clock frequencies required for HDMI CEA modes (74.25 MHz, 148.5 Mhz, etc.), I'm stuck with ...
4
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1answer
3k views

Understanding requirements for USB 2.0 high-speed

I am little bit confused about the requirements of USB 2.0 high-speed. USB 2.0. high-speed maximum transfer rate is 480 Mbit/s. So from my understanding to fully utilize this data rate one should ...
4
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1answer
470 views

What are the jitter characteristics of PLLs internal to Stratix V FPGAs?

I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
4
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4answers
396 views

In clock recovery, how is the recovered clock used to recover data?

I've been refreshing my memory on clock recovery, and I've hit some issues trying to understand how the recovered clock can be practically used to latch data bits from the input data stream. For ...
4
votes
1answer
471 views

Looking for 10GHz range clock generator

A bit of background: I'm doing some research with Doppler cooling and I need to design a new electronics package to tune a set of lasers to stimulate various two photon transitions. At the moment, ...
4
votes
1answer
5k views

Servo amplifier for DC motors

I have an Harmonic drive and would like to design a PLL (phase-locked loop) controller for speed control of it. Here is a block diagram of a motor-speed control system based on PLL techniques: My ...
3
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2answers
13k views

What is (phase lock loop)PLL?, Lock Range & Capture Range?

The explanation of a PLL is here, for a PLL, what is the meaning of the following terms? Capture Range ? Lock Range ? What is it about the PLL circuit that might have these two terms span a ...
3
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2answers
18k views

PLL loop bandwidth, lock time and jitter

For a PLL in short, 1) What controls loop bandwidth? 2) What impact does it have on output phase noise/jitter? 3) What impact does loop bandwidth have on PLL lock time? I am trying to find answers ...
3
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3answers
198 views

Circuit for converting 48kHz to 12MHz

I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
3
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3answers
353 views

PLL versus putt-putt-skip, putt-putt-wait, fractional-rate division, or other approaches

Many applications use PLL's to generate frequencies where long-term frequency accuracy is necessary, but where a certain amount of short-term jitter might be acceptable. I've seen a number of devices ...
3
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2answers
337 views

What does the input to output ratio for a PLL chip mean?

For PLL chips, digikey notes the "Ratio - Input:Output". For example, here are two 74HCT4046 ICs: This TI chip has a "Ratio - Input:Output" of "1:4" This NXP chip has a "Ratio - Input:Output" of "2:3"...
3
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1answer
352 views

Possible to tap a PLL signal as a clock for multiple devices

We have an oscillator providing a clock signal for an MCU. It has oscillator in and out pins: XTAL-IN and XTAL-OUT. We'd like to use the same clock signal as a digital clock input to another MCU. ...
3
votes
1answer
530 views

Change in PLL settling time as a result of halving charge pump current/doubling loop filter capacitor

I have a PLL that is operating unstably at some temperatures. I have been able to show that reducing the charge pump current from 128uA to 64uA ensures that the PLL will operate stably at the same ...
3
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3answers
1k views

Phase-locking pixel clock to HSYNC/VSYNC

I am trying to capture pixel data going to a small B&W CRT display. The signals I have to work with are the TTL-level pixel data signal, HSYNC, and VSYNC. I know the pixel clock frequency (~16 MHz)...
3
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2answers
128 views

How do I differentiate two distinct frequencies? 24Mhz and 40Mhz

I have these two frequencies fed to the input of the PLL and need to vary the B.W according to the frequency. But before that, how do I differentiate between these two frequencies?
3
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1answer
52 views

PID: how to deal with delay between controller and a process?

In designing a digital pll, I'm facing a problema with a communication delay between the loop filter output and the frequency synthesizer (via SPI). If I dont consider the communication delay the ...
3
votes
1answer
859 views

LTSpice simulation stalls after 100ms transient with 'Heightened Def Con'

I simulate a system of two mutually delay-coupled electronic clocks (DPLLs - digital phase-locked loops). This worked well and also in reasonable time so far. However, moving into a particular regime ...
3
votes
1answer
641 views

Displayport clock recovery

The displayport protocol runs at a fixed frequency of either 1.62GHz, 2.7GHz, or 5.4GHz. The pixel stream (strm_clk) it carries runs at an arbitrary frequency and is likely to be asynchronous to the ...
3
votes
1answer
349 views

HSPLL mode freezes 18F46K20 micro controller

COMPILER: XC8 v 1.30 micro: PIC18F46K20 I use this in CONFIG1H register to get 64MHz Fosc (and use PLL): ...
3
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2answers
214 views

Can I safely operate a PLL below it's “minimum” RF frequency?

I was wondering if anyone has had luck operating a PLL below the spec'd minimum RF frequency. For example, Analog's ADF4107 PLL specs 1-7GHz RF input frequency, but I don't immediately see why it can ...

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