# Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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### How to generate a sine wave that is in phase with a generated square wave at 1MHz for lock-in amplifier?

I am building a lock in amplifier (LIA) for fluorescence lifetime measurement using off the shelf components, after going through literature, I have decided to use square wave for excitation of the ...
1 vote
66 views

### STM32F407 PLL config not producing 1ms SysTick

I've a bare metal PLL setup for my STM32F407 which should generate a 168MHz system clock. However for some reason the 1ms SysTick interrupt is orders of magnitude off the grid. The math works out on ...
98 views

### Phase lock loop frequency of reference signal

I am writing code for a phase locked loop in MATLAB. Up to now, I assumed that the frequency of the input signal is given (known) and I choose the frequency of my VCO close or exactly the same as the ...
114 views

I am working on a PLL design. I am at the research stage now. I am confused about the PLL input frequency range. This frequency has to remain constant. If this input frequency stays constant, how can ...
85 views

### What Exactly Is Meant by a 2nd Order Phase Locked Loop?

I'm teaching myself about polyphase clock sync for demodulation of OQPSK. An article from gnuradio.org entitled "Polyphase Clock Sync" makes references to a 2nd order loop. The context seems ...
1 vote
68 views

### Creating a large number of crystal-stabilized pulse waves at precise frequencies

I intend to generate 22 separate 50% duty cycle pulse or square waves. The frequencies range from about 5 Hz to 350000 Hz and are all irrational numbers, so I would like as much precision as possible. ...
197 views

### How does this phase advance loop filter work?

I am reading this paper titled A Versatile Digital GHz Phase Lock for External Cavity Diode Lasers. This is part of the circuit. I am confused about the functionality of the part labeled "Phase ...
1 vote
596 views

### PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
325 views

### PLL multiplier input output phase

I need to pass a 100MHz continous clock between an MCU and FPGA. The clock edges are aligned to various interface signals between both devices. I wonder if I can pass a submultiple of the clock like ...
440 views

### Costas Loop QPSK/4QAM

I can use a Costas Loop, modified for QPSK/4QAM and recover the frequency and phase successfully when using a pattern of all 1s or all 0s or a pattern that is repetitive for each I and Q data rail (in ...
209 views

### Differences between phase locked loop on PCB and on breadboard

I have a question with regard to the differences between a PLL on a PCB and on a breadboard. In this test, I have connected the output of the amplifier (LMH6503) to both the PLL on the PCB and the PLL ...
19 views

### finding PID coefficient for my PLL system

I have a feedback loop as shown below,We are fixing the noisy YIG with a cavity resonator and feedback.(shown in the attached paper and diagram below). the phase difference between the signal is ...
40 views

### Are two FPLLs in sync?

Two FPLLs are being driven by a common clock and the output of each FPLL is used to drive a counter after achieving a lock. When we turn on the circuit both FPLLs miraculously lock EXACTLY at the same ...
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### Debugging PLL STW81200TR not locking

I need a bit of debugging help with SWT81200 PLL that I am using on my custom designed PCB. I am able to configure registers through SPI communication, but the problem is that I am not able to achieve ...
1 vote
71 views

### Type 2 comparator locking on ringing

I have successfully designed a 4046 IC with a phase 2 comparator locking to an external 10 MHz VCOCXO. The circuit is simple vcoxco----> divide by 10--> Schmitt Trigger --> divide by 10 -->...
223 views

### How to generate correct frequency in DDS using stm32?

I had asked a question a week ago regarding DDS on STM32 and I got some good answers. Based on that I tried to write a code to implement DDS on stm32. In my project I need to generate a 10 KHz sine ...
459 views

### How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
185 views

### Driving high impedance load with Crystek Sine Wave Oscillator- CCSS-945X-25-100.000

I am planning to use Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 . Now in datasheet of oscillator, output power mentioned is 5dBm into 50 ...
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### Can't find transistor-based PLL circuit example

I am learning electronics as a hobby. My current interest is phase locked loops (PLL.) I was able to find a lot of block diagrams with explanations of how PLLs work and also CD4046 based PLL ...
1 vote
763 views

### How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
89 views

### What is the maximum PLL output frequency in the STM32H7A3?

I'm setting up a hyperram, and I want to run it at 200MHz, with the DHQC setting enabled. The peripheral manual on page 874 says: DHQC must not be set when the prescaler value is 0, as this action ...
67 views

### Designing loop filter for frequency-modulated PLL

I'm designing a PLL circuit to stabilize a ~200MHz VCO against temperature-induced frequency drift. However, I need to be able to occasionally (~few times/sec) send a short pulse (~few μs) to modulate ...
227 views

### Simulation of PLL

I am simulating a PLL with a reference frequency of 25 MHz, VCO freq of 450 MHz. I want to plot the gain versus frequency offset of the closed loop PLL in cadence. How should I give the inputs to get ...
88 views

### How to synthetize a 10 kHz signal from 1 Hz analogically

I would like to synthesize a 1 Hz signal to a 10 kHz one without using MCU or related DPLLs. Anyone has a schematic example? I found this reference schematic on Art of Electronics. Would that suit (...
22 views

### How to find the direction of phase difference of sine signals using multiplier phase detector?

I am using a multiplier phase detector like here 1to find the phase difference between two phase shifted sine signals, and I got the value of magnitude but how to find if the signal 2 is leading/...
341 views

### Using MMCM/PLL source clock pin elsewhere in design breaks timing

TL;DR: New to Vivado Clocking Wizard, using the clock pin from the FPGA for anything other than the input to MMCM/PLL IP fails timing. I'm working with Vivado ML 2022 in VHDL targeting an Artix-7 FPGA ...
65 views

### Best way to close GPSDO PLL digital loop?

I am trying to build a GPSDO with a holdover capability of 500us/24hs (maximum drift accumulated). The system uses a 10MHz OCXO and it is my intention to use a microcontroller (ATMega, STM or ...
25 views

### Calculating AC-Coupled input current

I'm using an SDR which uses and ADF4002-based PLL with its REFIN input AC-coupled via a 0.1 uF capacitor to an external input. I'd like to connect an external reference clock to it, but I'm unsure how ...
1 vote
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I designed and tested a PCB with a PLL circuit. The goal is to lock on the reference signal which is a square wave. The problem I am having is that the signal of the N-counter shows no response, just ...
1k views

### Converting the 400 picosecond pulse train to 15 MHz clock signal

My goal: I am trying to phase lock a 74HC-based digital circuit from a clock reference at 10~15MHz pulse repetition rate. The pulse width is around 400 picosecond. The peak voltage is sometimes below ...
238 views

### Problems Comparator II of this CD4046 for LTspice

I downloaded a CD4046B model from user ale_t, which can be found here: https://www.electro-tech-online.com/threads/new-spice-model-for-cd4046b-phase-locked-loop-ic.149093/ However, the Phase ...
269 views

### Clock crystal oscillator and PLL accuracy

If I use an 8 MHz oscillator with accuracy of 25 ppm and the PLL multiplies it to 32 MHz, then the accuracy is also multiplied (x4 = 100 ppm) or is it not? Thanx.
264 views

### Frequency multiplication with PLL circuit

I am currently working on frequency multiplication with a PLL circuit. I want to give it an input frequency of 10 kHz to 100 kHz and I want to get 160 kHz to 1.6 MHz from the VCO output. That's a ...
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### Thermal shutdown in HMC510, HMC507 and ADF4159

We have following chip combination cards:- ADF4159CCPZ-RL7 and HMC507LP5ETR ADF4159CCPZ-RL7 and HMC510LP5E We have both PLL and VCO are on a single board. We are using same board for above combination....
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### How to get freq stability with constant offset for PLL synthesizer?

I used ADF5356 PLL synthesizer. And i use reference oscillator freq is 10MHz with initially offset 0.1ppm and stability is 10 ppb. I need to output freq is 3750 MHz. Expected output result: 10MHz × 0....
432 views

### Implementing direct digital synthesis in STM32 microcontroller

I am working on a project that requires phase locking (digitally) of an output signal from a sensor to the reference signal which needs to be done on STM32 microcontroller. I am new to this area, and ...
589 views

### Meaning of "three-stating" a PLL charge pump

I am designing a phase lock circuit using an Analog Devices ADF4107 PLL Frequency synthesizer (https://www.analog.com/en/products/adf4107.html). The PLL is programmed manually and one of the settings ...
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We have designed a PLL for an operating range of 11-14 GHz. The output of the VCO goes directly to the amplifier, and then to a divider, see the picture. Is there anything that affects PLL locking ...
137 views

### Reliability issue of HMC833 PLL

We are using an HMC833LP6GE PLL in our design for generating 122.88 MHz from a reference of 100 MHz. We are feeding a reference signal of >5 dBm. What we are observing is that out of 10 times, if ...
1 vote
337 views

### What does this symbol of a PNP BJT transistor with extra connections to the base and collector represent?

I am trying to understand the internal circuit schematic of the LM565 phase locked loop IC, on page 6 of this datasheet: PDF Datasheet for LM565 from TI website In the upper middle, there is a strange ...
1 vote
636 views

### Matlab digital phase locked loop script

I am trying to extract carrier signal from amplitude modulated signal. The amplitude modulated signal is stored in a CSV file. I tried to calculate calculate carrier frequency by calculating the zero ...
252 views

### PLL minimum frequency: how much tolerance?

Many FPGAs have phase-locked loops which can multiply the frequency of a clock. The signal path of a PLL is rather simple: ...
1 vote
151 views

### Selecting optimal phase locked loop (PLL) frequency for microcontroller peripherals

Typically microcontrollers use an input clock source with a certain frequency. This clock source is then divided and multiplied to a PLL frequency which is much higher. Finally, the PLL frequency is ...
53 views

### How did he calculate the error in this example?

He found an error of about 18%. What is the error formula used in this example? From section 1.5.1 of the book Design of PLLs by Behzad Razav.
1 vote
166 views

### CD74HC4046 PLL slipping with off-air reference frequency

I am trying to use the Radio 4 198kHz carrier frequency to discipline a PLL, in order to generate a pulse-per-second (PPS) output that is stable over several hours. The issue I am facing is that the ...
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### Designing circuit of clock recovery from data line [duplicate]

I am currently struggling with the following challenge. In the system I am currently designing, the transmitting device is equipped with an image sensor with MIPI output (1 data line, 12 Mbit data ...
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### Oscillator with low frequency drift

I need a ~70MHz oscillator with low frequency drift (less than 1%) over a wide temperature range (10°C to 50°C). I dont have any experience with oscillators, so I have no idea which type of oscillator ...
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### ATTiny861A fast PWM mode not working

For a couple of hours, I struggle to find the source of my PWM output to not generate a PWM signal. I changed register values to explicitly show their contents - I hope it will make the diagnostics ...
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