Questions tagged [pll]
PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.
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Reconstructing Clock for Serial Signal
Suppose that I have a serial signal (example below), which is transmitted without an accompanying clock signal, I would like find a circuit (using discrete components / ICs, possibly an FPGA, but not ...
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What is the difference between a PLL and a DLL?
Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what ...
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How can over 24 GHz communication be possible?
I read the article Google wants the US' wireless spectrum for balloon-based Internet. It says to use over 24 GHz frequency spectrum for communication.
Is it ever possible to generate that high ...
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All Digital Phase Lock Loop
I'm looking to implement a phase lock in an FPGA without using any external components (other than the ADC). For simplicity locking to a simple binary pulse is adequate. The frequency of the signals ...
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Low pass filter target frequency for a mixed signal frequency synthesizer
I'm building a frequency synthesized local oscillator with coarse and fine tuning to span 30.5 to 32MHz. The design follows the following block diagram (bits not essential to this question removed ...
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What is the purpose of PLL in a general microcontroller
An ARM Cortex-M4 based microcontroller like TM4C123GH6PM is designed with multiple clock sources with a processor core clocked at 80MHz provided by the PLL, which, from what've read in NI-What is a ...
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What is the difference between first order, second order and third order phase locked loops?
What does PLL order represent?
What are the disadvantages in order 1 & 2 PLL comprared to order 3?
How to choose the pll type for an application like QPSK demodulator?
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Generate a 4.25 GHz using 50 MHz crystal/oscillator and PLL
I want to generate a 4.25 GHz using a PLL and 50 MHz crystal/oscillator.
I am confused as to what I need to look for in a PLL. In a integer-N PLL, the prescalers are 16/17, 32/33, 64/65, etc. So, my ...
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Can I input a square wave LO into a mixer?
I would like to downconvert a signal at 169.55MHz (10khz bandwidth) into an IF of 20.4MHz.
For that purpose, I need a local oscillator of 149.15MHz or 189.95MHz.
But... of course, I cannot find a ...
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Pulse on edge of different clock
I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK).
Now I need a pulse each time a rising edge of the original clock ...
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Circuit for converting 48kHz to 12MHz
I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
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How do I differentiate two distinct frequencies? 24Mhz and 40Mhz
I have these two frequencies fed to the input of the PLL and need to vary the B.W according to the frequency. But before that, how do I differentiate between these two frequencies?
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orthogonal singal generator
I am working on a single phase PLL (phase locked loop) and I would like to make a phase shift by using orthogonal signal generator non frequency dependent.
I have found many method like transport ...
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will two plls wander with shared reference clock
I'm trying to learn about pll wander or drift. My reading leads me to believe one of the reasons plls were developed was to fight wander so maybe it does not affect plls? Although I've seen some ...
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Working out the Transfer Function of a PLL Loop given by the Analog Devices ADISim Tool
This is a followup question to this question, I asked previously. My synthesizer PLL still isn't locking and it must be the introduction of the mixer and filter into the loop that's causing the issue ...
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How to get a high precision sine wave not available from standard crystal?
I am considering for a RFID transmitter, which just send power with no data. However, my frequency is not standard 13.56MHz not 27.12MHz, it is 27.095MHz. Can I use the block diagram shown above? If ...
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Issue for TCXO through frequency multiplier (PLL) for STM32 I2S signal
I try to use TCXO (KT7050A24576KAW33TAD) at 24.576 MHz through frequency multiplier (PLL) x4 (NB3N511DG) to clock the I2S bus (SAI domain) at 98.304 MHz on a MCU (STM32L4R5VIT6). Signals are not what ...
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Accommodating Gain Elements in PLL Loop
Background
I'm working on a PLL based frequency synthesizer for the 20m amateur radio band. For reference, I've asked questions in relation to this project before (see here). It uses the idea of an ...
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PIC24 PLL module is always out of lock
I have been working on a PIC24FJ128GA310 development board for for some time now and recently got a PCB made. If I try to move my code into the new board all timing related math and functions are ...
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Whats the principle of a PLL used as demodulator of a FM signal?
I didnt quite understand te following:
A basic PLL consists of the following parts:
phase detector
low pass filter
VCO
If you input a 1MHz sine the PLL will try to lock on it by controlling the VCO....
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External clock oscillator and MCU
I am creating this post as a second part to a recent post I have made: STM32F446 & External Oscillator
I have read other post about using a crystal that runs at 8 MHz rather than 25 MHz. Such as ...
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Delta Sigma Modulator for 2/3 Multi modulus divider used in FracN PLL
I have been trying to implement a Delta Sigma modulator for a 2/3 Multi Modulus divider. I am referring to Riley's paper: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=229400
I have designed ...
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Add a Tunable delay to a TTL pulse?
How can you add a tunable delay to a TTL pulse?
My understanding is that this is the job of a PPL. I am not sure if a digital PLL delays a square wave or if it can also delay a single rising edge (...
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PLL and VCO example of a reference tone's frequency muliplied by 12000 to generate a master clock
A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency.
The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 ...
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DDS example of a reference tone's frequency muliplied by 12000 to generate a master clock
A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency.
The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 ...
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Driving high impedance load with Crystek Sine Wave Oscillator- CCSS-945X-25-100.000
I am planning to use Crystek CCSS-945X-25-100.000 sine wave oscillator to drive the reference CLKin pins of TI PLL IC LMK04832 .
Now in datasheet of oscillator, output power mentioned is 5dBm into 50 ...
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Confusion: Lock range of PLL
Suppose we have a type-I PLL whose block diagram is shown below:
Here \$k_{pd}\$ is the average gain of the phase detector producing the control voltage \$V_c\$ which is input to the Voltage ...
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Creating a digital PLL
I want to drive a quartz crystal resonator at its resonant frequency so I need to stay locked on to its resonant frequency as its resonant frequency changes. I'm using an FPGA to do this.
I want to ...