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Questions tagged [pmos]

A p-channel metal-oxide semiconductor (pMOS) transistor which has has p-type carriers used in the channel. The channel is established by a negative voltage on the gate which inverts the substrate (NWell) under the gate which turns the device on. The term may also be used to describe logic circuits ...

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19 views

NMOS/PMOS Transit Frequency

I found this video which shows how to plot the transit frequency in Cadence Virtuoso. But on another site, instead of using c_gg, the capacitance used was c_gs+c_gd for the ft equation. Which is ...
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2answers
46 views

Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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1answer
29 views

Inversion Region

If one transistor in a circuit (say common source with active load) operate at the strong inversion region, should the rest of the transistor also operate on that same region? Or will it depend?
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1k views

Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: i/p o/p 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please explain in simple terms as I am a beginner in this topic ...
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1answer
24 views

Advantages/Disadvantages of high/low transconductance efficiency (gm/Id) of NMOS/PMOS

From here, it's said that a higher gm/Id results in lower current consumption (which is usually preferred in low power operation) But what other effects does a high gm/Id have? Will it have other ...
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21 views

Clarifications on Intrinsic Gain

I found this here while searching for questions regarding intrinsic gain but I'm still quite confused and the links given were dead. My questions are: Is intrinsic gain the maximum gain of a ...
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1answer
31 views

NMOS/PMOS Saturation

If I recall correctly, saturation occurs if \$V_{GS}>V_{TH}\$ and \$V_{DS}>V_{Dsat}\$ for NMOS. But is there an upper limit for the voltage? Like, when does a transistor not saturate after ...
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2answers
60 views

Understanding Vgs absolute value

If a P-channel MOSFET have absolute maximum values: VDSS = -60 V Vgs = +/-20 V "refering to high switch side": Does this means we cannot switch the MOSFET by the gate driver that ties the gate to ...
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92 views

Resistor or no resistor between this IC and the pmos GATE?

I'm using this IC (https://www2.mouser.com/datasheet/2/609/ADM1270-878589.pdf). This IC controls the GATE of a pmos. I'm thinking about using this MOSFET (https://www2.mouser.com/datasheet/2/389/...
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3answers
115 views

How long do I have before my sensitive components get fried?

I'm using this IC (https://www2.mouser.com/datasheet/2/609/ADM1270-878589.pdf) to control the current and the voltage on some of the outputs of a PCB that controls the power to other PCBs, which have ...
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1answer
38 views

What would happen if there is no ground in a PMOS inverter?

I understand why when there is a ground you need a resistor or an NMOS but what if there were no ground at all and simply A goes high, B is 0, A goes low, current flows from VDD to B through the p ...
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40 views

How to improve this circuit to open / close 24V power rail?

I have thought to use the following circuit to control the power of a subcircuit. The control is done through a GPIO pin of a microcontroller (ATMEGA328P). I would like to know if you see any serious ...
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1answer
133 views

Small signal equivalent circuit - MOSFET

Let's consider the following amplifier circuit: Now, if we would analyze small signal operation, we could represent the circuit with small signal equivalent: The part that bothers me is the PMOS ...
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2answers
69 views

P MOSFET turning on before gate threshold

I was simulating a P MOSFET, and for turning a P MOSFET on we need gate to Source voltage less then its threshold voltage. as per below simulation circuit at start VGS= 0, then there is no way mosfet ...
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1answer
119 views

Why are my p-channel mosfets cutting off in LTSpice even though Vgs is negative?

I'm running into a weird bug. Part of me thinks that it's LTSpice that's wrong, but that seems unlikely. I'm working on the circuit below, to be able to switch between feeding my voltage regulator ...
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1answer
71 views

Strange behaviour of ne555 + pmosfet circuit

I was a silent reader for a long time and could solve all the problems on my own, but this problem is really freaking me out. I was messing around until 3 AM today with this "feature" and still don't ...
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2answers
127 views

Slew Rate Adjustability

A SPST switch connects HB1 and HB2, to control a lamp connected to HB OUT. I am looking into modifying this circuit to make the slew rate adjustable when switching the output to VCC (around 12V). I ...
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1answer
92 views

Using LTSpice to find the gain of NPN-PMOS folded cascode

I am trying to use LTSpice to find the gain of NPN-PMOS folded cascode. Below is the question prompt: In the problem, the parameter specifications are as follows: \begin{equation} \beta =100,\:V_A=5V\...
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1answer
64 views

Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached
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2answers
59 views

How to amplify the output of an on NMOS, connected to zero source voltage?

I am simulating a 3 transistor based XNOR cell using HSPICE. The circuit is shown in the picture. technology = 45nm Vdd=1.1v |Vth|=0.62v In the case of A=1 and B=1, the output is charged through ...
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1answer
101 views

Driving a 35V PMOS circuit from a Grounded/Floating input

I have an application where I need to switch a contactor on and off using a spare output of an off the shelf Battery Management System (BMS) The input is the signal coming from the BMS, while the ...
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5answers
603 views

Simple Mosfet driver

I need to switch 8 IRF9540 (P-Channel Mosfets) with about 32kHz (so 1 MOSFET about 4kHz) so that only one is On at one time. I thought about using the decade counter 4017 for this, and the 555 Timer ...
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1answer
31 views

Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
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1answer
79 views

Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?

Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs. For example, could not we just put the green construction in the place of red ...
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4answers
235 views

What is the use of pull-down networks in CMOS gates?

Below you can see the basic CMOS inverter. What I don't understand about this particular design is the purpose of the n-channel mosfet which is the part referred as pull-down network. What if we ...
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1answer
462 views

Diode-connected PMOS

Im currently a year 1 electrical engineering student. May I ask, for a diode-connected PMOS (gate connected to drain), why is |Vsd| = |Vgd| ?
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35 views

half-bridge p-channel pwm

I need half-bridge that works 10% up to 100% (continuous), so I thought some driver for P-channel and N-chanel mosfet, equivalent to FAN3268. The FAN3268 is hard to find and expensive. Is there any ...
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2answers
57 views

How did we find Vin in this CMOS?

Why did the lecturer decided that Vin is vGSn - vGSp + vDD , Why did he not go through the drain path and used vGDn and vGDp ?
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1answer
25 views

Find p-MOS frow battery switch application

I'm designing a switching circuit between USB (5V) and Battery (li-ion 3.7V) for a portable device, below is shown the schematic: As you can see if correctly chosen the P-MOS switches between USB ...
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2answers
51 views

Why is vo = 0 when VI(gate voltage) = 0. Also why is are both mosfets operating in the saturation region . Could someone explain why this is so?

According to the book Vo =0 when VI(gate-voltage) = 0. Why is that so? Why does the book also assume that both mosfets are operating in the saturation region? when VI = 0. I appreciate the help. ...
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1answer
63 views

Getting brownouts when using MCU controlled P-FET to switch power to another board

I have an MCU connected to a logic level P-FET(part no AO3401A). The source is wired to a 3.3V regulator that also feeds the MCU. The drain is wired to an LED and a header that connects to a second ...
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2answers
55 views

How to redesign the circuit such that the switching threshold is VDD/2.

he switching threshold is the input voltage where the output crosses VDD/2. I want to redesign the circuit such that the witching threshold is VDD/2.
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1answer
71 views

Having trouble understanding CMOS and PMOS circuits [closed]

I'm in a digital logic class and I've got a solid grasp on Boolean algebra, SOP, POS, NAND, NOR gates, etc. Now I'm having trouble in understanding what NMOS, PMOS and CMOS transistors are and how ...
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2answers
542 views

Problems with DC analysis of a PMOS circuit

I'm beginning with electronics and I've picked up the book from Donald. A. Neamen - Microelectronics. I'm stuck at a simple example of DC analysis for this PMOS circuit. simulate this circuit – ...
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1answer
805 views

Pull up resistor on P-MOSFET gate. Not working

I am building a battery-powered datalogger that will communicate using cellular signal, based on the ATSAMD21 microcontroller and the SIM5320 cellular modem. To save power, an outside timer ...
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1answer
122 views

Li-ion power supply with a charger, a booster, and a pMOS high side switch

I am designing a circuit board for a small mobile robot and there is a problem with the power supply. The circuit is powered by a 1-cell Li-ion battery (VBAT) and includes a charger (MCP73831/2), a ...
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64 views

Soft latch on/off button simulation

I am trying to simulated in pspice a soft latch on/off circuit but it is not working as expected, even if I double check the implementation. Can someone explain to me why the voltage on the probe is 0....
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0answers
76 views

How to size the precharge circuitry of sram

I am trying to design a sram module on layout. I have designed and tested the sram bit cell and was looking at designing the remaining circuitry such as the precharge, row decoders, write drivers and ...
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2answers
151 views

Level shifted PMOS driver operation

simulate this circuit – Schematic created using CircuitLab Having some confusion this gate driver. It can be found in Design and Application Guide For High Speed MOSFET Gate Drive Circuits. ...
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1answer
304 views

Increasing gain of PMOS two-stage op-amp

I am trying to increase the gain of a two-stage PMOS op-amp I have designed below shown in this schematics: The gain currently hovers slightly below 71dB, but I have to increase it to above 75dB. I ...
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2answers
53 views

Filtering Voltage Spikes on Split Power Cable

I have a test set up that can more or less be broken down like below: simulate this circuit – Schematic created using CircuitLab The splitter shown is custom made for testing, here is a drawing:...
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1answer
163 views

current value of two serial transistors

How can i prove that the current value (Ids) of two serial transistors (nmos) with equivalent W/L values is equal to the current value of one transistor with W/2L (In linear region)? (Ids1 = Ids2 in ...
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2answers
190 views

P channel mosfet as a switch different setups for USB and battery switching

Recently I came across the below 2 examples of using a p-mosfet as a switch. Running a simulation leads to the following observations. Circuit 1 Reference 1 OUTPUT is 4.951 Circuit 2 Used this ...
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1answer
485 views

Switching High-voltages with p-channel MOSFET

I want to use a MOSFET to switch 400V to a circuit. I can switch low-side using an n-channel MOSFET, but it's more convenient to have the circuit with its ground fixed. So I want to switch high-side, ...
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1answer
43 views

Looking for the logical equation from this PMOS circuit

I am looking for the logical equation that describes the given circuit below. Unfortunately I don't have information whether \$U_b\$ is positive or negative - would that make a difference? I derived ...
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1answer
215 views

What is the best between a transistor and a pmos and which resistances

I need to create a switch to power on or off a moisture sensor. PIN 10 is HIGH or LOW to trigger either the transistor or the PMOS My sensor consume about 0.6mA Moisture sensor information My ...
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2answers
45 views

PMOS Falling Time

I have established a circuit which has a -7V,+7V 16kHz square wave and my aim is obtaining 0V,+1V 16kHz square wave output signal. To do this, i have used a TI SN75189ADR and DMP4051LK3-13 pmos as i ...
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2answers
391 views

Determination of region of operation for pmos

Given the value of Vgs, Vds and Id for a pmos, how to determine the mode of operation and its Vt
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3answers
331 views

Control inrush current

A basic question, how does the P-Mosfet reduce the inrush current. simulate this circuit – Schematic created using CircuitLab Old image link Can the P-Mosfet's drain and source orientation be ...
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1answer
176 views

PMOS Circuit Problem

The problem statement, all variables and given/known data Relevant equations •Id=K*(Vsg-Vth)2 •KVL The attempt at a solution On part A, Haven't had much experience with PMOS. Used large signal model, ...