Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [pmos]

A p-channel metal-oxide semiconductor (pMOS) transistor which has has p-type carriers used in the channel. The channel is established by a negative voltage on the gate which inverts the substrate (NWell) under the gate which turns the device on. The term may also be used to describe logic circuits built around pMOS transistors.

0
votes
0answers
22 views

Output voltage for pmos with Vt= -0.8

simulate this circuit – Schematic created using CircuitLab What is VX? I am having confusion between 2.8 V or 3 V. Thank you for your help.
0
votes
2answers
55 views

Op amp with pmos

simulate this circuit – Schematic created using CircuitLab What is the gain (Vout/Vin) for the schematic?
0
votes
0answers
17 views

Mixing Reverse Polarity Protection PMOS with a Piezo Element

I have a circuit that powers some leds when vibrations are detected. I am trying to integrate a PMOS for reverse polarity battery protection. When the PMOS is present the circuit simulation fails as ...
1
vote
0answers
24 views

PMOS Drain-Source Short at Turn-On

In the attached image, without C1 & C2 (used only as de-cap) mounted, when 24V is given at TP1 and nMOS (Q1) is turned ON, the circuit works fine and I get 24 V at TP3. But when C1 & C2 are ...
1
vote
1answer
41 views

Calculating resistors for an optocoupler controlling a pmos

I want to use a pmos (SI7157DP-T1-GE3, datasheet) as switch - controlled by an optocoupler (TLP291(V4GBTP,SE, datasheet) which is controlled by a teensy 3.6 (3V3 output voltage). Now I'm calculating ...
0
votes
0answers
44 views

Design Vbat system with PMOS to keep RTC

Since I'm using an MCU without internal Vbat system (STM32L0 series), I've read the "How to design a Vbat on STM32L0/L1 series" from STMicroelectronics to keep the internal RTC. I would like to ...
0
votes
0answers
34 views

CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
0
votes
0answers
26 views

LTSPICE Model Parameters of P-MOSFET

I am trying to simulate a circuit including TSM500P02CX P-MOSFET. The manufacturer of the MOSFET doesn't provide SPICE Model, so ...
-1
votes
3answers
48 views

Reverse Current Protection using two PMOS in back to back configuration

I am working on a circuit that needs reverse current protection. Back to back mosfet configuration has been suggested by many people, and it seems to make sense at the beginning. But after I built my ...
0
votes
2answers
67 views

How to calculate the maximal temperature of a transistor

let's assume I have this transistor (IRFR640): https://www.infineon.com/dgdl/Infineon-IRFR6215-DS-v01_02-EN.pdf?fileId=5546d462533600a40153563595592114 $$R_{DS(ON)} =0,295 \Omega $$ $$V_{max} = -150V$...
0
votes
2answers
103 views

TSMC model for lt spice simulation [closed]

From where to download the tsmc model file for nmos(slow,fast,typical) and pmos (slow,fast,typical)?
0
votes
1answer
53 views

Difference between body, bulk and substrate?

I have a pretty fundamental question related MOSFET devices. I am confused about whether the terms body, bulk and substrate are all just names for the same thing or are there actually some differences ...
0
votes
1answer
46 views

LTSpice - PMOS Gate not turning on

My question is why is the M2 PMOS FET not turning on when Vchrg_ctrl is LOW? My problem is Vload never goes high to charge the Capacitor C1. I think I am missing something very silly here. Thank you ...
0
votes
2answers
44 views

P-Mos switch high side

I'm trying to switch P-Mos given that: Vcc > Vgs max Enable_output is 0V or 3V I'm switching both GND and VCC on purpose. 4. 8.4VR at 2uA ! The questions: When Q2 is off, what is Vgs at Qsp1? Is ...
1
vote
0answers
34 views

Common Source with Active Load

I'm trying to design this circuit using gm/Id method. I am already able to achieve the desired GBWP and Gain (this is just a simple example so I'm just trying to achieve both) but I'm having trouble ...
0
votes
1answer
49 views

NMOS/PMOS Transit Frequency

I found this video which shows how to plot the transit frequency in Cadence Virtuoso. But on another site, instead of using c_gg, the capacitance used was c_gs+c_gd for the ft equation. Which is ...
0
votes
2answers
72 views

Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
0
votes
1answer
49 views

Inversion Region

If one transistor in a circuit (say common source with active load) operate at the strong inversion region, should the rest of the transistor also operate on that same region? Or will it depend?
8
votes
2answers
1k views

Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
0
votes
1answer
49 views

Advantages/Disadvantages of high/low transconductance efficiency (gm/Id) of NMOS/PMOS

From here, it's said that a higher gm/Id results in lower current consumption (which is usually preferred in low power operation) But what other effects does a high gm/Id have? Will it have other ...
0
votes
1answer
76 views

NMOS/PMOS Saturation

If I recall correctly, saturation occurs if \$V_{GS}>V_{TH}\$ and \$V_{DS}>V_{Dsat}\$ for NMOS. But is there an upper limit for the voltage? Like, when does a transistor not saturate after ...
1
vote
2answers
76 views

Understanding Vgs absolute value

If a P-channel MOSFET have absolute maximum values: VDSS = -60 V Vgs = +/-20 V "refering to high switch side": Does this means we cannot switch the MOSFET by the gate driver that ties the gate to ...
0
votes
2answers
96 views

Resistor or no resistor between this IC and the pmos GATE?

I'm using this IC (https://www2.mouser.com/datasheet/2/609/ADM1270-878589.pdf). This IC controls the GATE of a pmos. I'm thinking about using this MOSFET (https://www2.mouser.com/datasheet/2/389/...
0
votes
3answers
115 views

How long do I have before my sensitive components get fried?

I'm using this IC (https://www2.mouser.com/datasheet/2/609/ADM1270-878589.pdf) to control the current and the voltage on some of the outputs of a PCB that controls the power to other PCBs, which have ...
0
votes
1answer
40 views

What would happen if there is no ground in a PMOS inverter?

I understand why when there is a ground you need a resistor or an NMOS but what if there were no ground at all and simply A goes high, B is 0, A goes low, current flows from VDD to B through the p ...
0
votes
1answer
224 views

Small signal equivalent circuit - MOSFET

Let's consider the following amplifier circuit: Now, if we would analyze small signal operation, we could represent the circuit with small signal equivalent: The part that bothers me is the PMOS ...
0
votes
2answers
75 views

P MOSFET turning on before gate threshold

I was simulating a P MOSFET, and for turning a P MOSFET on we need gate to Source voltage less then its threshold voltage. as per below simulation circuit at start VGS= 0, then there is no way mosfet ...
0
votes
1answer
302 views

Why are my p-channel mosfets cutting off in LTSpice even though Vgs is negative?

I'm running into a weird bug. Part of me thinks that it's LTSpice that's wrong, but that seems unlikely. I'm working on the circuit below, to be able to switch between feeding my voltage regulator ...
0
votes
1answer
74 views

Strange behaviour of ne555 + pmosfet circuit

I was a silent reader for a long time and could solve all the problems on my own, but this problem is really freaking me out. I was messing around until 3 AM today with this "feature" and still don't ...
2
votes
2answers
145 views

Slew Rate Adjustability

A SPST switch connects HB1 and HB2, to control a lamp connected to HB OUT. I am looking into modifying this circuit to make the slew rate adjustable when switching the output to VCC (around 12V). I ...
-2
votes
1answer
154 views

Using LTSpice to find the gain of NPN-PMOS folded cascode

I am trying to use LTSpice to find the gain of NPN-PMOS folded cascode. Below is the question prompt: In the problem, the parameter specifications are as follows: \begin{equation} \beta =100,\:V_A=5V\...
0
votes
1answer
66 views

Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached
0
votes
2answers
61 views

How to amplify the output of an on NMOS, connected to zero source voltage?

I am simulating a 3 transistor based XNOR cell using HSPICE. The circuit is shown in the picture. technology = 45nm Vdd=1.1v |Vth|=0.62v In the case of A=1 and B=1, the output is charged through ...
0
votes
1answer
158 views

Driving a 35V PMOS circuit from a Grounded/Floating input

I have an application where I need to switch a contactor on and off using a spare output of an off the shelf Battery Management System (BMS) The input is the signal coming from the BMS, while the ...
2
votes
5answers
971 views

Simple Mosfet driver

I need to switch 8 IRF9540 (P-Channel Mosfets) with about 32kHz (so 1 MOSFET about 4kHz) so that only one is On at one time. I thought about using the decade counter 4017 for this, and the 555 Timer ...
0
votes
1answer
33 views

Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
0
votes
1answer
185 views

Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?

Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs. For example, could not we just put the green construction in the place of red ...
0
votes
4answers
377 views

What is the use of pull-down networks in CMOS gates?

Below you can see the basic CMOS inverter. What I don't understand about this particular design is the purpose of the n-channel mosfet which is the part referred as pull-down network. What if we ...
0
votes
1answer
965 views

Diode-connected PMOS

Im currently a year 1 electrical engineering student. May I ask, for a diode-connected PMOS (gate connected to drain), why is |Vsd| = |Vgd| ?
-1
votes
0answers
38 views

half-bridge p-channel pwm

I need half-bridge that works 10% up to 100% (continuous), so I thought some driver for P-channel and N-chanel mosfet, equivalent to FAN3268. The FAN3268 is hard to find and expensive. Is there any ...
-1
votes
2answers
60 views

How did we find Vin in this CMOS?

Why did the lecturer decided that Vin is vGSn - vGSp + vDD , Why did he not go through the drain path and used vGDn and vGDp ?
0
votes
1answer
36 views

Find p-MOS frow battery switch application

I'm designing a switching circuit between USB (5V) and Battery (li-ion 3.7V) for a portable device, below is shown the schematic: As you can see if correctly chosen the P-MOS switches between USB ...
0
votes
2answers
57 views

Why is vo = 0 when VI(gate voltage) = 0. Also why is are both mosfets operating in the saturation region . Could someone explain why this is so?

According to the book Vo =0 when VI(gate-voltage) = 0. Why is that so? Why does the book also assume that both mosfets are operating in the saturation region? when VI = 0. I appreciate the help. ...
1
vote
1answer
74 views

Getting brownouts when using MCU controlled P-FET to switch power to another board

I have an MCU connected to a logic level P-FET(part no AO3401A). The source is wired to a 3.3V regulator that also feeds the MCU. The drain is wired to an LED and a header that connects to a second ...
0
votes
2answers
71 views

How to redesign the circuit such that the switching threshold is VDD/2.

he switching threshold is the input voltage where the output crosses VDD/2. I want to redesign the circuit such that the witching threshold is VDD/2.
-1
votes
1answer
73 views

Having trouble understanding CMOS and PMOS circuits [closed]

I'm in a digital logic class and I've got a solid grasp on Boolean algebra, SOP, POS, NAND, NOR gates, etc. Now I'm having trouble in understanding what NMOS, PMOS and CMOS transistors are and how ...
4
votes
2answers
661 views

Problems with DC analysis of a PMOS circuit

I'm beginning with electronics and I've picked up the book from Donald. A. Neamen - Microelectronics. I'm stuck at a simple example of DC analysis for this PMOS circuit. simulate this circuit – ...
6
votes
1answer
971 views

Pull up resistor on P-MOSFET gate. Not working

I am building a battery-powered datalogger that will communicate using cellular signal, based on the ATSAMD21 microcontroller and the SIM5320 cellular modem. To save power, an outside timer ...
4
votes
1answer
155 views

Li-ion power supply with a charger, a booster, and a pMOS high side switch

I am designing a circuit board for a small mobile robot and there is a problem with the power supply. The circuit is powered by a 1-cell Li-ion battery (VBAT) and includes a charger (MCP73831/2), a ...
0
votes
0answers
75 views

Soft latch on/off button simulation

I am trying to simulated in pspice a soft latch on/off circuit but it is not working as expected, even if I double check the implementation. Can someone explain to me why the voltage on the probe is 0....