Questions tagged [pmos]

A p-channel metal-oxide semiconductor (pMOS) transistor which has has p-type carriers used in the channel. The channel is established by a negative voltage on the gate which inverts the substrate (NWell) under the gate which turns the device on. The term may also be used to describe logic circuits built around pMOS transistors.

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voltage divider driving PMOS with slow turn-off time

I have a voltage divider that is driving the gate of a high side PMOS switch. The voltage divider turns the PMOS on once the NMOS is turned on by a 5v logic controller. The PMOS turns on ...
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35 views

Contact on substrate of a MOSFET

Why do we want to have an ohmic contact on a substrate terminal of mosfet? What would happen if we used schottky contact instead?
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31 views

Voltage drop at gate of pmos (or nmos)

Sorry if this question has been asked before, I've tried looking through google and Stack Exchange and I can't seem to find the answer. Resistors on the gate (R3 on the picture) are usually in the K ...
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35 views

PMOS device in low-side switch

For most low-side switches I've seen, an NMOS device is used. I am wondering, is it not possible to use a PMOS device in a low-side switch?
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90 views

Multiplexed LED column driver MOSFET doesn't fully turn off without a resistor parallel to the LEDS

I have a board with a 16x10 led matrix. The columns are switched with DMG9933 Dual P mosfets. The rows are driven with a constant current led driver ST STP16CPC26 (similar to TI TLC5956) I noticed ...
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74 views

Circuit to save one battery when another battery is present

I have a battery powered system and I want to preserve the test batteries during setup and calibration. I want the system to use the setup batteries if they are present and use the test batteries if ...
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29 views

Understanding PMOS's and NMOS's

The problem says solve assuming VI = 0, +2.5V, and -2.5V. I know that if VI = -2.5V the MOSFET's are in cutoff and that VDS = 0. and IDP and IDN will = 0, but would V0 also = 0? If VI = 0 the ...
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39 views

Bandwidth of voltage divider with PMOS switch

Planning to measure (varying under switching e-bike load) voltage from a battery. To step down the voltage panning to use a voltage divider and buffer the output to an ADC via an op-amp. To ...
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65 views

What is the effect on propagation delay when we have a CMOS circuit with multiple transistors connected in series?

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of ...
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75 views

nanoPower comparator driving MOSFET not providing expected output

I built the following circuit to charge a large capacitor from a low power source before switching the load: simulate this circuit – Schematic created using CircuitLab MAX9064, MCH3484, ...
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22 views

Output voltage for pmos with Vt= -0.8

simulate this circuit – Schematic created using CircuitLab What is VX? I am having confusion between 2.8 V or 3 V. Thank you for your help.
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90 views

Op amp with pmos

simulate this circuit – Schematic created using CircuitLab What is the gain (Vout/Vin) for the schematic?
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Mixing Reverse Polarity Protection PMOS with a Piezo Element

I have a circuit that powers some leds when vibrations are detected. I am trying to integrate a PMOS for reverse polarity battery protection. When the PMOS is present the circuit simulation fails as ...
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31 views

PMOS Drain-Source Short at Turn-On

In the attached image, without C1 & C2 (used only as de-cap) mounted, when 24V is given at TP1 and nMOS (Q1) is turned ON, the circuit works fine and I get 24 V at TP3. But when C1 & C2 are ...
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1answer
64 views

Calculating resistors for an optocoupler controlling a pmos

I want to use a pmos (SI7157DP-T1-GE3, datasheet) as switch - controlled by an optocoupler (TLP291(V4GBTP,SE, datasheet) which is controlled by a teensy 3.6 (3V3 output voltage). Now I'm calculating ...
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63 views

Design Vbat system with PMOS to keep RTC

Since I'm using an MCU without internal Vbat system (STM32L0 series), I've read the "How to design a Vbat on STM32L0/L1 series" from STMicroelectronics to keep the internal RTC. I would like to ...
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39 views

CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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80 views

LTSPICE Model Parameters of P-MOSFET

I am trying to simulate a circuit including TSM500P02CX P-MOSFET. The manufacturer of the MOSFET doesn't provide SPICE Model, so ...
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137 views

Reverse Current Protection using two PMOS in back to back configuration

I am working on a circuit that needs reverse current protection. Back to back mosfet configuration has been suggested by many people, and it seems to make sense at the beginning. But after I built my ...
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2answers
67 views

How to calculate the maximal temperature of a transistor

let's assume I have this transistor (IRFR640): https://www.infineon.com/dgdl/Infineon-IRFR6215-DS-v01_02-EN.pdf?fileId=5546d462533600a40153563595592114 $$R_{DS(ON)} =0,295 \Omega $$ $$V_{max} = -150V$...
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199 views

TSMC model for lt spice simulation [closed]

From where to download the tsmc model file for nmos(slow,fast,typical) and pmos (slow,fast,typical)?
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93 views

Difference between body, bulk and substrate?

I have a pretty fundamental question related MOSFET devices. I am confused about whether the terms body, bulk and substrate are all just names for the same thing or are there actually some differences ...
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103 views

LTSpice - PMOS Gate not turning on

My question is why is the M2 PMOS FET not turning on when Vchrg_ctrl is LOW? My problem is Vload never goes high to charge the Capacitor C1. I think I am missing something very silly here. Thank you ...
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56 views

P-Mos switch high side

I'm trying to switch P-Mos given that: Vcc > Vgs max Enable_output is 0V or 3V I'm switching both GND and VCC on purpose. 4. 8.4VR at 2uA ! The questions: When Q2 is off, what is Vgs at Qsp1? Is ...
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51 views

Common Source with Active Load

I'm trying to design this circuit using gm/Id method. I am already able to achieve the desired GBWP and Gain (this is just a simple example so I'm just trying to achieve both) but I'm having trouble ...
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81 views

NMOS/PMOS Transit Frequency

I found this video which shows how to plot the transit frequency in Cadence Virtuoso. But on another site, instead of using c_gg, the capacitance used was c_gs+c_gd for the ft equation. Which is ...
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94 views

Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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51 views

Inversion Region

If one transistor in a circuit (say common source with active load) operate at the strong inversion region, should the rest of the transistor also operate on that same region? Or will it depend?
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1k views

Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
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75 views

Advantages/Disadvantages of high/low transconductance efficiency (gm/Id) of NMOS/PMOS

From here, it's said that a higher gm/Id results in lower current consumption (which is usually preferred in low power operation) But what other effects does a high gm/Id have? Will it have other ...
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105 views

NMOS/PMOS Saturation

If I recall correctly, saturation occurs if \$V_{GS}>V_{TH}\$ and \$V_{DS}>V_{Dsat}\$ for NMOS. But is there an upper limit for the voltage? Like, when does a transistor not saturate after ...
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91 views

Understanding Vgs absolute value

If a P-channel MOSFET have absolute maximum values: VDSS = -60 V Vgs = +/-20 V "refering to high switch side": Does this means we cannot switch the MOSFET by the gate driver that ties the gate to ...
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102 views

Resistor or no resistor between this IC and the pmos GATE?

I'm using this IC (https://www2.mouser.com/datasheet/2/609/ADM1270-878589.pdf). This IC controls the GATE of a pmos. I'm thinking about using this MOSFET (https://www2.mouser.com/datasheet/2/389/...
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117 views

How long do I have before my sensitive components get fried?

I'm using this IC (https://www2.mouser.com/datasheet/2/609/ADM1270-878589.pdf) to control the current and the voltage on some of the outputs of a PCB that controls the power to other PCBs, which have ...
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41 views

What would happen if there is no ground in a PMOS inverter?

I understand why when there is a ground you need a resistor or an NMOS but what if there were no ground at all and simply A goes high, B is 0, A goes low, current flows from VDD to B through the p ...
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270 views

Small signal equivalent circuit - MOSFET

Let's consider the following amplifier circuit: Now, if we would analyze small signal operation, we could represent the circuit with small signal equivalent: The part that bothers me is the PMOS ...
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2answers
76 views

P MOSFET turning on before gate threshold

I was simulating a P MOSFET, and for turning a P MOSFET on we need gate to Source voltage less then its threshold voltage. as per below simulation circuit at start VGS= 0, then there is no way mosfet ...
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1answer
473 views

Why are my p-channel mosfets cutting off in LTSpice even though Vgs is negative?

I'm running into a weird bug. Part of me thinks that it's LTSpice that's wrong, but that seems unlikely. I'm working on the circuit below, to be able to switch between feeding my voltage regulator ...
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1answer
77 views

Strange behaviour of ne555 + pmosfet circuit

I was a silent reader for a long time and could solve all the problems on my own, but this problem is really freaking me out. I was messing around until 3 AM today with this "feature" and still don't ...
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2answers
175 views

Slew Rate Adjustability

A SPST switch connects HB1 and HB2, to control a lamp connected to HB OUT. I am looking into modifying this circuit to make the slew rate adjustable when switching the output to VCC (around 12V). I ...
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1answer
219 views

Using LTSpice to find the gain of NPN-PMOS folded cascode

I am trying to use LTSpice to find the gain of NPN-PMOS folded cascode. Below is the question prompt: In the problem, the parameter specifications are as follows: \begin{equation} \beta =100,\:V_A=5V\...
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1answer
73 views

Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached
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2answers
63 views

How to amplify the output of an on NMOS, connected to zero source voltage?

I am simulating a 3 transistor based XNOR cell using HSPICE. The circuit is shown in the picture. technology = 45nm Vdd=1.1v |Vth|=0.62v In the case of A=1 and B=1, the output is charged through ...
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1answer
192 views

Driving a 35V PMOS circuit from a Grounded/Floating input

I have an application where I need to switch a contactor on and off using a spare output of an off the shelf Battery Management System (BMS) The input is the signal coming from the BMS, while the ...
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5answers
1k views

Simple Mosfet driver

I need to switch 8 IRF9540 (P-Channel Mosfets) with about 32kHz (so 1 MOSFET about 4kHz) so that only one is On at one time. I thought about using the decade counter 4017 for this, and the 555 Timer ...
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1answer
34 views

Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
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1answer
302 views

Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?

Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs. For example, could not we just put the green construction in the place of red ...
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4answers
446 views

What is the use of pull-down networks in CMOS gates?

Below you can see the basic CMOS inverter. What I don't understand about this particular design is the purpose of the n-channel mosfet which is the part referred as pull-down network. What if we ...
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1k views

Diode-connected PMOS

Im currently a year 1 electrical engineering student. May I ask, for a diode-connected PMOS (gate connected to drain), why is |Vsd| = |Vgd| ?
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How did we find Vin in this CMOS?

Why did the lecturer decided that Vin is vGSn - vGSp + vDD , Why did he not go through the drain path and used vGDn and vGDp ?